1 From cf93418a4bd5e69f069a65da92537bd4d6191223 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:29:51 +0100
4 Subject: [PATCH 54/57] DMA: ralink: add rt2880 dma engine
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/dma/Kconfig | 6 +
9 drivers/dma/Makefile | 1 +
10 drivers/dma/dmaengine.c | 26 ++
11 drivers/dma/ralink-gdma.c | 577 +++++++++++++++++++++++++++++++++++++++++++++
12 include/linux/dmaengine.h | 1 +
13 5 files changed, 611 insertions(+)
14 create mode 100644 drivers/dma/ralink-gdma.c
16 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
17 index 605b016..a9b31ff 100644
18 --- a/drivers/dma/Kconfig
19 +++ b/drivers/dma/Kconfig
20 @@ -351,6 +351,12 @@ config MOXART_DMA
22 Enable support for the MOXA ART SoC DMA controller.
25 + tristate "RALINK DMA support"
26 + depends on RALINK && SOC_MT7620
28 + select DMA_VIRTUAL_CHANNELS
33 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
34 index a029d0f4..419ccc2 100644
35 --- a/drivers/dma/Makefile
36 +++ b/drivers/dma/Makefile
37 @@ -44,3 +44,4 @@ obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
38 obj-$(CONFIG_TI_CPPI41) += cppi41.o
39 obj-$(CONFIG_K3_DMA) += k3dma.o
40 obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
41 +obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o
42 diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
43 index ed610b4..cc11e0b 100644
44 --- a/drivers/dma/dmaengine.c
45 +++ b/drivers/dma/dmaengine.c
46 @@ -564,6 +564,32 @@ struct dma_chan *dma_get_any_slave_channel(struct dma_device *device)
47 EXPORT_SYMBOL_GPL(dma_get_any_slave_channel);
50 + * dma_request_slave_channel - try to get specific channel exclusively
51 + * @chan: target channel
53 +struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
57 + /* lock against __dma_request_channel */
58 + mutex_lock(&dma_list_mutex);
60 + if (chan->client_count == 0) {
61 + err = dma_chan_get(chan);
63 + pr_debug("%s: failed to get %s: (%d)\n",
64 + __func__, dma_chan_name(chan), err);
68 + mutex_unlock(&dma_list_mutex);
72 +EXPORT_SYMBOL_GPL(dma_get_slave_channel);
76 * __dma_request_channel - try to allocate an exclusive channel
77 * @mask: capabilities that the channel must satisfy
78 * @fn: optional callback to disposition available channels
79 diff --git a/drivers/dma/ralink-gdma.c b/drivers/dma/ralink-gdma.c
81 index 0000000..2c3cace
83 +++ b/drivers/dma/ralink-gdma.c
86 + * Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
87 + * GDMA4740 DMAC support
89 + * This program is free software; you can redistribute it and/or modify it
90 + * under the terms of the GNU General Public License as published by the
91 + * Free Software Foundation; either version 2 of the License, or (at your
92 + * option) any later version.
94 + * You should have received a copy of the GNU General Public License along
95 + * with this program; if not, write to the Free Software Foundation, Inc.,
96 + * 675 Mass Ave, Cambridge, MA 02139, USA.
100 +#include <linux/dmaengine.h>
101 +#include <linux/dma-mapping.h>
102 +#include <linux/err.h>
103 +#include <linux/init.h>
104 +#include <linux/list.h>
105 +#include <linux/module.h>
106 +#include <linux/platform_device.h>
107 +#include <linux/slab.h>
108 +#include <linux/spinlock.h>
109 +#include <linux/irq.h>
110 +#include <linux/of_dma.h>
112 +#include "virt-dma.h"
114 +#define GDMA_NR_CHANS 16
116 +#define GDMA_REG_SRC_ADDR(x) (0x00 + (x) * 0x10)
117 +#define GDMA_REG_DST_ADDR(x) (0x04 + (x) * 0x10)
119 +#define GDMA_REG_CTRL0(x) (0x08 + (x) * 0x10)
120 +#define GDMA_REG_CTRL0_TX_MASK 0xffff
121 +#define GDMA_REG_CTRL0_TX_SHIFT 16
122 +#define GDMA_REG_CTRL0_CURR_MASK 0xff
123 +#define GDMA_REG_CTRL0_CURR_SHIFT 8
124 +#define GDMA_REG_CTRL0_SRC_ADDR_FIXED BIT(7)
125 +#define GDMA_REG_CTRL0_DST_ADDR_FIXED BIT(6)
126 +#define GDMA_REG_CTRL0_BURST_MASK 0x7
127 +#define GDMA_REG_CTRL0_BURST_SHIFT 3
128 +#define GDMA_REG_CTRL0_DONE_INT BIT(2)
129 +#define GDMA_REG_CTRL0_ENABLE BIT(1)
130 +#define GDMA_REG_CTRL0_HW_MODE 0
132 +#define GDMA_REG_CTRL1(x) (0x0c + (x) * 0x10)
133 +#define GDMA_REG_CTRL1_SEG_MASK 0xf
134 +#define GDMA_REG_CTRL1_SEG_SHIFT 22
135 +#define GDMA_REG_CTRL1_REQ_MASK 0x3f
136 +#define GDMA_REG_CTRL1_SRC_REQ_SHIFT 16
137 +#define GDMA_REG_CTRL1_DST_REQ_SHIFT 8
138 +#define GDMA_REG_CTRL1_CONTINOUS BIT(14)
139 +#define GDMA_REG_CTRL1_NEXT_MASK 0x1f
140 +#define GDMA_REG_CTRL1_NEXT_SHIFT 3
141 +#define GDMA_REG_CTRL1_COHERENT BIT(2)
142 +#define GDMA_REG_CTRL1_FAIL BIT(1)
143 +#define GDMA_REG_CTRL1_MASK BIT(0)
145 +#define GDMA_REG_UNMASK_INT 0x200
146 +#define GDMA_REG_DONE_INT 0x204
148 +#define GDMA_REG_GCT 0x220
149 +#define GDMA_REG_GCT_CHAN_MASK 0x3
150 +#define GDMA_REG_GCT_CHAN_SHIFT 3
151 +#define GDMA_REG_GCT_VER_MASK 0x3
152 +#define GDMA_REG_GCT_VER_SHIFT 1
153 +#define GDMA_REG_GCT_ARBIT_RR BIT(0)
155 +enum gdma_dma_transfer_size {
156 + GDMA_TRANSFER_SIZE_4BYTE = 0,
157 + GDMA_TRANSFER_SIZE_8BYTE = 1,
158 + GDMA_TRANSFER_SIZE_16BYTE = 2,
159 + GDMA_TRANSFER_SIZE_32BYTE = 3,
162 +struct gdma_dma_sg {
167 +struct gdma_dma_desc {
168 + struct virt_dma_desc vdesc;
170 + enum dma_transfer_direction direction;
173 + unsigned int num_sgs;
174 + struct gdma_dma_sg sg[];
177 +struct gdma_dmaengine_chan {
178 + struct virt_dma_chan vchan;
181 + dma_addr_t fifo_addr;
182 + unsigned int transfer_shift;
184 + struct gdma_dma_desc *desc;
185 + unsigned int next_sg;
188 +struct gdma_dma_dev {
189 + struct dma_device ddev;
190 + void __iomem *base;
193 + struct gdma_dmaengine_chan chan[GDMA_NR_CHANS];
196 +static struct gdma_dma_dev *gdma_dma_chan_get_dev(
197 + struct gdma_dmaengine_chan *chan)
199 + return container_of(chan->vchan.chan.device, struct gdma_dma_dev,
203 +static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c)
205 + return container_of(c, struct gdma_dmaengine_chan, vchan.chan);
208 +static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc)
210 + return container_of(vdesc, struct gdma_dma_desc, vdesc);
213 +static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
216 + return readl(dma_dev->base + reg);
219 +static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
220 + unsigned reg, uint32_t val)
222 + //printk("gdma --> %p = 0x%08X\n", dma_dev->base + reg, val);
223 + writel(val, dma_dev->base + reg);
226 +static inline void gdma_dma_write_mask(struct gdma_dma_dev *dma_dev,
227 + unsigned int reg, uint32_t val, uint32_t mask)
231 + tmp = gdma_dma_read(dma_dev, reg);
234 + gdma_dma_write(dma_dev, reg, tmp);
237 +static struct gdma_dma_desc *gdma_dma_alloc_desc(unsigned int num_sgs)
239 + return kzalloc(sizeof(struct gdma_dma_desc) +
240 + sizeof(struct gdma_dma_sg) * num_sgs, GFP_ATOMIC);
243 +static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst)
246 + return GDMA_TRANSFER_SIZE_4BYTE;
247 + else if (maxburst <= 15)
248 + return GDMA_TRANSFER_SIZE_8BYTE;
249 + else if (maxburst <= 31)
250 + return GDMA_TRANSFER_SIZE_16BYTE;
252 + return GDMA_TRANSFER_SIZE_32BYTE;
255 +static int gdma_dma_slave_config(struct dma_chan *c,
256 + const struct dma_slave_config *config)
258 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
259 + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
260 + enum gdma_dma_transfer_size transfer_size;
262 + uint32_t ctrl0, ctrl1;
264 + switch (config->direction) {
265 + case DMA_MEM_TO_DEV:
266 + ctrl1 = 32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
267 + ctrl1 |= config->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT;
268 + flags = GDMA_REG_CTRL0_DST_ADDR_FIXED;
269 + transfer_size = gdma_dma_maxburst(config->dst_maxburst);
270 + chan->fifo_addr = config->dst_addr;
273 + case DMA_DEV_TO_MEM:
274 + ctrl1 = config->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
275 + ctrl1 |= 32 << GDMA_REG_CTRL1_DST_REQ_SHIFT;
276 + flags = GDMA_REG_CTRL0_SRC_ADDR_FIXED;
277 + transfer_size = gdma_dma_maxburst(config->src_maxburst);
278 + chan->fifo_addr = config->src_addr;
285 + chan->transfer_shift = 1 + transfer_size;
287 + ctrl0 = flags | GDMA_REG_CTRL0_HW_MODE;
288 + ctrl0 |= GDMA_REG_CTRL0_DONE_INT;
290 + ctrl1 &= ~(GDMA_REG_CTRL1_NEXT_MASK << GDMA_REG_CTRL1_NEXT_SHIFT);
291 + ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
292 + ctrl1 |= GDMA_REG_CTRL1_FAIL;
293 + ctrl1 &= ~GDMA_REG_CTRL1_CONTINOUS;
294 + gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
295 + gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
300 +static int gdma_dma_terminate_all(struct dma_chan *c)
302 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
303 + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
304 + unsigned long flags;
307 + spin_lock_irqsave(&chan->vchan.lock, flags);
308 + gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
309 + GDMA_REG_CTRL0_ENABLE);
311 + vchan_get_all_descriptors(&chan->vchan, &head);
312 + spin_unlock_irqrestore(&chan->vchan.lock, flags);
314 + vchan_dma_desc_free_list(&chan->vchan, &head);
319 +static int gdma_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
322 + struct dma_slave_config *config = (struct dma_slave_config *)arg;
325 + case DMA_SLAVE_CONFIG:
326 + return gdma_dma_slave_config(chan, config);
327 + case DMA_TERMINATE_ALL:
328 + return gdma_dma_terminate_all(chan);
334 +static int gdma_dma_start_transfer(struct gdma_dmaengine_chan *chan)
336 + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
337 + dma_addr_t src_addr, dst_addr;
338 + struct virt_dma_desc *vdesc;
339 + struct gdma_dma_sg *sg;
341 + gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
342 + GDMA_REG_CTRL0_ENABLE);
345 + vdesc = vchan_next_desc(&chan->vchan);
348 + chan->desc = to_gdma_dma_desc(vdesc);
352 + if (chan->next_sg == chan->desc->num_sgs)
355 + sg = &chan->desc->sg[chan->next_sg];
357 + if (chan->desc->direction == DMA_MEM_TO_DEV) {
358 + src_addr = sg->addr;
359 + dst_addr = chan->fifo_addr;
361 + src_addr = chan->fifo_addr;
362 + dst_addr = sg->addr;
364 + gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
365 + gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
366 + gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id),
367 + (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | GDMA_REG_CTRL0_ENABLE,
368 + GDMA_REG_CTRL0_TX_MASK << GDMA_REG_CTRL0_TX_SHIFT);
370 + gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL1(chan->id), 0, GDMA_REG_CTRL1_MASK);
375 +static void gdma_dma_chan_irq(struct gdma_dmaengine_chan *chan)
377 + spin_lock(&chan->vchan.lock);
379 + if (chan->desc && chan->desc->cyclic) {
380 + vchan_cyclic_callback(&chan->desc->vdesc);
382 + if (chan->next_sg == chan->desc->num_sgs) {
384 + vchan_cookie_complete(&chan->desc->vdesc);
388 + gdma_dma_start_transfer(chan);
389 + spin_unlock(&chan->vchan.lock);
392 +static irqreturn_t gdma_dma_irq(int irq, void *devid)
394 + struct gdma_dma_dev *dma_dev = devid;
395 + uint32_t unmask, done;
398 + unmask = gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT);
399 + gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, unmask);
400 + done = gdma_dma_read(dma_dev, GDMA_REG_DONE_INT);
402 + for (i = 0; i < GDMA_NR_CHANS; ++i)
404 + gdma_dma_chan_irq(&dma_dev->chan[i]);
405 + gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, done);
407 + return IRQ_HANDLED;
410 +static void gdma_dma_issue_pending(struct dma_chan *c)
412 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
413 + unsigned long flags;
415 + spin_lock_irqsave(&chan->vchan.lock, flags);
416 + if (vchan_issue_pending(&chan->vchan) && !chan->desc)
417 + gdma_dma_start_transfer(chan);
418 + spin_unlock_irqrestore(&chan->vchan.lock, flags);
421 +static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg(
422 + struct dma_chan *c, struct scatterlist *sgl,
423 + unsigned int sg_len, enum dma_transfer_direction direction,
424 + unsigned long flags, void *context)
426 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
427 + struct gdma_dma_desc *desc;
428 + struct scatterlist *sg;
431 + desc = gdma_dma_alloc_desc(sg_len);
435 + for_each_sg(sgl, sg, sg_len, i) {
436 + desc->sg[i].addr = sg_dma_address(sg);
437 + desc->sg[i].len = sg_dma_len(sg);
440 + desc->num_sgs = sg_len;
441 + desc->direction = direction;
442 + desc->cyclic = false;
444 + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
447 +static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic(
448 + struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
449 + size_t period_len, enum dma_transfer_direction direction,
450 + unsigned long flags, void *context)
452 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
453 + struct gdma_dma_desc *desc;
454 + unsigned int num_periods, i;
456 + if (buf_len % period_len)
459 + num_periods = buf_len / period_len;
461 + desc = gdma_dma_alloc_desc(num_periods);
465 + for (i = 0; i < num_periods; i++) {
466 + desc->sg[i].addr = buf_addr;
467 + desc->sg[i].len = period_len;
468 + buf_addr += period_len;
471 + desc->num_sgs = num_periods;
472 + desc->direction = direction;
473 + desc->cyclic = true;
475 + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
478 +static size_t gdma_dma_desc_residue(struct gdma_dmaengine_chan *chan,
479 + struct gdma_dma_desc *desc, unsigned int next_sg)
481 + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
482 + unsigned int residue, count;
487 + for (i = next_sg; i < desc->num_sgs; i++)
488 + residue += desc->sg[i].len;
490 + if (next_sg != 0) {
491 + count = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
492 + count >>= GDMA_REG_CTRL0_CURR_SHIFT;
493 + count &= GDMA_REG_CTRL0_CURR_MASK;
494 + residue += count << chan->transfer_shift;
500 +static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
501 + dma_cookie_t cookie, struct dma_tx_state *state)
503 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
504 + struct virt_dma_desc *vdesc;
505 + enum dma_status status;
506 + unsigned long flags;
508 + status = dma_cookie_status(c, cookie, state);
509 + if (status == DMA_SUCCESS || !state)
512 + spin_lock_irqsave(&chan->vchan.lock, flags);
513 + vdesc = vchan_find_desc(&chan->vchan, cookie);
514 + if (cookie == chan->desc->vdesc.tx.cookie) {
515 + state->residue = gdma_dma_desc_residue(chan, chan->desc,
517 + } else if (vdesc) {
518 + state->residue = gdma_dma_desc_residue(chan,
519 + to_gdma_dma_desc(vdesc), 0);
521 + state->residue = 0;
523 + spin_unlock_irqrestore(&chan->vchan.lock, flags);
528 +static int gdma_dma_alloc_chan_resources(struct dma_chan *c)
533 +static void gdma_dma_free_chan_resources(struct dma_chan *c)
535 + vchan_free_chan_resources(to_virt_chan(c));
538 +static void gdma_dma_desc_free(struct virt_dma_desc *vdesc)
540 + kfree(container_of(vdesc, struct gdma_dma_desc, vdesc));
543 +static struct dma_chan *
544 +of_dma_xlate_by_chan_id(struct of_phandle_args *dma_spec,
545 + struct of_dma *ofdma)
547 + struct gdma_dma_dev *dma_dev = ofdma->of_dma_data;
548 + unsigned int request = dma_spec->args[0];
550 + if (request >= GDMA_NR_CHANS)
553 + return dma_get_slave_channel(&(dma_dev->chan[request].vchan.chan));
556 +static int gdma_dma_probe(struct platform_device *pdev)
558 + struct gdma_dmaengine_chan *chan;
559 + struct gdma_dma_dev *dma_dev;
560 + struct dma_device *dd;
562 + struct resource *res;
568 + dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev), GFP_KERNEL);
572 + dd = &dma_dev->ddev;
574 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
575 + dma_dev->base = devm_ioremap_resource(&pdev->dev, res);
576 + if (IS_ERR(dma_dev->base))
577 + return PTR_ERR(dma_dev->base);
579 + dma_cap_set(DMA_SLAVE, dd->cap_mask);
580 + dma_cap_set(DMA_CYCLIC, dd->cap_mask);
581 + dd->device_alloc_chan_resources = gdma_dma_alloc_chan_resources;
582 + dd->device_free_chan_resources = gdma_dma_free_chan_resources;
583 + dd->device_tx_status = gdma_dma_tx_status;
584 + dd->device_issue_pending = gdma_dma_issue_pending;
585 + dd->device_prep_slave_sg = gdma_dma_prep_slave_sg;
586 + dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic;
587 + dd->device_control = gdma_dma_control;
588 + dd->dev = &pdev->dev;
589 + dd->chancnt = GDMA_NR_CHANS;
590 + INIT_LIST_HEAD(&dd->channels);
592 + for (i = 0; i < dd->chancnt; i++) {
593 + chan = &dma_dev->chan[i];
595 + chan->vchan.desc_free = gdma_dma_desc_free;
596 + vchan_init(&chan->vchan, dd);
599 + ret = dma_async_device_register(dd);
603 + ret = of_dma_controller_register(pdev->dev.of_node,
604 + of_dma_xlate_by_chan_id, dma_dev);
606 + goto err_unregister;
608 + irq = platform_get_irq(pdev, 0);
609 + ret = request_irq(irq, gdma_dma_irq, 0, dev_name(&pdev->dev), dma_dev);
611 + goto err_unregister;
613 + gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, 0);
614 + gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, BIT(dd->chancnt) - 1);
616 + gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
617 + dev_info(&pdev->dev, "revision: %d, channels: %d\n",
618 + (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
619 + 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) & GDMA_REG_GCT_CHAN_MASK));
620 + platform_set_drvdata(pdev, dma_dev);
622 + gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR);
627 + dma_async_device_unregister(dd);
631 +static int gdma_dma_remove(struct platform_device *pdev)
633 + struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev);
634 + int irq = platform_get_irq(pdev, 0);
636 + free_irq(irq, dma_dev);
637 + of_dma_controller_free(pdev->dev.of_node);
638 + dma_async_device_unregister(&dma_dev->ddev);
643 +static const struct of_device_id gdma_of_match_table[] = {
644 + { .compatible = "ralink,rt2880-gdma" },
648 +static struct platform_driver gdma_dma_driver = {
649 + .probe = gdma_dma_probe,
650 + .remove = gdma_dma_remove,
652 + .name = "gdma-rt2880",
653 + .owner = THIS_MODULE,
654 + .of_match_table = gdma_of_match_table,
657 +module_platform_driver(gdma_dma_driver);
659 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
660 +MODULE_DESCRIPTION("GDMA4740 DMA driver");
661 +MODULE_LICENSE("GPLv2");
662 diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
663 index c5c92d5..482131e 100644
664 --- a/include/linux/dmaengine.h
665 +++ b/include/linux/dmaengine.h
666 @@ -1072,6 +1072,7 @@ struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
668 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
669 void dma_release_channel(struct dma_chan *chan);
670 +struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
672 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)