1 --- a/drivers/spi/spi-rt2880.c
2 +++ b/drivers/spi/spi-rt2880.c
4 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
6 #define DRIVER_NAME "spi-rt2880"
7 -/* only one slave is supported*/
8 -#define RALINK_NUM_CHIPSELECTS 1
10 #define RALINK_SPI_WAIT_MAX_LOOP 2000
12 -#define RAMIPS_SPI_STAT 0x00
13 -#define RAMIPS_SPI_CFG 0x10
14 -#define RAMIPS_SPI_CTL 0x14
15 -#define RAMIPS_SPI_DATA 0x20
16 -#define RAMIPS_SPI_FIFO_STAT 0x38
17 +#define RAMIPS_SPI_DEV_OFFSET 0x40
19 +#define RAMIPS_SPI_STAT(cs) (0x00 + (cs * RAMIPS_SPI_DEV_OFFSET))
20 +#define RAMIPS_SPI_CFG(cs) (0x10 + (cs * RAMIPS_SPI_DEV_OFFSET))
21 +#define RAMIPS_SPI_CTL(cs) (0x14 + (cs * RAMIPS_SPI_DEV_OFFSET))
22 +#define RAMIPS_SPI_DATA(cs) (0x20 + (cs * RAMIPS_SPI_DEV_OFFSET))
23 +#define RAMIPS_SPI_FIFO_STAT(cs) (0x38 + (cs * RAMIPS_SPI_DEV_OFFSET))
24 +#define RAMIPS_SPI_ARBITER 0xF0
26 /* SPISTAT register bit field */
27 #define SPISTAT_BUSY BIT(0)
29 /* SPIFIFOSTAT register bit field */
30 #define SPIFIFOSTAT_TXFULL BIT(17)
32 +#define SPICTL_ARB_EN BIT(31)
33 +#define SPI1_POR BIT(1)
34 +#define SPI0_POR BIT(0)
36 #define MT7621_SPI_TRANS 0x00
37 #define SPITRANS_BUSY BIT(16)
38 #define MT7621_SPI_OPCODE 0x04
40 #define MT7621_SPI_MASTER 0x28
41 #define MT7621_SPI_SPACE 0x3c
43 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
47 struct rt2880_spi_ops {
48 void (*init_hw)(struct rt2880_spi *rs);
49 - void (*set_cs)(struct rt2880_spi *rs, int enable);
50 + void (*set_cs)(struct spi_device *spi, int enable);
51 int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
52 unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
57 @@ -141,6 +149,7 @@ static inline void rt2880_spi_clrbits(st
59 static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
61 + int cs = spi->chip_select;
62 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
65 @@ -168,9 +177,9 @@ static int rt2880_spi_baudrate_set(struc
66 prescale = ilog2(rate / 2);
67 dev_dbg(&spi->dev, "prescale:%u\n", prescale);
69 - reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
70 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG(cs));
71 reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
72 - rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
73 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs), reg);
77 @@ -194,7 +203,8 @@ rt2880_spi_setup_transfer(struct spi_dev
79 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
80 unsigned int speed = spi->max_speed_hz;
82 + int rc, cs = spi->chip_select;
85 if ((t != NULL) && t->speed_hz)
87 @@ -206,19 +216,61 @@ rt2880_spi_setup_transfer(struct spi_dev
91 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG(cs));
93 + reg = (reg & ~SPICFG_MSBFIRST);
94 + if (!(spi->mode & SPI_LSB_FIRST))
95 + reg |= SPICFG_MSBFIRST;
97 + reg = (reg & ~(SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING |SPICFG_TXCLKEDGE_FALLING));
98 + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
100 + reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
103 + reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
106 + reg |= SPICFG_RXCLKEDGE_FALLING;
109 + reg |= SPICFG_TXCLKEDGE_FALLING;
113 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs), reg);
115 + reg = SPICTL_ARB_EN;
116 + if (spi->mode & SPI_CS_HIGH) {
127 + rt2880_spi_write(rs, RAMIPS_SPI_ARBITER, reg);
132 -static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
133 +static void rt2880_spi_set_cs(struct spi_device *spi, int enable)
135 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
136 + int cs = spi->chip_select;
139 - rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
140 + rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);
142 - rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
143 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);
146 -static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
147 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
149 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
150 u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
153 @@ -228,14 +280,16 @@ static void mt7621_spi_set_cs(struct rt2
154 rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
157 -static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
158 +static inline int rt2880_spi_wait_till_ready(struct spi_device *spi)
160 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
161 + int cs = spi->chip_select;
164 for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
167 - status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
168 + status = rt2880_spi_read(rs, RAMIPS_SPI_STAT(cs));
169 if ((status & SPISTAT_BUSY) == 0)
172 @@ -246,8 +300,9 @@ static inline int rt2880_spi_wait_till_r
176 -static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
177 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
179 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
182 for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
183 @@ -268,6 +323,7 @@ static unsigned int
184 rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
186 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
187 + int cs = spi->chip_select;
189 u8 *rx = xfer->rx_buf;
190 const u8 *tx = xfer->tx_buf;
191 @@ -279,9 +335,9 @@ rt2880_spi_write_read(struct spi_device
194 for (count = 0; count < xfer->len; count++) {
195 - rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
196 - rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
197 - err = rt2880_spi_wait_till_ready(rs);
198 + rt2880_spi_write(rs, RAMIPS_SPI_DATA(cs), tx[count]);
199 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_STARTWR);
200 + err = rt2880_spi_wait_till_ready(spi);
202 dev_err(&spi->dev, "TX failed, err=%d\n", err);
204 @@ -291,13 +347,13 @@ rt2880_spi_write_read(struct spi_device
207 for (count = 0; count < xfer->len; count++) {
208 - rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
209 - err = rt2880_spi_wait_till_ready(rs);
210 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_STARTRD);
211 + err = rt2880_spi_wait_till_ready(spi);
213 dev_err(&spi->dev, "RX failed, err=%d\n", err);
216 - rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
217 + rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA(cs));
221 @@ -364,7 +420,7 @@ mt7621_spi_write_read(struct spi_device
222 trans |= SPI_CTL_START;
223 rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
225 - mt7621_spi_wait_till_ready(rs);
226 + mt7621_spi_wait_till_ready(spi);
229 u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
230 @@ -440,7 +496,7 @@ static int rt2880_spi_transfer_one_messa
234 - rs->ops->set_cs(rs, 1);
235 + rs->ops->set_cs(spi, 1);
239 @@ -451,14 +507,14 @@ static int rt2880_spi_transfer_one_messa
240 udelay(t->delay_usecs);
243 - rs->ops->set_cs(rs, 0);
244 + rs->ops->set_cs(spi, 0);
251 - rs->ops->set_cs(rs, 0);
252 + rs->ops->set_cs(spi, 0);
255 spi_finalize_current_message(master);
256 @@ -471,7 +527,7 @@ static int rt2880_spi_setup(struct spi_d
257 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
259 if ((spi->max_speed_hz == 0) ||
260 - (spi->max_speed_hz > (rs->sys_freq / 2)))
261 + (spi->max_speed_hz > (rs->sys_freq / 2)))
262 spi->max_speed_hz = (rs->sys_freq / 2);
264 if (spi->max_speed_hz < (rs->sys_freq / 128)) {
265 @@ -488,10 +544,25 @@ static int rt2880_spi_setup(struct spi_d
267 static void rt2880_spi_reset(struct rt2880_spi *rs)
269 - rt2880_spi_write(rs, RAMIPS_SPI_CFG,
270 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(0),
271 SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
272 SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
273 - rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
274 + rt2880_spi_write(rs, RAMIPS_SPI_CTL(0), SPICTL_HIZSDO | SPICTL_SPIENA);
277 +static void rt5350_spi_reset(struct rt2880_spi *rs)
281 + rt2880_spi_write(rs, RAMIPS_SPI_ARBITER,
284 + for (cs = 0; cs < rs->ops->num_cs; cs++) {
285 + rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs),
286 + SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
287 + SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
288 + rt2880_spi_write(rs, RAMIPS_SPI_CTL(cs), SPICTL_HIZSDO | SPICTL_SPIENA);
292 static void mt7621_spi_reset(struct rt2880_spi *rs)
293 @@ -511,24 +582,33 @@ static struct rt2880_spi_ops spi_ops[] =
294 .set_cs = rt2880_spi_set_cs,
295 .baudrate_set = rt2880_spi_baudrate_set,
296 .write_read = rt2880_spi_write_read,
299 + .init_hw = rt5350_spi_reset,
300 + .set_cs = rt2880_spi_set_cs,
301 + .baudrate_set = rt2880_spi_baudrate_set,
302 + .write_read = rt2880_spi_write_read,
305 .init_hw = mt7621_spi_reset,
306 .set_cs = mt7621_spi_set_cs,
307 .baudrate_set = mt7621_spi_baudrate_set,
308 .write_read = mt7621_spi_write_read,
313 static const struct of_device_id rt2880_spi_match[] = {
314 { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
315 - { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
316 + { .compatible = "ralink,rt5350-spi", .data = &spi_ops[1]},
317 + { .compatible = "ralink,mt7621-spi", .data = &spi_ops[2] },
320 MODULE_DEVICE_TABLE(of, rt2880_spi_match);
322 static int rt2880_spi_probe(struct platform_device *pdev)
324 - const struct of_device_id *match;
325 + const struct of_device_id *match;
326 struct spi_master *master;
327 struct rt2880_spi *rs;
329 @@ -536,10 +616,12 @@ static int rt2880_spi_probe(struct platf
333 + struct rt2880_spi_ops *ops;
335 - match = of_match_device(rt2880_spi_match, &pdev->dev);
336 + match = of_match_device(rt2880_spi_match, &pdev->dev);
339 + ops = (struct rt2880_spi_ops *)match->data;
341 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
342 base = devm_ioremap_resource(&pdev->dev, r);
343 @@ -563,14 +645,13 @@ static int rt2880_spi_probe(struct platf
347 - /* we support only mode 0, and no options */
348 - master->mode_bits = 0;
349 + master->mode_bits = RT2880_SPI_MODE_BITS;
351 master->setup = rt2880_spi_setup;
352 master->transfer_one_message = rt2880_spi_transfer_one_message;
353 - master->num_chipselect = RALINK_NUM_CHIPSELECTS;
354 master->bits_per_word_mask = SPI_BPW_MASK(8);
355 master->dev.of_node = pdev->dev.of_node;
356 + master->num_chipselect = ops->num_cs;
358 dev_set_drvdata(&pdev->dev, master);
360 @@ -579,7 +660,7 @@ static int rt2880_spi_probe(struct platf
363 rs->sys_freq = clk_get_rate(rs->clk);
364 - rs->ops = (struct rt2880_spi_ops *) match->data;
366 dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
367 spin_lock_irqsave(&rs->lock, flags);