1 From 5b0bcc314005dd14eeae190948165a81eef7da1f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:36:02 +0100
4 Subject: [PATCH 31/57] PCI: MIPS: adds rt2880 pci support
6 Add support for the pci found on the rt2880 SoC.
8 Signed-off-by: John Crispin <blogic@openwrt.org>
10 arch/mips/pci/Makefile | 1 +
11 arch/mips/pci/pci-rt2880.c | 281 ++++++++++++++++++++++++++++++++++++++++++++
12 arch/mips/ralink/Kconfig | 1 +
13 3 files changed, 283 insertions(+)
14 create mode 100644 arch/mips/pci/pci-rt2880.c
16 --- a/arch/mips/pci/Makefile
17 +++ b/arch/mips/pci/Makefile
18 @@ -43,6 +43,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
19 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
20 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
21 obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
22 +obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
23 obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
24 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
25 obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
27 +++ b/arch/mips/pci/pci-rt2880.c
30 + * Ralink RT288x SoC PCI register definitions
32 + * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
33 + * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
35 + * Parts of this file are based on Ralink's 2.6.21 BSP
37 + * This program is free software; you can redistribute it and/or modify it
38 + * under the terms of the GNU General Public License version 2 as published
39 + * by the Free Software Foundation.
42 +#include <linux/types.h>
43 +#include <linux/pci.h>
44 +#include <linux/io.h>
45 +#include <linux/init.h>
46 +#include <linux/module.h>
47 +#include <linux/of_platform.h>
48 +#include <linux/of_irq.h>
49 +#include <linux/of_pci.h>
51 +#include <asm/mach-ralink/rt288x.h>
53 +#define RT2880_PCI_BASE 0x00440000
54 +#define RT288X_CPU_IRQ_PCI 4
56 +#define RT2880_PCI_MEM_BASE 0x20000000
57 +#define RT2880_PCI_MEM_SIZE 0x10000000
58 +#define RT2880_PCI_IO_BASE 0x00460000
59 +#define RT2880_PCI_IO_SIZE 0x00010000
61 +#define RT2880_PCI_REG_PCICFG_ADDR 0x00
62 +#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
63 +#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
64 +#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
65 +#define RT2880_PCI_REG_CONFIG_ADDR 0x20
66 +#define RT2880_PCI_REG_CONFIG_DATA 0x24
67 +#define RT2880_PCI_REG_MEMBASE 0x28
68 +#define RT2880_PCI_REG_IOBASE 0x2c
69 +#define RT2880_PCI_REG_ID 0x30
70 +#define RT2880_PCI_REG_CLASS 0x34
71 +#define RT2880_PCI_REG_SUBID 0x38
72 +#define RT2880_PCI_REG_ARBCTL 0x80
74 +static void __iomem *rt2880_pci_base;
75 +static DEFINE_SPINLOCK(rt2880_pci_lock);
77 +static u32 rt2880_pci_reg_read(u32 reg)
79 + return readl(rt2880_pci_base + reg);
82 +static void rt2880_pci_reg_write(u32 val, u32 reg)
84 + writel(val, rt2880_pci_base + reg);
87 +static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
88 + unsigned int func, unsigned int where)
90 + return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
94 +static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
95 + int where, int size, u32 *val)
97 + unsigned long flags;
101 + address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
102 + PCI_FUNC(devfn), where);
104 + spin_lock_irqsave(&rt2880_pci_lock, flags);
105 + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
106 + data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
107 + spin_unlock_irqrestore(&rt2880_pci_lock, flags);
111 + *val = (data >> ((where & 3) << 3)) & 0xff;
114 + *val = (data >> ((where & 3) << 3)) & 0xffff;
121 + return PCIBIOS_SUCCESSFUL;
124 +static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
125 + int where, int size, u32 val)
127 + unsigned long flags;
131 + address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
132 + PCI_FUNC(devfn), where);
134 + spin_lock_irqsave(&rt2880_pci_lock, flags);
135 + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
136 + data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
140 + data = (data & ~(0xff << ((where & 3) << 3))) |
141 + (val << ((where & 3) << 3));
144 + data = (data & ~(0xffff << ((where & 3) << 3))) |
145 + (val << ((where & 3) << 3));
152 + rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
153 + spin_unlock_irqrestore(&rt2880_pci_lock, flags);
155 + return PCIBIOS_SUCCESSFUL;
158 +static struct pci_ops rt2880_pci_ops = {
159 + .read = rt2880_pci_config_read,
160 + .write = rt2880_pci_config_write,
163 +static struct resource rt2880_pci_mem_resource = {
164 + .name = "PCI MEM space",
165 + .start = RT2880_PCI_MEM_BASE,
166 + .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
167 + .flags = IORESOURCE_MEM,
170 +static struct resource rt2880_pci_io_resource = {
171 + .name = "PCI IO space",
172 + .start = RT2880_PCI_IO_BASE,
173 + .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
174 + .flags = IORESOURCE_IO,
177 +static struct pci_controller rt2880_pci_controller = {
178 + .pci_ops = &rt2880_pci_ops,
179 + .mem_resource = &rt2880_pci_mem_resource,
180 + .io_resource = &rt2880_pci_io_resource,
183 +static inline u32 rt2880_pci_read_u32(unsigned long reg)
185 + unsigned long flags;
189 + address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
191 + spin_lock_irqsave(&rt2880_pci_lock, flags);
192 + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
193 + ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
194 + spin_unlock_irqrestore(&rt2880_pci_lock, flags);
199 +static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
201 + unsigned long flags;
204 + address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
206 + spin_lock_irqsave(&rt2880_pci_lock, flags);
207 + rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
208 + rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
209 + spin_unlock_irqrestore(&rt2880_pci_lock, flags);
212 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
217 + if (dev->bus->number != 0)
220 + switch (PCI_SLOT(dev->devfn)) {
222 + rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
223 + (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
226 + irq = RT288X_CPU_IRQ_PCI;
229 + printk("%s:%s[%d] trying to alloc unknown pci irq\n",
230 + __FILE__, __func__, __LINE__);
235 + pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
236 + pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
237 + pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
238 + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
239 + PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
240 + PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
241 + pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
242 + pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
247 +static int rt288x_pci_probe(struct platform_device *pdev)
249 + void __iomem *io_map_base;
252 + rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
254 + io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
255 + rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
256 + set_io_port_base((unsigned long) io_map_base);
258 + ioport_resource.start = RT2880_PCI_IO_BASE;
259 + ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
261 + rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
262 + for(i = 0; i < 0xfffff; i++) {}
264 + rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
265 + rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
266 + rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
267 + rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
268 + rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
269 + rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
270 + rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
271 + rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
272 + rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
274 + rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
275 + (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
277 + register_pci_controller(&rt2880_pci_controller);
281 +int pcibios_plat_dev_init(struct pci_dev *dev)
286 +static const struct of_device_id rt288x_pci_match[] = {
287 + { .compatible = "ralink,rt288x-pci" },
290 +MODULE_DEVICE_TABLE(of, rt288x_pci_match);
292 +static struct platform_driver rt288x_pci_driver = {
293 + .probe = rt288x_pci_probe,
295 + .name = "rt288x-pci",
296 + .owner = THIS_MODULE,
297 + .of_match_table = rt288x_pci_match,
301 +int __init pcibios_init(void)
303 + int ret = platform_driver_register(&rt288x_pci_driver);
305 + pr_info("rt288x-pci: Error registering platform driver!");
309 +arch_initcall(pcibios_init);
310 --- a/arch/mips/ralink/Kconfig
311 +++ b/arch/mips/ralink/Kconfig
312 @@ -21,6 +21,7 @@ choice
315 select MIPS_L1_CACHE_SHIFT_4