1 From 307b7a71a634ae3848fb7c5c05759d647e140e12 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 18 May 2013 22:06:15 +0200
4 Subject: [PATCH 32/57] PCI: MIPS: adds mt7620a pcie driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/pci/Makefile | 1 +
9 arch/mips/pci/pci-mt7620.c | 363 +++++++++++++++++++++++++++++++++++++++++++
10 arch/mips/ralink/Kconfig | 1 +
11 3 files changed, 365 insertions(+)
12 create mode 100644 arch/mips/pci/pci-mt7620.c
14 --- a/arch/mips/pci/Makefile
15 +++ b/arch/mips/pci/Makefile
16 @@ -43,6 +43,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
17 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
18 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
19 obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
20 +obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
21 obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
22 obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
23 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
25 +++ b/arch/mips/pci/pci-mt7620.c
28 + * Ralink MT7620A SoC PCI support
30 + * Copyright (C) 2007-2013 Bruce Chang
31 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
33 + * This program is free software; you can redistribute it and/or modify it
34 + * under the terms of the GNU General Public License version 2 as published
35 + * by the Free Software Foundation.
38 +#include <linux/types.h>
39 +#include <linux/pci.h>
40 +#include <linux/io.h>
41 +#include <linux/init.h>
42 +#include <linux/delay.h>
43 +#include <linux/interrupt.h>
44 +#include <linux/module.h>
45 +#include <linux/of.h>
46 +#include <linux/of_irq.h>
47 +#include <linux/of_pci.h>
48 +#include <linux/reset.h>
49 +#include <linux/platform_device.h>
51 +#include <asm/mach-ralink/ralink_regs.h>
52 +#include <asm/mach-ralink/mt7620.h>
54 +#define RALINK_PCI_MM_MAP_BASE 0x20000000
55 +#define RALINK_PCI_IO_MAP_BASE 0x10160000
57 +#define RALINK_INT_PCIE0 4
58 +#define RALINK_SYSCFG1 0x14
59 +#define RALINK_CLKCFG1 0x30
60 +#define RALINK_GPIOMODE 0x60
61 +#define RALINK_PCIE_CLK_GEN 0x7c
62 +#define RALINK_PCIE_CLK_GEN1 0x80
63 +#define PCIEPHY0_CFG 0x90
64 +#define PPLL_CFG1 0x9c
65 +#define PPLL_DRV 0xa0
66 +#define PDRV_SW_SET (1<<31)
67 +#define LC_CKDRVPD_ (1<<19)
69 +#define RALINK_PCI_CONFIG_ADDR 0x20
70 +#define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
71 +#define MEMORY_BASE 0x0
72 +#define RALINK_PCIE0_RST (1<<26)
73 +#define RALINK_PCI_BASE 0xB0140000
74 +#define RALINK_PCI_MEMBASE 0x28
75 +#define RALINK_PCI_IOBASE 0x2C
77 +#define RT6855_PCIE0_OFFSET 0x2000
79 +#define RALINK_PCI_PCICFG_ADDR 0x00
80 +#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
81 +#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
82 +#define RALINK_PCI0_ID 0x30
83 +#define RALINK_PCI0_CLASS 0x34
84 +#define RALINK_PCI0_SUBID 0x38
85 +#define RALINK_PCI0_STATUS 0x50
86 +#define RALINK_PCI_PCIMSK_ADDR 0x0C
88 +#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
89 +#define RALINK_PCIE0_CLK_EN (1 << 26)
91 +#define BUSY 0x80000000
92 +#define WAITRETRY_MAX 10
93 +#define WRITE_MODE (1UL << 23)
97 +static void __iomem *bridge_base;
98 +static void __iomem *pcie_base;
100 +static struct reset_control *rstpcie0;
102 +static inline void bridge_w32(u32 val, unsigned reg)
104 + iowrite32(val, bridge_base + reg);
107 +static inline u32 bridge_r32(unsigned reg)
109 + return ioread32(bridge_base + reg);
112 +static inline void pcie_w32(u32 val, unsigned reg)
114 + iowrite32(val, pcie_base + reg);
117 +static inline u32 pcie_r32(unsigned reg)
119 + return ioread32(pcie_base + reg);
122 +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
124 + u32 val = pcie_r32(reg);
128 + pcie_w32(val, reg);
131 +static int wait_pciephy_busy(void)
133 + unsigned long reg_value = 0x0, retry = 0;
136 + reg_value = pcie_r32(PCIEPHY0_CFG);
138 + if (reg_value & BUSY)
142 + if (retry++ > WAITRETRY_MAX){
143 + printk("PCIE-PHY retry failed.\n");
150 +static void pcie_phy(unsigned long addr, unsigned long val)
152 + wait_pciephy_busy();
153 + pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
155 + wait_pciephy_busy();
158 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
160 + unsigned int slot = PCI_SLOT(devfn);
161 + u8 func = PCI_FUNC(devfn);
169 + address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
170 + bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
171 + data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
175 + *val = (data >> ((where & 3) << 3)) & 0xff;
178 + *val = (data >> ((where & 3) << 3)) & 0xffff;
185 + return PCIBIOS_SUCCESSFUL;
188 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
190 + unsigned int slot = PCI_SLOT(devfn);
191 + u8 func = PCI_FUNC(devfn);
199 + address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
200 + bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
201 + data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
205 + data = (data & ~(0xff << ((where & 3) << 3))) |
206 + (val << ((where & 3) << 3));
209 + data = (data & ~(0xffff << ((where & 3) << 3))) |
210 + (val << ((where & 3) << 3));
217 + bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
219 + return PCIBIOS_SUCCESSFUL;
222 +struct pci_ops mt7620_pci_ops= {
223 + .read = pci_config_read,
224 + .write = pci_config_write,
227 +static struct resource mt7620_res_pci_mem1;
228 +static struct resource mt7620_res_pci_io1;
229 +struct pci_controller mt7620_controller = {
230 + .pci_ops = &mt7620_pci_ops,
231 + .mem_resource = &mt7620_res_pci_mem1,
232 + .mem_offset = 0x00000000UL,
233 + .io_resource = &mt7620_res_pci_io1,
234 + .io_offset = 0x00000000UL,
235 + .io_map_base = 0xa0000000,
238 +static int mt7620_pci_hw_init(struct platform_device *pdev) {
239 + /* PCIE: bypass PCIe DLL */
240 + pcie_phy(0x0, 0x80);
241 + pcie_phy(0x1, 0x04);
243 + /* PCIE: Elastic buffer control */
244 + pcie_phy(0x68, 0xB4);
246 + pcie_m32(0, BIT(1), RALINK_PCI_PCICFG_ADDR);
248 + reset_control_assert(rstpcie0);
250 + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
251 + rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
253 + reset_control_deassert(rstpcie0);
254 + rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
258 + if (!(rt_sysc_r32(PPLL_CFG1) & BIT(23))) {
259 + dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
260 + reset_control_assert(rstpcie0);
261 + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
264 + rt_sysc_m32(BIT(18) | BIT(17), BIT(19) | BIT(31), PPLL_DRV);
269 +static int mt7628_pci_hw_init(struct platform_device *pdev) {
272 + rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
273 + reset_control_deassert(rstpcie0);
274 + rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
277 + pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
279 + pci_config_read(NULL, 0, 0x70c, 4, &val);
280 + val &= ~(0xff) << 8;
282 + pci_config_write(NULL, 0, 0x70c, 4, val);
284 + pci_config_read(NULL, 0, 0x70c, 4, &val);
285 + dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
290 +static int mt7620_pci_probe(struct platform_device *pdev)
292 + struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
293 + struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
296 + rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
297 + if (IS_ERR(rstpcie0))
298 + return PTR_ERR(rstpcie0);
300 + bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
304 + pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
308 + iomem_resource.start = 0;
309 + iomem_resource.end = ~0;
310 + ioport_resource.start = 0;
311 + ioport_resource.end = ~0;
313 + /* bring up the pci core */
314 + switch (ralink_soc) {
315 + case MT762X_SOC_MT7620A:
316 + if (mt7620_pci_hw_init(pdev))
320 + case MT762X_SOC_MT7628AN:
321 + if (mt7628_pci_hw_init(pdev))
326 + dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
331 + /* enable write access */
332 + pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
335 + /* check if there is a card present */
336 + if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
337 + reset_control_assert(rstpcie0);
338 + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
339 + if (ralink_soc == MT762X_SOC_MT7620A)
340 + rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
341 + dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
346 + bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
347 + bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
349 + pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
350 + pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
351 + pcie_w32(0x06040001, RALINK_PCI0_CLASS);
353 + /* enable interrupts */
354 + pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
356 + /* voodoo from the SDK driver */
357 + pci_config_read(NULL, 0, 4, 4, &val);
358 + pci_config_write(NULL, 0, 4, 4, val | 0x7);
360 + pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
361 + register_pci_controller(&mt7620_controller);
366 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
372 + if ((dev->bus->number == 0) && (slot == 0)) {
373 + pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
374 + pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
375 + pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
376 + } else if ((dev->bus->number == 1) && (slot == 0x0)) {
377 + irq = RALINK_INT_PCIE0;
379 + dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
382 + dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq);
384 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
385 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
386 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
389 + cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
390 + pci_write_config_word(dev, PCI_COMMAND, cmd);
391 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
392 + //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
397 +int pcibios_plat_dev_init(struct pci_dev *dev)
402 +static const struct of_device_id mt7620_pci_ids[] = {
403 + { .compatible = "mediatek,mt7620-pci" },
406 +MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
408 +static struct platform_driver mt7620_pci_driver = {
409 + .probe = mt7620_pci_probe,
411 + .name = "mt7620-pci",
412 + .owner = THIS_MODULE,
413 + .of_match_table = of_match_ptr(mt7620_pci_ids),
417 +static int __init mt7620_pci_init(void)
419 + return platform_driver_register(&mt7620_pci_driver);
422 +arch_initcall(mt7620_pci_init);
423 --- a/arch/mips/ralink/Kconfig
424 +++ b/arch/mips/ralink/Kconfig
425 @@ -43,6 +43,7 @@ choice
433 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
434 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
435 @@ -19,6 +19,7 @@ enum mt762x_soc_type {
439 +extern enum mt762x_soc_type mt762x_soc;
441 #define MT7620_SYSC_BASE 0x10000000