1 From f954801c6f48fc291c39ca8a888dbdfda1021415 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 13 Nov 2014 19:08:40 +0100
4 Subject: [PATCH] mmc: MIPS: ralink: add sdhci for mt7620a SoC
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/mmc/host/Kconfig | 2 +
9 drivers/mmc/host/Makefile | 1 +
10 drivers/mmc/host/mtk-mmc/Kconfig | 16 +
11 drivers/mmc/host/mtk-mmc/Makefile | 42 +
12 drivers/mmc/host/mtk-mmc/board.h | 137 ++
13 drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++
14 drivers/mmc/host/mtk-mmc/dbg.h | 153 ++
15 drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
16 drivers/mmc/host/mtk-mmc/sd.c | 3041 ++++++++++++++++++++++++++++++++++
17 9 files changed, 4740 insertions(+)
18 create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
19 create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
20 create mode 100644 drivers/mmc/host/mtk-mmc/board.h
21 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
22 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
23 create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
24 create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
26 --- a/drivers/mmc/host/Kconfig
27 +++ b/drivers/mmc/host/Kconfig
28 @@ -773,3 +773,5 @@ config MMC_SUNXI
30 This selects support for the SD/MMC Host Controller on
33 +source "drivers/mmc/host/mtk-mmc/Kconfig"
34 --- a/drivers/mmc/host/Makefile
35 +++ b/drivers/mmc/host/Makefile
37 # Makefile for MMC/SD host controller drivers
40 +obj-$(CONFIG_MTK_MMC) += mtk-mmc/
41 obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
42 obj-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
43 obj-$(CONFIG_MMC_PXA) += pxamci.o
45 +++ b/drivers/mmc/host/mtk-mmc/Kconfig
48 + tristate "MTK SD/MMC"
49 + depends on !MTD_NAND_RALINK
52 + bool "MTK AEE KDUMP"
55 +config MTK_MMC_CD_POLL
56 + bool "Card Detect with Polling"
59 +config MTK_MMC_EMMC_8BIT
60 + bool "eMMC 8-bit support"
61 + depends on MTK_MMC && RALINK_MT7628
64 +++ b/drivers/mmc/host/mtk-mmc/Makefile
66 +# Copyright Statement:
68 +# This software/firmware and related documentation ("MediaTek Software") are
69 +# protected under relevant copyright laws. The information contained herein
70 +# is confidential and proprietary to MediaTek Inc. and/or its licensors.
71 +# Without the prior written permission of MediaTek inc. and/or its licensors,
72 +# any reproduction, modification, use or disclosure of MediaTek Software,
73 +# and information contained herein, in whole or in part, shall be strictly prohibited.
75 +# MediaTek Inc. (C) 2010. All rights reserved.
77 +# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
78 +# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
79 +# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
80 +# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
81 +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
82 +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
83 +# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
84 +# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
85 +# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
86 +# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
87 +# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
88 +# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
89 +# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
90 +# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
91 +# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
92 +# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
93 +# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
94 +# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
96 +# The following software/firmware and/or related documentation ("MediaTek Software")
97 +# have been modified by MediaTek Inc. All revisions are subject to any receiver's
98 +# applicable license agreements with MediaTek Inc.
100 +obj-$(CONFIG_MTK_MMC) += mtk_sd.o
101 +mtk_sd-objs := sd.o dbg.o
102 +ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
103 +EXTRA_CFLAGS += -DMT6575_SD_DEBUG
107 + @rm -f *.o modules.order .*.cmd
109 +++ b/drivers/mmc/host/mtk-mmc/board.h
111 +/* Copyright Statement:
113 + * This software/firmware and related documentation ("MediaTek Software") are
114 + * protected under relevant copyright laws. The information contained herein
115 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
116 + * Without the prior written permission of MediaTek inc. and/or its licensors,
117 + * any reproduction, modification, use or disclosure of MediaTek Software,
118 + * and information contained herein, in whole or in part, shall be strictly prohibited.
120 +/* MediaTek Inc. (C) 2010. All rights reserved.
122 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
123 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
124 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
125 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
126 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
127 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
128 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
129 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
130 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
131 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
132 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
133 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
134 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
135 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
136 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
137 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
138 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
139 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
141 + * The following software/firmware and/or related documentation ("MediaTek Software")
142 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
143 + * applicable license agreements with MediaTek Inc.
146 +#ifndef __ARCH_ARM_MACH_BOARD_H
147 +#define __ARCH_ARM_MACH_BOARD_H
149 +#include <generated/autoconf.h>
150 +#include <linux/pm.h>
152 +// #include <mach/mt6575.h>
153 +// #include <board-custom.h>
156 +typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
157 +typedef void (*pm_callback_t)(pm_message_t state, void *data);
159 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
160 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
161 +#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
162 +#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
163 +#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
164 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
165 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
166 +#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
167 +#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
168 +#define MSDC_DDR (1 << 9) /* ddr mode support */
171 +#define MSDC_SMPL_RISING (0)
172 +#define MSDC_SMPL_FALLING (1)
174 +#define MSDC_CMD_PIN (0)
175 +#define MSDC_DAT_PIN (1)
176 +#define MSDC_CD_PIN (2)
177 +#define MSDC_WP_PIN (3)
178 +#define MSDC_RST_PIN (4)
181 + MSDC_CLKSRC_48MHZ = 0,
182 +// MSDC_CLKSRC_26MHZ = 0,
183 +// MSDC_CLKSRC_197MHZ = 1,
184 +// MSDC_CLKSRC_208MHZ = 2
188 + unsigned char clk_src; /* host clock source */
189 + unsigned char cmd_edge; /* command latch edge */
190 + unsigned char data_edge; /* data latch edge */
191 + unsigned char clk_drv; /* clock pad driving */
192 + unsigned char cmd_drv; /* command pad driving */
193 + unsigned char dat_drv; /* data pad driving */
194 + unsigned long flags; /* hardware capability flags */
195 + unsigned long data_pins; /* data pins */
196 + unsigned long data_offset; /* data address offset */
198 + /* config gpio pull mode */
199 + void (*config_gpio_pin)(int type, int pull);
201 + /* external power control for card */
202 + void (*ext_power_on)(void);
203 + void (*ext_power_off)(void);
205 + /* external sdio irq operations */
206 + void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
207 + void (*enable_sdio_eirq)(void);
208 + void (*disable_sdio_eirq)(void);
210 + /* external cd irq operations */
211 + void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
212 + void (*enable_cd_eirq)(void);
213 + void (*disable_cd_eirq)(void);
214 + int (*get_cd_status)(void);
216 + /* power management callback for external module */
217 + void (*register_pm)(pm_callback_t pm_cb, void *data);
220 +extern struct msdc_hw msdc0_hw;
221 +extern struct msdc_hw msdc1_hw;
222 +extern struct msdc_hw msdc2_hw;
223 +extern struct msdc_hw msdc3_hw;
226 +#define GPS_FLAG_FORCE_OFF 0x0001
227 +struct mt3326_gps_hardware {
228 + int (*ext_power_on)(int);
229 + int (*ext_power_off)(int);
231 +extern struct mt3326_gps_hardware mt3326_gps_hw;
234 +struct mt6575_nand_host_hw {
235 + unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
236 + unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
237 + unsigned int nfi_cs_num; /* NFI_CS_NUM */
238 + unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
239 + unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
240 + unsigned int nand_ecc_size;
241 + unsigned int nand_ecc_bytes;
242 + unsigned int nand_ecc_mode;
244 +extern struct mt6575_nand_host_hw mt6575_nand_hw;
246 +#endif /* __ARCH_ARM_MACH_BOARD_H */
249 +++ b/drivers/mmc/host/mtk-mmc/dbg.c
251 +/* Copyright Statement:
253 + * This software/firmware and related documentation ("MediaTek Software") are
254 + * protected under relevant copyright laws. The information contained herein
255 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
256 + * Without the prior written permission of MediaTek inc. and/or its licensors,
257 + * any reproduction, modification, use or disclosure of MediaTek Software,
258 + * and information contained herein, in whole or in part, shall be strictly prohibited.
260 + * MediaTek Inc. (C) 2010. All rights reserved.
262 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
263 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
264 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
265 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
266 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
267 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
268 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
269 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
270 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
271 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
272 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
273 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
274 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
275 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
276 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
277 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
278 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
279 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
281 + * The following software/firmware and/or related documentation ("MediaTek Software")
282 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
283 + * applicable license agreements with MediaTek Inc.
286 +#include <linux/version.h>
287 +#include <linux/kernel.h>
288 +#include <linux/sched.h>
289 +#include <linux/kthread.h>
290 +#include <linux/delay.h>
291 +#include <linux/module.h>
292 +#include <linux/init.h>
293 +#include <linux/proc_fs.h>
294 +#include <linux/string.h>
295 +#include <linux/uaccess.h>
296 +// #include <mach/mt6575_gpt.h> /* --- by chhung */
298 +#include "mt6575_sd.h"
299 +#include <linux/seq_file.h>
301 +static char cmd_buf[256];
303 +/* for debug zone */
304 +unsigned int sd_debug_zone[4]={
318 +msdc_mode drv_mode[4]={
319 + MODE_SIZE_DEP, /* using DMA or not depend on the size */
325 +#if defined (MT6575_SD_DEBUG)
326 +/* for driver profile */
327 +#define TICKS_ONE_MS (13000)
329 +u32 sdio_pro_enable = 0; /* make sure gpt is enabled */
330 +u32 sdio_pro_time = 0; /* no more than 30s */
331 +struct sdio_profile sdio_perfomance = {0};
333 +#if 0 /* --- chhung */
334 +void msdc_init_gpt(void)
339 + config.mode = GPT_FREE_RUN;
340 + config.clkSrc = GPT_CLK_SRC_SYS;
341 + config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
343 + if (GPT_Config(config) == FALSE )
348 +#endif /* end of --- */
350 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
354 + if (new_H32 == old_H32) {
355 + ret = new_L32 - old_L32;
356 + } else if(new_H32 == (old_H32 + 1)) {
357 + if (new_L32 > old_L32) {
358 + printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
360 + ret = (0xffffffff - old_L32);
363 + printk("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);
369 +void msdc_sdio_profile(struct sdio_profile* result)
371 + struct cmd_profile* cmd;
374 + printk("sdio === performance dump ===\n");
375 + printk("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n",
376 + result->total_tc, result->total_tc / TICKS_ONE_MS,
377 + result->total_tx_bytes, result->total_rx_bytes);
380 + cmd = &result->cmd52_rx;
381 + printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
382 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
383 + cmd = &result->cmd52_tx;
384 + printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
385 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
387 + /* CMD53 Rx bytes + block mode */
388 + for (i=0; i<512; i++) {
389 + cmd = &result->cmd53_rx_byte[i];
391 + printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
392 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
393 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
396 + for (i=0; i<100; i++) {
397 + cmd = &result->cmd53_rx_blk[i];
399 + printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
400 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
401 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
405 + /* CMD53 Tx bytes + block mode */
406 + for (i=0; i<512; i++) {
407 + cmd = &result->cmd53_tx_byte[i];
409 + printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
410 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
411 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
414 + for (i=0; i<100; i++) {
415 + cmd = &result->cmd53_tx_blk[i];
417 + printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
418 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
419 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
423 + printk("sdio === performance dump done ===\n");
426 +//========= sdio command table ===========
427 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
429 + struct sdio_profile* result = &sdio_perfomance;
430 + struct cmd_profile* cmd;
433 + if (sdio_pro_enable == 0) {
437 + if (opcode == 52) {
438 + cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
439 + } else if (opcode == 53) {
441 + cmd = bRx ? &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];
443 + block = sizes / 512;
445 + printk("cmd53 error blocks\n");
448 + cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
454 + /* update the members */
455 + if (ticks > cmd->max_tc){
456 + cmd->max_tc = ticks;
458 + if (cmd->min_tc == 0 || ticks < cmd->min_tc) {
459 + cmd->min_tc = ticks;
461 + cmd->tot_tc += ticks;
462 + cmd->tot_bytes += sizes;
466 + result->total_rx_bytes += sizes;
468 + result->total_tx_bytes += sizes;
470 + result->total_tc += ticks;
472 + /* dump when total_tc > 30s */
473 + if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
474 + msdc_sdio_profile(result);
475 + memset(result, 0 , sizeof(struct sdio_profile));
479 +//========== driver proc interface ===========
480 +static int msdc_debug_proc_read(struct seq_file *s, void *p)
482 + seq_printf(s, "\n=========================================\n");
483 + seq_printf(s, "Index<0> + Id + Zone\n");
484 + seq_printf(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
485 + seq_printf(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
486 + seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
487 + seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
488 + seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
489 + seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
491 + seq_printf(s, "Index<1> + ID:4|Mode:4 + DMA_SIZE\n");
492 + seq_printf(s, "-> 0)PIO 1)DMA 2)SIZE\n");
493 + seq_printf(s, "-> echo 1 22 0x200 >msdc_bebug -> host[2] size mode, dma when >= 512\n");
494 + seq_printf(s, "-> MSDC[0] mode<%d> size<%d>\n", drv_mode[0], dma_size[0]);
495 + seq_printf(s, "-> MSDC[1] mode<%d> size<%d>\n", drv_mode[1], dma_size[1]);
496 + seq_printf(s, "-> MSDC[2] mode<%d> size<%d>\n", drv_mode[2], dma_size[2]);
497 + seq_printf(s, "-> MSDC[3] mode<%d> size<%d>\n", drv_mode[3], dma_size[3]);
499 + seq_printf(s, "Index<3> + SDIO_PROFILE + TIME\n");
500 + seq_printf(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
501 + seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
502 + seq_printf(s, "=========================================\n\n");
507 +static ssize_t msdc_debug_proc_write(struct file *file,
508 + const char __user *buf, size_t count, loff_t *data)
516 + if (count == 0)return -1;
517 + if(count > 255)count = 255;
519 + ret = copy_from_user(cmd_buf, buf, count);
520 + if (ret < 0)return -1;
522 + cmd_buf[count] = '\0';
523 + printk("msdc Write %s\n", cmd_buf);
525 + sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
527 + if(cmd == SD_TOOL_ZONE) {
528 + id = p1; zone = p2; zone &= 0x3ff;
529 + printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
530 + if(id >=0 && id<=3){
531 + sd_debug_zone[id] = zone;
534 + sd_debug_zone[0] = sd_debug_zone[1] = zone;
535 + sd_debug_zone[2] = sd_debug_zone[3] = zone;
538 + printk("msdc host_id error when set debug zone\n");
540 + } else if (cmd == SD_TOOL_DMA_SIZE) {
541 + id = p1>>4; mode = (p1&0xf); size = p2;
542 + if(id >=0 && id<=3){
543 + drv_mode[id] = mode;
547 + drv_mode[0] = drv_mode[1] = mode;
548 + drv_mode[2] = drv_mode[3] = mode;
549 + dma_size[0] = dma_size[1] = p2;
550 + dma_size[2] = dma_size[3] = p2;
553 + printk("msdc host_id error when select mode\n");
555 + } else if (cmd == SD_TOOL_SDIO_PROFILE) {
556 + if (p1 == 1) { /* enable profile */
557 + if (gpt_enable == 0) {
558 + // msdc_init_gpt(); /* --- by chhung */
561 + sdio_pro_enable = 1;
562 + if (p2 == 0) p2 = 1; if (p2 >= 30) p2 = 30;
563 + sdio_pro_time = p2 ;
564 + } else if (p1 == 0) {
566 + sdio_pro_enable = 0;
573 +static int msdc_debug_show(struct inode *inode, struct file *file)
575 + return single_open(file, msdc_debug_proc_read, NULL);
578 +static const struct file_operations msdc_debug_fops = {
579 + .owner = THIS_MODULE,
580 + .open = msdc_debug_show,
582 + .write = msdc_debug_proc_write,
583 + .llseek = seq_lseek,
584 + .release = single_release,
587 +int msdc_debug_proc_init(void)
589 + struct proc_dir_entry *de = proc_create("msdc_debug", 0667, NULL, &msdc_debug_fops);
591 + if (!de || IS_ERR(de))
592 + printk("!! Create MSDC debug PROC fail !!\n");
596 +EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
599 +++ b/drivers/mmc/host/mtk-mmc/dbg.h
601 +/* Copyright Statement:
603 + * This software/firmware and related documentation ("MediaTek Software") are
604 + * protected under relevant copyright laws. The information contained herein
605 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
606 + * Without the prior written permission of MediaTek inc. and/or its licensors,
607 + * any reproduction, modification, use or disclosure of MediaTek Software,
608 + * and information contained herein, in whole or in part, shall be strictly prohibited.
610 + * MediaTek Inc. (C) 2010. All rights reserved.
612 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
613 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
614 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
615 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
616 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
617 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
618 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
619 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
620 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
621 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
622 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
623 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
624 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
625 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
626 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
627 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
628 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
629 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
631 + * The following software/firmware and/or related documentation ("MediaTek Software")
632 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
633 + * applicable license agreements with MediaTek Inc.
635 +#ifndef __MT_MSDC_DEUBG__
636 +#define __MT_MSDC_DEUBG__
638 +//==========================
639 +extern u32 sdio_pro_enable;
640 +/* for a type command, e.g. CMD53, 2 blocks */
641 +struct cmd_profile {
642 + u32 max_tc; /* Max tick count */
644 + u32 tot_tc; /* total tick count */
646 + u32 count; /* the counts of the command */
649 +/* dump when total_tc and total_bytes */
650 +struct sdio_profile {
651 + u32 total_tc; /* total tick count of CMD52 and CMD53 */
652 + u32 total_tx_bytes; /* total bytes of CMD53 Tx */
653 + u32 total_rx_bytes; /* total bytes of CMD53 Rx */
656 + struct cmd_profile cmd52_tx;
657 + struct cmd_profile cmd52_rx;
659 + /*CMD53 in byte unit */
660 + struct cmd_profile cmd53_tx_byte[512];
661 + struct cmd_profile cmd53_rx_byte[512];
663 + /*CMD53 in block unit */
664 + struct cmd_profile cmd53_tx_blk[100];
665 + struct cmd_profile cmd53_rx_blk[100];
668 +//==========================
671 + SD_TOOL_DMA_SIZE = 1,
672 + SD_TOOL_PM_ENABLE = 2,
673 + SD_TOOL_SDIO_PROFILE = 3,
681 +extern msdc_mode drv_mode[4];
682 +extern u32 dma_size[4];
684 +/* Debug message event */
685 +#define DBG_EVT_NONE (0) /* No event */
686 +#define DBG_EVT_DMA (1 << 0) /* DMA related event */
687 +#define DBG_EVT_CMD (1 << 1) /* MSDC CMD related event */
688 +#define DBG_EVT_RSP (1 << 2) /* MSDC CMD RSP related event */
689 +#define DBG_EVT_INT (1 << 3) /* MSDC INT event */
690 +#define DBG_EVT_CFG (1 << 4) /* MSDC CFG event */
691 +#define DBG_EVT_FUC (1 << 5) /* Function event */
692 +#define DBG_EVT_OPS (1 << 6) /* Read/Write operation event */
693 +#define DBG_EVT_FIO (1 << 7) /* FIFO operation event */
694 +#define DBG_EVT_WRN (1 << 8) /* Warning event */
695 +#define DBG_EVT_PWR (1 << 9) /* Power event */
696 +#define DBG_EVT_ALL (0xffffffff)
698 +#define DBG_EVT_MASK (DBG_EVT_ALL)
700 +extern unsigned int sd_debug_zone[4];
702 +#if 0 /* +++ chhung */
706 + printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
710 +#endif /* end of +++ */
712 +#define N_MSG(evt, fmt, args...)
715 + if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
716 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
717 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
722 +#define ERR_MSG(fmt, args...) \
724 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
725 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
729 +//defined CONFIG_MTK_MMC_CD_POLL
730 +#define INIT_MSG(fmt, args...)
731 +#define IRQ_MSG(fmt, args...)
733 +#define INIT_MSG(fmt, args...) \
735 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
736 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
739 +/* PID in ISR in not corrent */
740 +#define IRQ_MSG(fmt, args...) \
742 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
743 + host->id, ##args , __FUNCTION__, __LINE__); \
747 +int msdc_debug_proc_init(void);
749 +#if 0 /* --- chhung */
750 +void msdc_init_gpt(void);
751 +extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
752 +#endif /* end of --- */
753 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
754 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);
758 +++ b/drivers/mmc/host/mtk-mmc/mt6575_sd.h
760 +/* Copyright Statement:
762 + * This software/firmware and related documentation ("MediaTek Software") are
763 + * protected under relevant copyright laws. The information contained herein
764 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
765 + * Without the prior written permission of MediaTek inc. and/or its licensors,
766 + * any reproduction, modification, use or disclosure of MediaTek Software,
767 + * and information contained herein, in whole or in part, shall be strictly prohibited.
769 +/* MediaTek Inc. (C) 2010. All rights reserved.
771 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
772 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
773 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
774 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
775 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
776 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
777 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
778 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
779 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
780 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
781 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
782 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
783 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
784 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
785 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
786 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
787 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
788 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
790 + * The following software/firmware and/or related documentation ("MediaTek Software")
791 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
792 + * applicable license agreements with MediaTek Inc.
798 +#include <linux/bitops.h>
799 +#include <linux/mmc/host.h>
801 +// #include <mach/mt6575_reg_base.h> /* --- by chhung */
803 +/*--------------------------------------------------------------------------*/
805 +/*--------------------------------------------------------------------------*/
806 +#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
808 +/*--------------------------------------------------------------------------*/
809 +/* Common Definition */
810 +/*--------------------------------------------------------------------------*/
811 +#define MSDC_FIFO_SZ (128)
812 +#define MSDC_FIFO_THD (64) // (128)
813 +#define MSDC_NUM (4)
816 +#define MSDC_SDMMC (1)
818 +#define MSDC_MODE_UNKNOWN (0)
819 +#define MSDC_MODE_PIO (1)
820 +#define MSDC_MODE_DMA_BASIC (2)
821 +#define MSDC_MODE_DMA_DESC (3)
822 +#define MSDC_MODE_DMA_ENHANCED (4)
823 +#define MSDC_MODE_MMC_STREAM (5)
825 +#define MSDC_BUS_1BITS (0)
826 +#define MSDC_BUS_4BITS (1)
827 +#define MSDC_BUS_8BITS (2)
829 +#define MSDC_BRUST_8B (3)
830 +#define MSDC_BRUST_16B (4)
831 +#define MSDC_BRUST_32B (5)
832 +#define MSDC_BRUST_64B (6)
834 +#define MSDC_PIN_PULL_NONE (0)
835 +#define MSDC_PIN_PULL_DOWN (1)
836 +#define MSDC_PIN_PULL_UP (2)
837 +#define MSDC_PIN_KEEP (3)
839 +#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
840 +#define MSDC_MIN_SCLK (260000)
842 +#define MSDC_AUTOCMD12 (0x0001)
843 +#define MSDC_AUTOCMD23 (0x0002)
844 +#define MSDC_AUTOCMD19 (0x0003)
846 +#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
847 +#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
861 +/*--------------------------------------------------------------------------*/
862 +/* Register Offset */
863 +/*--------------------------------------------------------------------------*/
864 +#define OFFSET_MSDC_CFG (0x0)
865 +#define OFFSET_MSDC_IOCON (0x04)
866 +#define OFFSET_MSDC_PS (0x08)
867 +#define OFFSET_MSDC_INT (0x0c)
868 +#define OFFSET_MSDC_INTEN (0x10)
869 +#define OFFSET_MSDC_FIFOCS (0x14)
870 +#define OFFSET_MSDC_TXDATA (0x18)
871 +#define OFFSET_MSDC_RXDATA (0x1c)
872 +#define OFFSET_SDC_CFG (0x30)
873 +#define OFFSET_SDC_CMD (0x34)
874 +#define OFFSET_SDC_ARG (0x38)
875 +#define OFFSET_SDC_STS (0x3c)
876 +#define OFFSET_SDC_RESP0 (0x40)
877 +#define OFFSET_SDC_RESP1 (0x44)
878 +#define OFFSET_SDC_RESP2 (0x48)
879 +#define OFFSET_SDC_RESP3 (0x4c)
880 +#define OFFSET_SDC_BLK_NUM (0x50)
881 +#define OFFSET_SDC_CSTS (0x58)
882 +#define OFFSET_SDC_CSTS_EN (0x5c)
883 +#define OFFSET_SDC_DCRC_STS (0x60)
884 +#define OFFSET_EMMC_CFG0 (0x70)
885 +#define OFFSET_EMMC_CFG1 (0x74)
886 +#define OFFSET_EMMC_STS (0x78)
887 +#define OFFSET_EMMC_IOCON (0x7c)
888 +#define OFFSET_SDC_ACMD_RESP (0x80)
889 +#define OFFSET_SDC_ACMD19_TRG (0x84)
890 +#define OFFSET_SDC_ACMD19_STS (0x88)
891 +#define OFFSET_MSDC_DMA_SA (0x90)
892 +#define OFFSET_MSDC_DMA_CA (0x94)
893 +#define OFFSET_MSDC_DMA_CTRL (0x98)
894 +#define OFFSET_MSDC_DMA_CFG (0x9c)
895 +#define OFFSET_MSDC_DBG_SEL (0xa0)
896 +#define OFFSET_MSDC_DBG_OUT (0xa4)
897 +#define OFFSET_MSDC_PATCH_BIT (0xb0)
898 +#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
899 +#define OFFSET_MSDC_PAD_CTL0 (0xe0)
900 +#define OFFSET_MSDC_PAD_CTL1 (0xe4)
901 +#define OFFSET_MSDC_PAD_CTL2 (0xe8)
902 +#define OFFSET_MSDC_PAD_TUNE (0xec)
903 +#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
904 +#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
905 +#define OFFSET_MSDC_HW_DBG (0xf8)
906 +#define OFFSET_MSDC_VERSION (0x100)
907 +#define OFFSET_MSDC_ECO_VER (0x104)
909 +/*--------------------------------------------------------------------------*/
910 +/* Register Address */
911 +/*--------------------------------------------------------------------------*/
913 +/* common register */
914 +#define MSDC_CFG REG_ADDR(MSDC_CFG)
915 +#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
916 +#define MSDC_PS REG_ADDR(MSDC_PS)
917 +#define MSDC_INT REG_ADDR(MSDC_INT)
918 +#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
919 +#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
920 +#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
921 +#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
922 +#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
924 +/* sdmmc register */
925 +#define SDC_CFG REG_ADDR(SDC_CFG)
926 +#define SDC_CMD REG_ADDR(SDC_CMD)
927 +#define SDC_ARG REG_ADDR(SDC_ARG)
928 +#define SDC_STS REG_ADDR(SDC_STS)
929 +#define SDC_RESP0 REG_ADDR(SDC_RESP0)
930 +#define SDC_RESP1 REG_ADDR(SDC_RESP1)
931 +#define SDC_RESP2 REG_ADDR(SDC_RESP2)
932 +#define SDC_RESP3 REG_ADDR(SDC_RESP3)
933 +#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
934 +#define SDC_CSTS REG_ADDR(SDC_CSTS)
935 +#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
936 +#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
939 +#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
940 +#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
941 +#define EMMC_STS REG_ADDR(EMMC_STS)
942 +#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
944 +/* auto command register */
945 +#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
946 +#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
947 +#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
950 +#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
951 +#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
952 +#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
953 +#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
955 +/* pad ctrl register */
956 +#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
957 +#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
958 +#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
960 +/* data read delay */
961 +#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
962 +#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
964 +/* debug register */
965 +#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
966 +#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
969 +#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
970 +#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
971 +#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
972 +#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
973 +#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
974 +#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
976 +/*--------------------------------------------------------------------------*/
978 +/*--------------------------------------------------------------------------*/
981 +#define MSDC_CFG_MODE (0x1 << 0) /* RW */
982 +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
983 +#define MSDC_CFG_RST (0x1 << 2) /* RW */
984 +#define MSDC_CFG_PIO (0x1 << 3) /* RW */
985 +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
986 +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
987 +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
988 +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
989 +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
990 +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
992 +/* MSDC_IOCON mask */
993 +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
994 +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
995 +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
996 +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
997 +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
998 +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
999 +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
1000 +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
1001 +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
1002 +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
1003 +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
1004 +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
1005 +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
1006 +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
1007 +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
1010 +#define MSDC_PS_CDEN (0x1 << 0) /* RW */
1011 +#define MSDC_PS_CDSTS (0x1 << 1) /* R */
1012 +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
1013 +#define MSDC_PS_DAT (0xff << 16) /* R */
1014 +#define MSDC_PS_CMD (0x1 << 24) /* R */
1015 +#define MSDC_PS_WP (0x1UL<< 31) /* R */
1017 +/* MSDC_INT mask */
1018 +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
1019 +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
1020 +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
1021 +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
1022 +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
1023 +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
1024 +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
1025 +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
1026 +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
1027 +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
1028 +#define MSDC_INT_CSTA (0x1 << 11) /* R */
1029 +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
1030 +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
1031 +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
1032 +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
1033 +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
1035 +/* MSDC_INTEN mask */
1036 +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
1037 +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
1038 +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
1039 +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
1040 +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
1041 +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
1042 +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
1043 +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
1044 +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
1045 +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
1046 +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
1047 +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
1048 +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
1049 +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
1050 +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
1051 +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
1053 +/* MSDC_FIFOCS mask */
1054 +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
1055 +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
1056 +#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
1059 +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
1060 +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
1061 +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
1062 +#define SDC_CFG_SDIO (0x1 << 19) /* RW */
1063 +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
1064 +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
1065 +#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
1068 +#define SDC_CMD_OPC (0x3f << 0) /* RW */
1069 +#define SDC_CMD_BRK (0x1 << 6) /* RW */
1070 +#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
1071 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1072 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1073 +#define SDC_CMD_RW (0x1 << 13) /* RW */
1074 +#define SDC_CMD_STOP (0x1 << 14) /* RW */
1075 +#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
1076 +#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
1077 +#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
1078 +#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
1081 +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
1082 +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
1083 +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
1085 +/* SDC_DCRC_STS mask */
1086 +#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
1087 +#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
1089 +/* EMMC_CFG0 mask */
1090 +#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
1091 +#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
1092 +#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
1093 +#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
1094 +#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
1095 +#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
1097 +/* EMMC_CFG1 mask */
1098 +#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
1099 +#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
1101 +/* EMMC_STS mask */
1102 +#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
1103 +#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
1104 +#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
1105 +#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
1106 +#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
1107 +#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
1108 +#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
1110 +/* EMMC_IOCON mask */
1111 +#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
1113 +/* SDC_ACMD19_TRG mask */
1114 +#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
1116 +/* MSDC_DMA_CTRL mask */
1117 +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
1118 +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
1119 +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
1120 +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
1121 +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
1122 +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
1123 +#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
1125 +/* MSDC_DMA_CFG mask */
1126 +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
1127 +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
1128 +#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
1129 +#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
1131 +/* MSDC_PATCH_BIT mask */
1132 +#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
1133 +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
1134 +#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
1135 +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
1136 +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
1137 +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
1138 +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
1139 +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
1140 +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
1141 +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
1142 +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
1143 +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
1145 +/* MSDC_PATCH_BIT1 mask */
1146 +#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
1147 +#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
1149 +/* MSDC_PAD_CTL0 mask */
1150 +#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
1151 +#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
1152 +#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
1153 +#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
1154 +#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
1155 +#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
1156 +#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
1157 +#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
1158 +#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
1160 +/* MSDC_PAD_CTL1 mask */
1161 +#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
1162 +#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
1163 +#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
1164 +#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
1165 +#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
1166 +#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
1167 +#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
1168 +#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
1169 +#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
1171 +/* MSDC_PAD_CTL2 mask */
1172 +#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
1173 +#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
1174 +#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
1175 +#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
1176 +#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
1177 +#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
1178 +#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
1179 +#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
1180 +#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
1182 +/* MSDC_PAD_TUNE mask */
1183 +#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
1184 +#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
1185 +#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
1186 +#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
1187 +#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
1189 +/* MSDC_DAT_RDDLY0/1 mask */
1190 +#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
1191 +#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
1192 +#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
1193 +#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
1195 +#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
1196 +#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
1197 +#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
1198 +#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
1200 +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
1201 +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
1202 +#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
1203 +#define CARD_READY_FOR_DATA (1<<8)
1204 +#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
1206 +/*--------------------------------------------------------------------------*/
1207 +/* Descriptor Structure */
1208 +/*--------------------------------------------------------------------------*/
1210 + u32 hwo:1; /* could be changed by hw */
1240 +/*--------------------------------------------------------------------------*/
1241 +/* Register Debugging Structure */
1242 +/*--------------------------------------------------------------------------*/
1258 + u32 sdr104cksel:1;
1303 + u32 atocmd19done:1;
1323 + u32 atocmd19done:1;
1399 +} sdc_datcrcsts_reg;
1410 + u32 bootcrctmc:16;
1412 + u32 bootacktmc:12;
1419 + u32 bootupstate:1;
1430 +} msdc_acmd_resp_reg;
1434 +} msdc_acmd19_trg_reg;
1437 +} msdc_acmd19_sts_reg;
1456 +} msdc_dma_ctrl_reg;
1464 +} msdc_dma_cfg_reg;
1468 +} msdc_dbg_sel_reg;
1471 +} msdc_dbg_out_reg;
1485 +} msdc_pad_ctl0_reg;
1499 +} msdc_pad_ctl1_reg;
1513 +} msdc_pad_ctl2_reg;
1519 +} msdc_pad_tune_reg;
1551 +} msdc_version_reg;
1554 +} msdc_eco_ver_reg;
1557 + msdc_cfg_reg msdc_cfg; /* base+0x00h */
1558 + msdc_iocon_reg msdc_iocon; /* base+0x04h */
1559 + msdc_ps_reg msdc_ps; /* base+0x08h */
1560 + msdc_int_reg msdc_int; /* base+0x0ch */
1561 + msdc_inten_reg msdc_inten; /* base+0x10h */
1562 + msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
1563 + msdc_txdat_reg msdc_txdat; /* base+0x18h */
1564 + msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
1566 + sdc_cfg_reg sdc_cfg; /* base+0x30h */
1567 + sdc_cmd_reg sdc_cmd; /* base+0x34h */
1568 + sdc_arg_reg sdc_arg; /* base+0x38h */
1569 + sdc_sts_reg sdc_sts; /* base+0x3ch */
1570 + sdc_resp0_reg sdc_resp0; /* base+0x40h */
1571 + sdc_resp1_reg sdc_resp1; /* base+0x44h */
1572 + sdc_resp2_reg sdc_resp2; /* base+0x48h */
1573 + sdc_resp3_reg sdc_resp3; /* base+0x4ch */
1574 + sdc_blknum_reg sdc_blknum; /* base+0x50h */
1576 + sdc_csts_reg sdc_csts; /* base+0x58h */
1577 + sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
1578 + sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
1580 + emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
1581 + emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
1582 + emmc_sts_reg emmc_sts; /* base+0x78h */
1583 + emmc_iocon_reg emmc_iocon; /* base+0x7ch */
1584 + msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
1585 + msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
1586 + msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
1588 + msdc_dma_sa_reg dma_sa; /* base+0x90h */
1589 + msdc_dma_ca_reg dma_ca; /* base+0x94h */
1590 + msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
1591 + msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
1592 + msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
1593 + msdc_dbg_out_reg dbg_out; /* base+0xa4h */
1595 + u32 patch0; /* base+0xb0h */
1596 + u32 patch1; /* base+0xb4h */
1598 + msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
1599 + msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
1600 + msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
1601 + msdc_pad_tune_reg pad_tune; /* base+0xech */
1602 + msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
1603 + msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
1604 + msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
1606 + msdc_version_reg version; /* base+0x100h */
1607 + msdc_eco_ver_reg eco_ver; /* base+0x104h */
1610 +struct scatterlist_ex {
1614 + struct scatterlist *sg;
1617 +#define DMA_FLAG_NONE (0x00000000)
1618 +#define DMA_FLAG_EN_CHKSUM (0x00000001)
1619 +#define DMA_FLAG_PAD_BLOCK (0x00000002)
1620 +#define DMA_FLAG_PAD_DWORD (0x00000004)
1623 + u32 flags; /* flags */
1624 + u32 xfersz; /* xfer size in bytes */
1625 + u32 sglen; /* size of scatter list */
1626 + u32 blklen; /* block size */
1627 + struct scatterlist *sg; /* I/O scatter list */
1628 + struct scatterlist_ex *esg; /* extended I/O scatter list */
1629 + u8 mode; /* dma mode */
1630 + u8 burstsz; /* burst size */
1631 + u8 intr; /* dma done interrupt */
1632 + u8 padding; /* padding */
1633 + u32 cmd; /* enhanced mode command */
1634 + u32 arg; /* enhanced mode arg */
1635 + u32 rsp; /* enhanced mode command response */
1636 + u32 autorsp; /* auto command response */
1638 + gpd_t *gpd; /* pointer to gpd array */
1639 + bd_t *bd; /* pointer to bd array */
1640 + dma_addr_t gpd_addr; /* the physical address of gpd array */
1641 + dma_addr_t bd_addr; /* the physical address of bd array */
1642 + u32 used_gpd; /* the number of used gpd elements */
1643 + u32 used_bd; /* the number of used bd elements */
1648 + struct msdc_hw *hw;
1650 + struct mmc_host *mmc; /* mmc structure */
1651 + struct mmc_command *cmd;
1652 + struct mmc_data *data;
1653 + struct mmc_request *mrq;
1659 + spinlock_t lock; /* mutex */
1660 + struct semaphore sem;
1662 + u32 blksz; /* host block size */
1663 + u32 base; /* host base address */
1664 + int id; /* host id */
1665 + int pwr_ref; /* core power reference count */
1667 + u32 xfer_size; /* total transferred size */
1669 + struct msdc_dma dma; /* dma channel */
1670 + u32 dma_addr; /* dma transfer address */
1671 + u32 dma_left_size; /* dma transfer left size */
1672 + u32 dma_xfer_size; /* dma transfer size in bytes */
1673 + int dma_xfer; /* dma transfer mode */
1675 + u32 timeout_ns; /* data timeout ns */
1676 + u32 timeout_clks; /* data timeout clks */
1678 + atomic_t abort; /* abort transfer */
1680 + int irq; /* host interrupt */
1682 + struct tasklet_struct card_tasklet;
1684 + struct work_struct card_workqueue;
1686 + struct delayed_work card_delaywork;
1689 + struct completion cmd_done;
1690 + struct completion xfer_done;
1691 + struct pm_message pm_state;
1693 + u32 mclk; /* mmc subsystem clock */
1694 + u32 hclk; /* host clock speed */
1695 + u32 sclk; /* SD/MS clock speed */
1696 + u8 core_clkon; /* Host core clock on ? */
1697 + u8 card_clkon; /* Card clock on ? */
1698 + u8 core_power; /* core power */
1699 + u8 power_mode; /* host power mode */
1700 + u8 card_inserted; /* card inserted ? */
1701 + u8 suspend; /* host suspended ? */
1703 + u8 app_cmd; /* for app command */
1708 +static inline unsigned int uffs(unsigned int x)
1710 + unsigned int r = 1;
1714 + if (!(x & 0xffff)) {
1718 + if (!(x & 0xff)) {
1736 +#define sdr_read8(reg) __raw_readb(reg)
1737 +#define sdr_read16(reg) __raw_readw(reg)
1738 +#define sdr_read32(reg) __raw_readl(reg)
1739 +#define sdr_write8(reg,val) __raw_writeb(val,reg)
1740 +#define sdr_write16(reg,val) __raw_writew(val,reg)
1741 +#define sdr_write32(reg,val) __raw_writel(val,reg)
1743 +#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
1744 +#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
1746 +#define sdr_set_field(reg,field,val) \
1748 + volatile unsigned int tv = sdr_read32(reg); \
1750 + tv |= ((val) << (uffs((unsigned int)field) - 1)); \
1751 + sdr_write32(reg,tv); \
1753 +#define sdr_get_field(reg,field,val) \
1755 + volatile unsigned int tv = sdr_read32(reg); \
1756 + val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
1762 +++ b/drivers/mmc/host/mtk-mmc/sd.c
1764 +/* Copyright Statement:
1766 + * This software/firmware and related documentation ("MediaTek Software") are
1767 + * protected under relevant copyright laws. The information contained herein
1768 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
1769 + * Without the prior written permission of MediaTek inc. and/or its licensors,
1770 + * any reproduction, modification, use or disclosure of MediaTek Software,
1771 + * and information contained herein, in whole or in part, shall be strictly prohibited.
1773 + * MediaTek Inc. (C) 2010. All rights reserved.
1775 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1776 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1777 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
1778 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1779 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1780 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1781 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1782 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1783 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
1784 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
1785 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
1786 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
1787 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
1788 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
1789 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1790 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1791 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
1792 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1794 + * The following software/firmware and/or related documentation ("MediaTek Software")
1795 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
1796 + * applicable license agreements with MediaTek Inc.
1799 +#include <linux/module.h>
1800 +#include <linux/moduleparam.h>
1801 +#include <linux/init.h>
1802 +#include <linux/spinlock.h>
1803 +#include <linux/timer.h>
1804 +#include <linux/ioport.h>
1805 +#include <linux/device.h>
1806 +#include <linux/platform_device.h>
1807 +#include <linux/interrupt.h>
1808 +#include <linux/delay.h>
1809 +#include <linux/blkdev.h>
1810 +#include <linux/slab.h>
1811 +#include <linux/mmc/host.h>
1812 +#include <linux/mmc/card.h>
1813 +#include <linux/mmc/core.h>
1814 +#include <linux/mmc/mmc.h>
1815 +#include <linux/mmc/sd.h>
1816 +#include <linux/mmc/sdio.h>
1817 +#include <linux/dma-mapping.h>
1819 +/* +++ by chhung */
1820 +#include <linux/types.h>
1821 +#include <linux/kernel.h>
1822 +#include <linux/version.h>
1823 +#include <linux/pm.h>
1824 +#include <linux/of.h>
1826 +#define MSDC_SMPL_FALLING (1)
1827 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
1828 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
1829 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
1830 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
1831 +#define MSDC_HIGHSPEED (1 << 7)
1833 +//#define IRQ_SDC 14 //MT7620 /*FIXME*/
1834 +#ifdef CONFIG_SOC_MT7621
1835 +#define RALINK_SYSCTL_BASE 0xbe000000
1836 +#define RALINK_MSDC_BASE 0xbe130000
1838 +#define RALINK_SYSCTL_BASE 0xb0000000
1839 +#define RALINK_MSDC_BASE 0xb0130000
1841 +#define IRQ_SDC 22 /*FIXME*/
1843 +#include <asm/dma.h>
1847 +#include <asm/mach-ralink/ralink_regs.h>
1849 +#if 0 /* --- by chhung */
1850 +#include <mach/board.h>
1851 +#include <mach/mt6575_devs.h>
1852 +#include <mach/mt6575_typedefs.h>
1853 +#include <mach/mt6575_clock_manager.h>
1854 +#include <mach/mt6575_pm_ldo.h>
1855 +//#include <mach/mt6575_pll.h>
1856 +//#include <mach/mt6575_gpio.h>
1857 +//#include <mach/mt6575_gpt_sw.h>
1858 +#include <asm/tcm.h>
1859 +// #include <mach/mt6575_gpt.h>
1860 +#endif /* end of --- */
1862 +#include "mt6575_sd.h"
1865 +/* +++ by chhung */
1869 +#if 0 /* --- by chhung */
1870 +#define isb() __asm__ __volatile__ ("" : : : "memory")
1871 +#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
1872 + : : "r" (0) : "memory")
1873 +#define dmb() __asm__ __volatile__ ("" : : : "memory")
1874 +#endif /* end of --- */
1876 +#define DRV_NAME "mtk-sd"
1878 +#define HOST_MAX_NUM (1) /* +/- by chhung */
1880 +#if defined (CONFIG_SOC_MT7620)
1881 +#define HOST_MAX_MCLK (48000000) /* +/- by chhung */
1882 +#elif defined (CONFIG_SOC_MT7621)
1883 +#define HOST_MAX_MCLK (50000000) /* +/- by chhung */
1885 +#define HOST_MIN_MCLK (260000)
1887 +#define HOST_MAX_BLKSZ (2048)
1889 +#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
1891 +#define GPIO_PULL_DOWN (0)
1892 +#define GPIO_PULL_UP (1)
1894 +#if 0 /* --- by chhung */
1895 +#define MSDC_CLKSRC_REG (0xf100000C)
1896 +#define PDN_REG (0xF1000010)
1897 +#endif /* end of --- */
1899 +#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
1900 +#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
1902 +#define CMD_TIMEOUT (HZ/10) /* 100ms */
1903 +#define DAT_TIMEOUT (HZ/2 * 5) /* 500ms x5 */
1905 +#define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
1907 +#define MAX_GPD_NUM (1 + 1) /* one null gpd */
1908 +#define MAX_BD_NUM (1024)
1909 +#define MAX_BD_PER_GPD (MAX_BD_NUM)
1911 +#define MAX_HW_SGMTS (MAX_BD_NUM)
1912 +#define MAX_PHY_SGMTS (MAX_BD_NUM)
1913 +#define MAX_SGMT_SZ (MAX_DMA_CNT)
1914 +#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
1916 +#ifdef MT6575_SD_DEBUG
1917 +static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
1920 +static int mtk_sw_poll;
1922 +static int cd_active_low = 1;
1924 +//=================================
1925 +#define PERI_MSDC0_PDN (15)
1926 +//#define PERI_MSDC1_PDN (16)
1927 +//#define PERI_MSDC2_PDN (17)
1928 +//#define PERI_MSDC3_PDN (18)
1930 +struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
1931 +#if 0 /* --- by chhung */
1932 +/* gate means clock power down */
1933 +static int g_clk_gate = 0;
1934 +#define msdc_gate_clock(id) \
1936 + g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
1938 +/* not like power down register. 1 means clock on. */
1939 +#define msdc_ungate_clock(id) \
1941 + g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
1944 +// do we need sync object or not
1945 +void msdc_clk_status(int * status)
1947 + *status = g_clk_gate;
1949 +#endif /* end of --- */
1951 +/* +++ by chhung */
1952 +struct msdc_hw msdc0_hw = {
1954 + .cmd_edge = MSDC_SMPL_FALLING,
1955 + .data_edge = MSDC_SMPL_FALLING,
1961 + .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
1962 +// .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
1965 +static struct resource mtk_sd_resources[] = {
1967 + .start = RALINK_MSDC_BASE,
1968 + .end = RALINK_MSDC_BASE+0x3fff,
1969 + .flags = IORESOURCE_MEM,
1972 + .start = IRQ_SDC, /*FIXME*/
1973 + .end = IRQ_SDC, /*FIXME*/
1974 + .flags = IORESOURCE_IRQ,
1978 +static struct platform_device mtk_sd_device = {
1981 + .num_resources = ARRAY_SIZE(mtk_sd_resources),
1982 + .resource = mtk_sd_resources,
1986 +static int msdc_rsp[] = {
1987 + 0, /* RESP_NONE */
1998 +/* For Inhanced DMA */
1999 +#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
2001 + ((gpd_t*)gpd)->extlen = extlen; \
2002 + ((gpd_t*)gpd)->cmd = cmd; \
2003 + ((gpd_t*)gpd)->arg = arg; \
2004 + ((gpd_t*)gpd)->blknum = blknum; \
2007 +#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
2009 + BUG_ON(dlen > 0xFFFFUL); \
2010 + ((bd_t*)bd)->blkpad = blkpad; \
2011 + ((bd_t*)bd)->dwpad = dwpad; \
2012 + ((bd_t*)bd)->ptr = (void*)dptr; \
2013 + ((bd_t*)bd)->buflen = dlen; \
2016 +#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
2017 +#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
2018 +#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
2019 +#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
2020 +#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
2021 +#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
2024 +#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
2025 +#define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
2027 +#define msdc_retry(expr,retry,cnt) \
2029 + int backup = cnt; \
2031 + if (!(expr)) break; \
2032 + if (cnt-- == 0) { \
2033 + retry--; mdelay(1); cnt = backup; \
2036 + WARN_ON(retry == 0); \
2039 +#if 0 /* --- by chhung */
2040 +#define msdc_reset() \
2042 + int retry = 3, cnt = 1000; \
2043 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2045 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2048 +#define msdc_reset() \
2050 + int retry = 3, cnt = 1000; \
2051 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2052 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2054 +#endif /* end of +/- */
2056 +#define msdc_clr_int() \
2058 + volatile u32 val = sdr_read32(MSDC_INT); \
2059 + sdr_write32(MSDC_INT, val); \
2062 +#define msdc_clr_fifo() \
2064 + int retry = 3, cnt = 1000; \
2065 + sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
2066 + msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
2069 +#define msdc_irq_save(val) \
2071 + val = sdr_read32(MSDC_INTEN); \
2072 + sdr_clr_bits(MSDC_INTEN, val); \
2075 +#define msdc_irq_restore(val) \
2077 + sdr_set_bits(MSDC_INTEN, val); \
2080 +/* clock source for host: global */
2081 +#if defined (CONFIG_SOC_MT7620)
2082 +static u32 hclks[] = {48000000}; /* +/- by chhung */
2083 +#elif defined (CONFIG_SOC_MT7621)
2084 +static u32 hclks[] = {50000000}; /* +/- by chhung */
2087 +//============================================
2088 +// the power for msdc host controller: global
2089 +// always keep the VMC on.
2090 +//============================================
2091 +#define msdc_vcore_on(host) \
2093 + INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
2094 + (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
2096 +#define msdc_vcore_off(host) \
2098 + INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
2099 + (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
2102 +//====================================
2103 +// the vdd output for card: global
2104 +// always keep the VMCH on.
2105 +//====================================
2106 +#define msdc_vdd_on(host) \
2108 + (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
2110 +#define msdc_vdd_off(host) \
2112 + (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
2115 +#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
2116 +#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
2118 +#define sdc_send_cmd(cmd,arg) \
2120 + sdr_write32(SDC_ARG, (arg)); \
2121 + sdr_write32(SDC_CMD, (cmd)); \
2124 +// can modify to read h/w register.
2125 +//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
2126 +#define is_card_present(h) (((struct msdc_host*)(h))->card_inserted)
2128 +/* +++ by chhung */
2129 +#ifndef __ASSEMBLY__
2130 +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
2132 +#define PHYSADDR(a) ((a) & 0x1fffffff)
2135 +static unsigned int msdc_do_command(struct msdc_host *host,
2136 + struct mmc_command *cmd,
2138 + unsigned long timeout);
2140 +static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
2142 +#ifdef MT6575_SD_DEBUG
2143 +static void msdc_dump_card_status(struct msdc_host *host, u32 status)
2145 + static char *state[] = {
2155 + "Reserved", /* 9 */
2156 + "Reserved", /* 10 */
2157 + "Reserved", /* 11 */
2158 + "Reserved", /* 12 */
2159 + "Reserved", /* 13 */
2160 + "Reserved", /* 14 */
2161 + "I/O mode", /* 15 */
2163 + if (status & R1_OUT_OF_RANGE)
2164 + N_MSG(RSP, "[CARD_STATUS] Out of Range");
2165 + if (status & R1_ADDRESS_ERROR)
2166 + N_MSG(RSP, "[CARD_STATUS] Address Error");
2167 + if (status & R1_BLOCK_LEN_ERROR)
2168 + N_MSG(RSP, "[CARD_STATUS] Block Len Error");
2169 + if (status & R1_ERASE_SEQ_ERROR)
2170 + N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
2171 + if (status & R1_ERASE_PARAM)
2172 + N_MSG(RSP, "[CARD_STATUS] Erase Param");
2173 + if (status & R1_WP_VIOLATION)
2174 + N_MSG(RSP, "[CARD_STATUS] WP Violation");
2175 + if (status & R1_CARD_IS_LOCKED)
2176 + N_MSG(RSP, "[CARD_STATUS] Card is Locked");
2177 + if (status & R1_LOCK_UNLOCK_FAILED)
2178 + N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
2179 + if (status & R1_COM_CRC_ERROR)
2180 + N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
2181 + if (status & R1_ILLEGAL_COMMAND)
2182 + N_MSG(RSP, "[CARD_STATUS] Illegal Command");
2183 + if (status & R1_CARD_ECC_FAILED)
2184 + N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
2185 + if (status & R1_CC_ERROR)
2186 + N_MSG(RSP, "[CARD_STATUS] CC Error");
2187 + if (status & R1_ERROR)
2188 + N_MSG(RSP, "[CARD_STATUS] Error");
2189 + if (status & R1_UNDERRUN)
2190 + N_MSG(RSP, "[CARD_STATUS] Underrun");
2191 + if (status & R1_OVERRUN)
2192 + N_MSG(RSP, "[CARD_STATUS] Overrun");
2193 + if (status & R1_CID_CSD_OVERWRITE)
2194 + N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
2195 + if (status & R1_WP_ERASE_SKIP)
2196 + N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
2197 + if (status & R1_CARD_ECC_DISABLED)
2198 + N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
2199 + if (status & R1_ERASE_RESET)
2200 + N_MSG(RSP, "[CARD_STATUS] Erase Reset");
2201 + if (status & R1_READY_FOR_DATA)
2202 + N_MSG(RSP, "[CARD_STATUS] Ready for Data");
2203 + if (status & R1_SWITCH_ERROR)
2204 + N_MSG(RSP, "[CARD_STATUS] Switch error");
2205 + if (status & R1_APP_CMD)
2206 + N_MSG(RSP, "[CARD_STATUS] App Command");
2208 + N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
2211 +static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
2213 + if (resp & (1 << 7))
2214 + N_MSG(RSP, "[OCR] Low Voltage Range");
2215 + if (resp & (1 << 15))
2216 + N_MSG(RSP, "[OCR] 2.7-2.8 volt");
2217 + if (resp & (1 << 16))
2218 + N_MSG(RSP, "[OCR] 2.8-2.9 volt");
2219 + if (resp & (1 << 17))
2220 + N_MSG(RSP, "[OCR] 2.9-3.0 volt");
2221 + if (resp & (1 << 18))
2222 + N_MSG(RSP, "[OCR] 3.0-3.1 volt");
2223 + if (resp & (1 << 19))
2224 + N_MSG(RSP, "[OCR] 3.1-3.2 volt");
2225 + if (resp & (1 << 20))
2226 + N_MSG(RSP, "[OCR] 3.2-3.3 volt");
2227 + if (resp & (1 << 21))
2228 + N_MSG(RSP, "[OCR] 3.3-3.4 volt");
2229 + if (resp & (1 << 22))
2230 + N_MSG(RSP, "[OCR] 3.4-3.5 volt");
2231 + if (resp & (1 << 23))
2232 + N_MSG(RSP, "[OCR] 3.5-3.6 volt");
2233 + if (resp & (1 << 24))
2234 + N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
2235 + if (resp & (1 << 30))
2236 + N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
2237 + if (resp & (1 << 31))
2238 + N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
2240 + N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
2243 +static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
2245 + u32 status = (((resp >> 15) & 0x1) << 23) |
2246 + (((resp >> 14) & 0x1) << 22) |
2247 + (((resp >> 13) & 0x1) << 19) |
2250 + N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
2251 + msdc_dump_card_status(host, status);
2254 +static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
2256 + u32 flags = (resp >> 8) & 0xFF;
2257 + char *state[] = {"DIS", "CMD", "TRN", "RFU"};
2259 + if (flags & (1 << 7))
2260 + N_MSG(RSP, "[IO] COM_CRC_ERR");
2261 + if (flags & (1 << 6))
2262 + N_MSG(RSP, "[IO] Illgal command");
2263 + if (flags & (1 << 3))
2264 + N_MSG(RSP, "[IO] Error");
2265 + if (flags & (1 << 2))
2266 + N_MSG(RSP, "[IO] RFU");
2267 + if (flags & (1 << 1))
2268 + N_MSG(RSP, "[IO] Function number error");
2269 + if (flags & (1 << 0))
2270 + N_MSG(RSP, "[IO] Out of range");
2272 + N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
2276 +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
2278 + u32 base = host->base;
2279 + u32 timeout, clk_ns;
2281 + host->timeout_ns = ns;
2282 + host->timeout_clks = clks;
2284 + clk_ns = 1000000000UL / host->sclk;
2285 + timeout = ns / clk_ns + clks;
2286 + timeout = timeout >> 16; /* in 65536 sclk cycle unit */
2287 + timeout = timeout > 1 ? timeout - 1 : 0;
2288 + timeout = timeout > 255 ? 255 : timeout;
2290 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
2292 + N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
2293 + ns, clks, timeout + 1);
2296 +/* msdc_eirq_sdio() will be called when EIRQ(for WIFI) */
2297 +static void msdc_eirq_sdio(void *data)
2299 + struct msdc_host *host = (struct msdc_host *)data;
2301 + N_MSG(INT, "SDIO EINT");
2303 + mmc_signal_sdio_irq(host->mmc);
2306 +/* msdc_eirq_cd will not be used! We not using EINT for card detection. */
2307 +static void msdc_eirq_cd(void *data)
2309 + struct msdc_host *host = (struct msdc_host *)data;
2311 + N_MSG(INT, "CD EINT");
2314 + tasklet_hi_schedule(&host->card_tasklet);
2316 + schedule_delayed_work(&host->card_delaywork, HZ);
2321 +static void msdc_tasklet_card(unsigned long arg)
2323 + struct msdc_host *host = (struct msdc_host *)arg;
2325 +static void msdc_tasklet_card(struct work_struct *work)
2327 + struct msdc_host *host = (struct msdc_host *)container_of(work,
2328 + struct msdc_host, card_delaywork.work);
2330 + struct msdc_hw *hw = host->hw;
2331 + u32 base = host->base;
2336 + spin_lock(&host->lock);
2338 + if (hw->get_cd_status) { // NULL
2339 + inserted = hw->get_cd_status();
2341 + status = sdr_read32(MSDC_PS);
2342 + if (cd_active_low)
2343 + inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
2345 + inserted = (status & MSDC_PS_CDSTS) ? 1 : 0;
2349 + change = host->card_inserted ^ inserted;
2350 + host->card_inserted = inserted;
2352 + if (change && !host->suspend) {
2354 + host->mmc->f_max = HOST_MAX_MCLK; // work around
2356 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2358 +#else /* Make sure: handle the last interrupt */
2359 + host->card_inserted = inserted;
2361 + if (!host->suspend) {
2362 + host->mmc->f_max = HOST_MAX_MCLK;
2363 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2366 + IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
2369 + spin_unlock(&host->lock);
2372 +#if 0 /* --- by chhung */
2374 +static u8 clk_src_bit[4] = {
2378 +static void msdc_select_clksrc(struct msdc_host* host, unsigned char clksrc)
2381 + u32 base = host->base;
2383 + BUG_ON(clksrc > 3);
2384 + INIT_MSG("set clock source to <%d>", clksrc);
2386 + val = sdr_read32(MSDC_CLKSRC_REG);
2387 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2388 + val &= ~(0x3 << clk_src_bit[host->id]);
2389 + val |= clksrc << clk_src_bit[host->id];
2391 + val &= ~0x3; val |= clksrc;
2393 + sdr_write32(MSDC_CLKSRC_REG, val);
2395 + host->hclk = hclks[clksrc];
2396 + host->hw->clk_src = clksrc;
2398 +#endif /* end of --- */
2400 +static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
2402 + //struct msdc_hw *hw = host->hw;
2403 + u32 base = host->base;
2408 + u32 hclk = host->hclk;
2409 + //u8 clksrc = hw->clk_src;
2411 + if (!hz) { // set mmc system clock to 0 ?
2412 + //ERR_MSG("set mclk to 0!!!");
2417 + msdc_irq_save(flags);
2419 +#if defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7628_FPGA)
2420 + mode = 0x0; /* use divisor */
2421 + if (hz >= (hclk >> 1)) {
2422 + div = 0; /* mean div = 1/2 */
2423 + sclk = hclk >> 1; /* sclk = clk / 2 */
2425 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2426 + sclk = (hclk >> 2) / div;
2430 + mode = 0x2; /* ddr mode and use divisor */
2431 + if (hz >= (hclk >> 2)) {
2432 + div = 1; /* mean div = 1/4 */
2433 + sclk = hclk >> 2; /* sclk = clk / 4 */
2435 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2436 + sclk = (hclk >> 2) / div;
2438 + } else if (hz >= hclk) { /* bug fix */
2439 + mode = 0x1; /* no divisor and divisor is ignored */
2443 + mode = 0x0; /* use divisor */
2444 + if (hz >= (hclk >> 1)) {
2445 + div = 0; /* mean div = 1/2 */
2446 + sclk = hclk >> 1; /* sclk = clk / 2 */
2448 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2449 + sclk = (hclk >> 2) / div;
2453 + /* set clock mode and divisor */
2454 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
2455 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
2457 + /* wait clock stable */
2458 + while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
2460 + host->sclk = sclk;
2462 + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
2464 + INIT_MSG("================");
2465 + INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz/1000, hclk/1000, sclk/1000);
2466 + INIT_MSG("================");
2468 + msdc_irq_restore(flags);
2471 +/* Fix me. when need to abort */
2472 +static void msdc_abort_data(struct msdc_host *host)
2474 + u32 base = host->base;
2475 + struct mmc_command *stop = host->mrq->stop;
2477 + ERR_MSG("Need to Abort. dma<%d>", host->dma_xfer);
2483 + // need to check FIFO count 0 ?
2485 + if (stop) { /* try to stop, but may not success */
2486 + ERR_MSG("stop when abort CMD<%d>", stop->opcode);
2487 + (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
2490 + //if (host->mclk >= 25000000) {
2491 + // msdc_set_mclk(host, 0, host->mclk >> 1);
2495 +#if 0 /* --- by chhung */
2496 +static void msdc_pin_config(struct msdc_host *host, int mode)
2498 + struct msdc_hw *hw = host->hw;
2499 + u32 base = host->base;
2500 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2502 + /* Config WP pin */
2503 + if (hw->flags & MSDC_WP_PIN_EN) {
2504 + if (hw->config_gpio_pin) /* NULL */
2505 + hw->config_gpio_pin(MSDC_WP_PIN, pull);
2509 + case MSDC_PIN_PULL_UP:
2510 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
2511 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2512 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
2513 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2514 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
2515 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2517 + case MSDC_PIN_PULL_DOWN:
2518 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2519 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
2520 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2521 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
2522 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2523 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
2525 + case MSDC_PIN_PULL_NONE:
2527 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2528 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2529 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2530 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2531 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2532 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2536 + N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
2537 + mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
2540 +void msdc_pin_reset(struct msdc_host *host, int mode)
2542 + struct msdc_hw *hw = (struct msdc_hw *)host->hw;
2543 + u32 base = host->base;
2544 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2546 + /* Config reset pin */
2547 + if (hw->flags & MSDC_RST_PIN_EN) {
2548 + if (hw->config_gpio_pin) /* NULL */
2549 + hw->config_gpio_pin(MSDC_RST_PIN, pull);
2551 + if (mode == MSDC_PIN_PULL_UP) {
2552 + sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2554 + sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2559 +static void msdc_core_power(struct msdc_host *host, int on)
2561 + N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
2562 + on ? "on" : "off", "core", host->core_power, on);
2564 + if (on && host->core_power == 0) {
2565 + msdc_vcore_on(host);
2566 + host->core_power = 1;
2568 + } else if (!on && host->core_power == 1) {
2569 + msdc_vcore_off(host);
2570 + host->core_power = 0;
2575 +static void msdc_host_power(struct msdc_host *host, int on)
2577 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
2580 + //msdc_core_power(host, 1); // need do card detection.
2581 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
2583 + msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
2584 + //msdc_core_power(host, 0);
2588 +static void msdc_card_power(struct msdc_host *host, int on)
2590 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
2593 + msdc_pin_config(host, MSDC_PIN_PULL_UP);
2594 + if (host->hw->ext_power_on) {
2595 + host->hw->ext_power_on();
2597 + //msdc_vdd_on(host); // need todo card detection.
2601 + if (host->hw->ext_power_off) {
2602 + host->hw->ext_power_off();
2604 + //msdc_vdd_off(host);
2606 + msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
2611 +static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
2613 + N_MSG(CFG, "Set power mode(%d)", mode);
2615 + if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
2616 + msdc_host_power(host, 1);
2617 + msdc_card_power(host, 1);
2618 + } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
2619 + msdc_card_power(host, 0);
2620 + msdc_host_power(host, 0);
2622 + host->power_mode = mode;
2624 +#endif /* end of --- */
2628 + register as callback function of WIFI(combo_sdio_register_pm) .
2629 + can called by msdc_drv_suspend/resume too.
2631 +static void msdc_pm(pm_message_t state, void *data)
2633 + struct msdc_host *host = (struct msdc_host *)data;
2634 + int evt = state.event;
2636 + if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
2637 + INIT_MSG("USR_%s: suspend<%d> power<%d>",
2638 + evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
2639 + host->suspend, host->power_mode);
2642 + if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
2643 + if (host->suspend) /* already suspend */ /* default 0*/
2646 + /* for memory card. already power off by mmc */
2647 + if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
2650 + host->suspend = 1;
2651 + host->pm_state = state; /* default PMSG_RESUME */
2653 + INIT_MSG("%s Suspend", evt == PM_EVENT_SUSPEND ? "PM" : "USR");
2654 + if(host->hw->flags & MSDC_SYS_SUSPEND) /* set for card */
2655 + (void)mmc_suspend_host(host->mmc);
2657 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* just for double confirm */ /* --- by chhung */
2658 + mmc_remove_host(host->mmc);
2660 + } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
2661 + if (!host->suspend){
2662 + //ERR_MSG("warning: already resume");
2666 + /* No PM resume when USR suspend */
2667 + if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
2668 + ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
2672 + host->suspend = 0;
2673 + host->pm_state = state;
2675 + INIT_MSG("%s Resume", evt == PM_EVENT_RESUME ? "PM" : "USR");
2676 + if(host->hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
2677 + (void)mmc_resume_host(host->mmc);
2680 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* --- by chhung */
2681 + mmc_add_host(host->mmc);
2687 +/*--------------------------------------------------------------------------*/
2688 +/* mmc_host_ops members */
2689 +/*--------------------------------------------------------------------------*/
2690 +static unsigned int msdc_command_start(struct msdc_host *host,
2691 + struct mmc_command *cmd,
2692 + int tune, /* not used */
2693 + unsigned long timeout)
2695 + u32 base = host->base;
2696 + u32 opcode = cmd->opcode;
2698 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2699 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2700 + MSDC_INT_ACMD19_DONE;
2703 + unsigned long tmo;
2705 + /* Protocol layer does not provide response type, but our hardware needs
2706 + * to know exact type, not just size!
2708 + if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
2710 + else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
2711 + resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
2712 + else if (opcode == MMC_FAST_IO)
2714 + else if (opcode == MMC_GO_IRQ_STATE)
2716 + else if (opcode == MMC_SELECT_CARD)
2717 + resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
2718 + else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
2719 + resp = RESP_R1; /* SDIO workaround. */
2720 + else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
2723 + switch (mmc_resp_type(cmd)) {
2736 + case MMC_RSP_NONE:
2745 + * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
2746 + * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
2748 + rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
2750 + if (opcode == MMC_READ_MULTIPLE_BLOCK) {
2751 + rawcmd |= (2 << 11);
2752 + } else if (opcode == MMC_READ_SINGLE_BLOCK) {
2753 + rawcmd |= (1 << 11);
2754 + } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
2755 + rawcmd |= ((2 << 11) | (1 << 13));
2756 + } else if (opcode == MMC_WRITE_BLOCK) {
2757 + rawcmd |= ((1 << 11) | (1 << 13));
2758 + } else if (opcode == SD_IO_RW_EXTENDED) {
2759 + if (cmd->data->flags & MMC_DATA_WRITE)
2760 + rawcmd |= (1 << 13);
2761 + if (cmd->data->blocks > 1)
2762 + rawcmd |= (2 << 11);
2764 + rawcmd |= (1 << 11);
2765 + } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
2766 + rawcmd |= (1 << 14);
2767 + } else if ((opcode == SD_APP_SEND_SCR) ||
2768 + (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
2769 + (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2770 + (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2771 + (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
2772 + rawcmd |= (1 << 11);
2773 + } else if (opcode == MMC_STOP_TRANSMISSION) {
2774 + rawcmd |= (1 << 14);
2775 + rawcmd &= ~(0x0FFF << 16);
2778 + N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode , rawcmd, cmd->arg);
2780 + tmo = jiffies + timeout;
2782 + if (opcode == MMC_SEND_STATUS) {
2784 + if (!sdc_is_cmd_busy())
2787 + if (time_after(jiffies, tmo)) {
2788 + ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
2789 + cmd->error = (unsigned int)-ETIMEDOUT;
2796 + if (!sdc_is_busy())
2798 + if (time_after(jiffies, tmo)) {
2799 + ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
2800 + cmd->error = (unsigned int)-ETIMEDOUT;
2807 + //BUG_ON(in_interrupt());
2809 + host->cmd_rsp = resp;
2811 + init_completion(&host->cmd_done);
2813 + sdr_set_bits(MSDC_INTEN, wints);
2814 + sdc_send_cmd(rawcmd, cmd->arg);
2817 + return cmd->error;
2820 +static unsigned int msdc_command_resp(struct msdc_host *host,
2821 + struct mmc_command *cmd,
2823 + unsigned long timeout)
2825 + u32 base = host->base;
2826 + u32 opcode = cmd->opcode;
2829 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2830 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2831 + MSDC_INT_ACMD19_DONE;
2833 + resp = host->cmd_rsp;
2835 + BUG_ON(in_interrupt());
2836 + //init_completion(&host->cmd_done);
2837 + //sdr_set_bits(MSDC_INTEN, wints);
2839 + spin_unlock(&host->lock);
2840 + if(!wait_for_completion_timeout(&host->cmd_done, 10*timeout)){
2841 + ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
2842 + cmd->error = (unsigned int)-ETIMEDOUT;
2845 + spin_lock(&host->lock);
2847 + sdr_clr_bits(MSDC_INTEN, wints);
2851 +#ifdef MT6575_SD_DEBUG
2854 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
2857 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
2858 + opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
2859 + cmd->resp[2], cmd->resp[3]);
2861 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
2862 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
2863 + opcode, cmd->error, resp, cmd->resp[0]);
2864 + if (cmd->error == 0) {
2868 + msdc_dump_card_status(host, cmd->resp[0]);
2871 + msdc_dump_ocr_reg(host, cmd->resp[0]);
2874 + msdc_dump_io_resp(host, cmd->resp[0]);
2877 + msdc_dump_rca_resp(host, cmd->resp[0]);
2885 + /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
2888 + return cmd->error;
2891 + /* memory card CRC */
2892 + if(host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
2893 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
2894 + msdc_abort_data(host);
2896 + /* do basic: reset*/
2901 + cmd->error = msdc_tune_cmdrsp(host,cmd);
2905 + /* if (resp == RESP_R1B) {
2906 + while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);
2908 + /* CMD12 Error Handle */
2910 + return cmd->error;
2913 +static unsigned int msdc_do_command(struct msdc_host *host,
2914 + struct mmc_command *cmd,
2916 + unsigned long timeout)
2918 + if (msdc_command_start(host, cmd, tune, timeout))
2921 + if (msdc_command_resp(host, cmd, tune, timeout))
2926 + N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
2927 + return cmd->error;
2930 +/* The abort condition when PIO read/write
2933 +static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
2936 + u32 base = host->base;
2938 + if (atomic_read(&host->abort)) {
2942 + if (time_after(jiffies, tmo)) {
2943 + data->error = (unsigned int)-ETIMEDOUT;
2944 + ERR_MSG("XXX PIO Data Timeout: CMD<%d>", host->mrq->cmd->opcode);
2952 + ERR_MSG("msdc pio find abort");
2958 + Need to add a timeout, or WDT timeout, system reboot.
2960 +// pio mode data read/write
2961 +static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
2963 + struct scatterlist *sg = data->sg;
2964 + u32 base = host->base;
2965 + u32 num = data->sg_len;
2969 + u32 count, size = 0;
2970 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
2971 + unsigned long tmo = jiffies + DAT_TIMEOUT;
2973 + sdr_set_bits(MSDC_INTEN, wints);
2975 + left = sg_dma_len(sg);
2976 + ptr = sg_virt(sg);
2978 + if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
2979 + count = MSDC_FIFO_THD >> 2;
2981 + *ptr++ = msdc_fifo_read32();
2982 + } while (--count);
2983 + left -= MSDC_FIFO_THD;
2984 + } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
2985 + while (left > 3) {
2986 + *ptr++ = msdc_fifo_read32();
2990 + u8ptr = (u8 *)ptr;
2992 + * u8ptr++ = msdc_fifo_read8();
2997 + if (msdc_pio_abort(host, data, tmo)) {
3001 + size += sg_dma_len(sg);
3002 + sg = sg_next(sg); num--;
3005 + data->bytes_xfered += size;
3006 + N_MSG(FIO, " PIO Read<%d>bytes", size);
3008 + sdr_clr_bits(MSDC_INTEN, wints);
3009 + if(data->error) ERR_MSG("read pio data->error<%d> left<%d> size<%d>", data->error, left, size);
3010 + return data->error;
3013 +/* please make sure won't using PIO when size >= 512
3014 + which means, memory card block read/write won't using pio
3015 + then don't need to handle the CMD12 when data error.
3017 +static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
3019 + u32 base = host->base;
3020 + struct scatterlist *sg = data->sg;
3021 + u32 num = data->sg_len;
3025 + u32 count, size = 0;
3026 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3027 + unsigned long tmo = jiffies + DAT_TIMEOUT;
3029 + sdr_set_bits(MSDC_INTEN, wints);
3031 + left = sg_dma_len(sg);
3032 + ptr = sg_virt(sg);
3035 + if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3036 + count = MSDC_FIFO_SZ >> 2;
3038 + msdc_fifo_write32(*ptr); ptr++;
3039 + } while (--count);
3040 + left -= MSDC_FIFO_SZ;
3041 + } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3042 + while (left > 3) {
3043 + msdc_fifo_write32(*ptr); ptr++;
3049 + msdc_fifo_write8(*u8ptr); u8ptr++;
3054 + if (msdc_pio_abort(host, data, tmo)) {
3058 + size += sg_dma_len(sg);
3059 + sg = sg_next(sg); num--;
3062 + data->bytes_xfered += size;
3063 + N_MSG(FIO, " PIO Write<%d>bytes", size);
3064 + if(data->error) ERR_MSG("write pio data->error<%d>", data->error);
3066 + sdr_clr_bits(MSDC_INTEN, wints);
3067 + return data->error;
3070 +#if 0 /* --- by chhung */
3071 +// DMA resume / start / stop
3072 +static void msdc_dma_resume(struct msdc_host *host)
3074 + u32 base = host->base;
3076 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
3078 + N_MSG(DMA, "DMA resume");
3080 +#endif /* end of --- */
3082 +static void msdc_dma_start(struct msdc_host *host)
3084 + u32 base = host->base;
3085 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3087 + sdr_set_bits(MSDC_INTEN, wints);
3088 + //dsb(); /* --- by chhung */
3089 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
3091 + N_MSG(DMA, "DMA start");
3094 +static void msdc_dma_stop(struct msdc_host *host)
3096 + u32 base = host->base;
3097 + //u32 retries=500;
3098 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3100 + N_MSG(DMA, "DMA status: 0x%.8x",sdr_read32(MSDC_DMA_CFG));
3101 + //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3103 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
3104 + while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3106 + //dsb(); /* --- by chhung */
3107 + sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
3109 + N_MSG(DMA, "DMA stop");
3112 +#if 0 /* --- by chhung */
3113 +/* dump a gpd list */
3114 +static void msdc_dma_dump(struct msdc_host *host, struct msdc_dma *dma)
3116 + gpd_t *gpd = dma->gpd;
3117 + bd_t *bd = dma->bd;
3122 + if (dma->mode != MSDC_MODE_DMA_DESC) {
3126 + ERR_MSG("try to dump gpd and bd");
3129 + ERR_MSG(".gpd<0x%.8x> gpd_phy<0x%.8x>", (int)gpd, (int)dma->gpd_addr);
3130 + ERR_MSG("...hwo <%d>", gpd->hwo );
3131 + ERR_MSG("...bdp <%d>", gpd->bdp );
3132 + ERR_MSG("...chksum<0x%.8x>", gpd->chksum );
3133 + //ERR_MSG("...intr <0x%.8x>", gpd->intr );
3134 + ERR_MSG("...next <0x%.8x>", (int)gpd->next );
3135 + ERR_MSG("...ptr <0x%.8x>", (int)gpd->ptr );
3136 + ERR_MSG("...buflen<0x%.8x>", gpd->buflen );
3137 + //ERR_MSG("...extlen<0x%.8x>", gpd->extlen );
3138 + //ERR_MSG("...arg <0x%.8x>", gpd->arg );
3139 + //ERR_MSG("...blknum<0x%.8x>", gpd->blknum );
3140 + //ERR_MSG("...cmd <0x%.8x>", gpd->cmd );
3143 + ERR_MSG(".bd<0x%.8x> bd_phy<0x%.8x> gpd_ptr<0x%.8x>", (int)bd, (int)dma->bd_addr, (int)gpd->ptr);
3145 + p_to_v = ((u32)bd - (u32)dma->bd_addr);
3147 + ERR_MSG(".bd[%d]", i); i++;
3148 + ERR_MSG("...eol <%d>", ptr->eol );
3149 + ERR_MSG("...chksum<0x%.8x>", ptr->chksum );
3150 + //ERR_MSG("...blkpad<0x%.8x>", ptr->blkpad );
3151 + //ERR_MSG("...dwpad <0x%.8x>", ptr->dwpad );
3152 + ERR_MSG("...next <0x%.8x>", (int)ptr->next );
3153 + ERR_MSG("...ptr <0x%.8x>", (int)ptr->ptr );
3154 + ERR_MSG("...buflen<0x%.8x>", (int)ptr->buflen );
3156 + if (ptr->eol == 1) {
3160 + /* find the next bd, virtual address of ptr->next */
3161 + /* don't need to enable when use malloc */
3162 + //BUG_ON( (ptr->next + p_to_v)!=(ptr+1) );
3163 + //ERR_MSG(".next bd<0x%.8x><0x%.8x>", (ptr->next + p_to_v), (ptr+1));
3167 + ERR_MSG("dump gpd and bd finished");
3169 +#endif /* end of --- */
3171 +/* calc checksum */
3172 +static u8 msdc_dma_calcs(u8 *buf, u32 len)
3175 + for (i = 0; i < len; i++) {
3178 + return 0xFF - (u8)sum;
3181 +/* gpd bd setup + dma registers */
3182 +static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
3184 + u32 base = host->base;
3185 + u32 sglen = dma->sglen;
3186 + //u32 i, j, num, bdlen, arg, xfersz;
3187 + u32 j, num, bdlen;
3188 + u8 blkpad, dwpad, chksum;
3189 + struct scatterlist *sg = dma->sg;
3193 + switch (dma->mode) {
3194 + case MSDC_MODE_DMA_BASIC:
3195 + BUG_ON(dma->xfersz > 65535);
3196 + BUG_ON(dma->sglen != 1);
3197 + sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
3198 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
3199 +//#if defined (CONFIG_RALINK_MT7620)
3200 + if (ralink_soc == MT762X_SOC_MT7620A)
3201 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
3202 +//#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3204 + sdr_write32((volatile u32*)(RALINK_MSDC_BASE+0xa8), sg_dma_len(sg));
3206 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3207 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
3209 + case MSDC_MODE_DMA_DESC:
3210 + blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
3211 + dwpad = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
3212 + chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
3214 + /* calculate the required number of gpd */
3215 + num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
3224 + gpd->hwo = 1; /* hw will clear it */
3226 + gpd->chksum = 0; /* need to clear first. */
3227 + gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
3230 + for (j = 0; j < bdlen; j++) {
3231 + msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
3232 + if(j == bdlen - 1) {
3233 + bd[j].eol = 1; /* the last bd */
3237 + bd[j].chksum = 0; /* checksume need to clear first */
3238 + bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
3242 + dma->used_gpd += 2;
3243 + dma->used_bd += bdlen;
3245 + sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
3246 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3247 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
3249 + sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
3256 + N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3257 + N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3258 + N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3263 +static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
3264 + struct scatterlist *sg, unsigned int sglen)
3266 + BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
3269 + dma->flags = DMA_FLAG_EN_CHKSUM;
3270 + //dma->flags = DMA_FLAG_NONE; /* CHECKME */
3271 + dma->sglen = sglen;
3272 + dma->xfersz = host->xfer_size;
3273 + dma->burstsz = MSDC_BRUST_64B;
3275 + if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
3276 + dma->mode = MSDC_MODE_DMA_BASIC;
3278 + dma->mode = MSDC_MODE_DMA_DESC;
3280 + N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen, dma->xfersz);
3282 + msdc_dma_config(host, dma);
3284 + /*if (dma->mode == MSDC_MODE_DMA_DESC) {
3285 + //msdc_dma_dump(host, dma);
3289 +/* set block number before send command */
3290 +static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
3292 + u32 base = host->base;
3294 + sdr_write32(SDC_BLK_NUM, blknum);
3297 +static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
3299 + struct msdc_host *host = mmc_priv(mmc);
3300 + struct mmc_command *cmd;
3301 + struct mmc_data *data;
3302 + u32 base = host->base;
3304 + unsigned int left=0;
3305 + int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
3310 + BUG_ON(mmc == NULL);
3311 + BUG_ON(mrq == NULL);
3314 + atomic_set(&host->abort, 0);
3317 + data = mrq->cmd->data;
3319 +#if 0 /* --- by chhung */
3320 + //if(host->id ==1){
3321 + N_MSG(OPS, "enable clock!");
3322 + msdc_ungate_clock(host->id);
3324 +#endif /* end of --- */
3327 + send_type=SND_CMD;
3328 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3332 + BUG_ON(data->blksz > HOST_MAX_BLKSZ);
3333 + send_type=SND_DAT;
3336 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3337 + host->data = data;
3338 + host->xfer_size = data->blocks * data->blksz;
3339 + host->blksz = data->blksz;
3341 + /* deside the transfer mode */
3342 + if (drv_mode[host->id] == MODE_PIO) {
3343 + host->dma_xfer = dma = 0;
3344 + } else if (drv_mode[host->id] == MODE_DMA) {
3345 + host->dma_xfer = dma = 1;
3346 + } else if (drv_mode[host->id] == MODE_SIZE_DEP) {
3347 + host->dma_xfer = dma = ((host->xfer_size >= dma_size[host->id]) ? 1 : 0);
3351 + if ((host->timeout_ns != data->timeout_ns) ||
3352 + (host->timeout_clks != data->timeout_clks)) {
3353 + msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
3357 + msdc_set_blknum(host, data->blocks);
3358 + //msdc_clr_fifo(); /* no need */
3361 + msdc_dma_on(); /* enable DMA mode first!! */
3362 + init_completion(&host->xfer_done);
3364 + /* start the command first*/
3365 + if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
3368 + dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
3369 + (void)dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3370 + msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
3372 + /* then wait command done */
3373 + if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
3376 + /* for read, the data coming too fast, then CRC error
3377 + start DMA no business with CRC. */
3378 + //init_completion(&host->xfer_done);
3379 + msdc_dma_start(host);
3381 + spin_unlock(&host->lock);
3382 + if(!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)){
3383 + ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
3384 + ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3385 + ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA));
3386 + ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3387 + ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3388 + data->error = (unsigned int)-ETIMEDOUT;
3394 + spin_lock(&host->lock);
3395 + msdc_dma_stop(host);
3397 + /* Firstly: send command */
3398 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3402 + /* Secondly: pio data phase */
3404 + if (msdc_pio_read(host, data)){
3408 + if (msdc_pio_write(host, data)) {
3413 + /* For write case: make sure contents in fifo flushed to device */
3416 + left=msdc_txfifocnt();
3420 + if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
3422 + /* Fix me: what about if data error, when stop ? how to? */
3426 + /* Fix me: read case: need to check CRC error */
3429 + /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
3430 + For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
3433 + /* try not to wait xfer_comp interrupt.
3434 + the next command will check SDC_BUSY.
3435 + SDC_BUSY means xfer_comp assert
3440 + /* Last: stop transfer */
3442 + if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
3449 + if (data != NULL) {
3450 + host->data = NULL;
3451 + host->dma_xfer = 0;
3454 + host->dma.used_bd = 0;
3455 + host->dma.used_gpd = 0;
3456 + dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3460 +#if 0 // don't stop twice!
3461 + if(host->hw->flags & MSDC_REMOVABLE && data->error) {
3462 + msdc_abort_data(host);
3463 + /* reset in IRQ, stop command has issued. -> No need */
3467 + N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio"),
3468 + (read ? "read ":"write") ,data->blksz, data->blocks, data->error);
3471 +#if 0 /* --- by chhung */
3473 + //if(host->id==1) {
3474 + if(send_type==SND_CMD) {
3475 + if(cmd->opcode == MMC_SEND_STATUS) {
3476 + if((cmd->resp[0] & CARD_READY_FOR_DATA) ||(CARD_CURRENT_STATE(cmd->resp[0]) != 7)){
3477 + N_MSG(OPS,"disable clock, CMD13 IDLE");
3478 + msdc_gate_clock(host->id);
3481 + N_MSG(OPS,"disable clock, CMD<%d>", cmd->opcode);
3482 + msdc_gate_clock(host->id);
3486 + N_MSG(OPS,"disable clock!!! Read CMD<%d>",cmd->opcode);
3487 + msdc_gate_clock(host->id);
3492 + msdc_gate_clock(host->id);
3494 +#endif /* end of --- */
3496 + if (mrq->cmd->error) host->error = 0x001;
3497 + if (mrq->data && mrq->data->error) host->error |= 0x010;
3498 + if (mrq->stop && mrq->stop->error) host->error |= 0x100;
3500 + //if (host->error) ERR_MSG("host->error<%d>", host->error);
3502 + return host->error;
3505 +static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
3507 + struct mmc_command cmd;
3508 + struct mmc_request mrq;
3511 + memset(&cmd, 0, sizeof(struct mmc_command));
3512 + cmd.opcode = MMC_APP_CMD;
3513 +#if 0 /* bug: we meet mmc->card is null when ACMD6 */
3514 + cmd.arg = mmc->card->rca << 16;
3516 + cmd.arg = host->app_cmd_arg;
3518 + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
3520 + memset(&mrq, 0, sizeof(struct mmc_request));
3521 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3524 + err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
3528 +static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
3531 + u32 base = host->base;
3532 + u32 rsmpl, cur_rsmpl, orig_rsmpl;
3533 + u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
3536 + /* ==== don't support 3.0 now ====
3538 + 2: PAD_CMD_RESP_RXDLY[26:22]
3539 + ==========================*/
3541 + // save the previous tune result
3542 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
3543 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
3547 + for (rsmpl = 0; rsmpl < 2; rsmpl++) {
3548 + /* Lv1: R_SMPL[1] */
3549 + cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
3554 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
3556 + if (host->app_cmd) {
3557 + result = msdc_app_cmd(host->mmc, host);
3559 + ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
3560 + host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
3564 + result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
3565 + ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
3566 + (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
3568 + if (result == 0) {
3571 + if (result != (unsigned int)(-EIO)) {
3572 + ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
3576 + /* should be EIO */
3577 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
3578 + msdc_abort_data(host);
3582 + /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
3583 + cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
3584 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
3585 + }while (++rrdly < 32);
3590 +/* Support SD2.0 Only */
3591 +static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
3593 + struct msdc_host *host = mmc_priv(mmc);
3594 + u32 base = host->base;
3597 + u32 rxdly, cur_rxdly0, cur_rxdly1;
3598 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3599 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3600 + u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
3601 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3602 + u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
3606 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
3608 + /* Tune Method 2. */
3609 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3613 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3614 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3619 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3621 + if (host->app_cmd) {
3622 + result = msdc_app_cmd(host->mmc, host);
3624 + ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
3628 + result = msdc_do_request(mmc,mrq);
3630 + sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
3631 + if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
3632 + ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
3633 + (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
3634 + sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
3636 + /* Fix me: result is 0, but dcrc is still exist */
3637 + if (result == 0 && dcrc == 0) {
3640 + /* there is a case: command timeout, and data phase not processed */
3641 + if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
3642 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3643 + result, mrq->cmd->error, mrq->data->error);
3649 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3650 + cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
3652 + /* E1 ECO. YD: Reverse */
3653 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3654 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3655 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3656 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3657 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3658 + orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
3659 + orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
3660 + orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
3661 + orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
3663 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3664 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3665 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3666 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3667 + orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
3668 + orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
3669 + orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
3670 + orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
3674 + cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3675 + cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3676 + cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3677 + cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3679 + cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3680 + cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3681 + cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3682 + cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3684 + cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
3685 + cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
3686 + cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
3687 + cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
3689 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3690 + cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
3692 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3693 + sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
3695 + } while (++rxdly < 32);
3701 +static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
3703 + struct msdc_host *host = mmc_priv(mmc);
3704 + u32 base = host->base;
3706 + u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
3707 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3708 + u32 rxdly, cur_rxdly0;
3709 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3710 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3714 + // MSDC_IOCON_DDR50CKD need to check. [Fix me]
3716 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
3717 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl );
3719 + /* Tune Method 2. just DAT0 */
3720 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3721 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3723 + /* E1 ECO. YD: Reverse */
3724 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3725 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3726 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3727 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3728 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3730 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3731 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3732 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3733 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3740 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3741 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3746 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3748 + if (host->app_cmd) {
3749 + result = msdc_app_cmd(host->mmc, host);
3751 + ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
3755 + result = msdc_do_request(mmc,mrq);
3757 + ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
3758 + result == 0 ? "PASS" : "FAIL",
3759 + cur_dsmpl, cur_wrrdly, cur_rxdly0);
3761 + if (result == 0) {
3765 + /* there is a case: command timeout, and data phase not processed */
3766 + if (mrq->data->error != (unsigned int)(-EIO)) {
3767 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3768 + result, mrq->cmd->error, mrq->data->error);
3773 + cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
3774 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
3775 + } while (++wrrdly < 32);
3777 + cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
3778 + cur_dat1 = orig_dat1;
3779 + cur_dat2 = orig_dat2;
3780 + cur_dat3 = orig_dat3;
3782 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3783 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3784 + } while (++rxdly < 32);
3790 +static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
3792 + struct mmc_command cmd;
3793 + struct mmc_request mrq;
3796 + memset(&cmd, 0, sizeof(struct mmc_command));
3797 + cmd.opcode = MMC_SEND_STATUS;
3799 + cmd.arg = mmc->card->rca << 16;
3801 + ERR_MSG("cmd13 mmc card is null");
3802 + cmd.arg = host->app_cmd_arg;
3804 + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
3806 + memset(&mrq, 0, sizeof(struct mmc_request));
3807 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3810 + err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
3813 + *status = cmd.resp[0];
3819 +static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
3825 + err = msdc_get_card_status(mmc, host, &status);
3826 + if (err) return err;
3828 + ERR_MSG("cmd<13> resp<0x%x>", status);
3829 + } while (R1_CURRENT_STATE(status) == 7);
3834 +/* failed when msdc_do_request */
3835 +static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
3837 + struct msdc_host *host = mmc_priv(mmc);
3838 + struct mmc_command *cmd;
3839 + struct mmc_data *data;
3840 + //u32 base = host->base;
3844 + data = mrq->cmd->data;
3846 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3849 + if (data->error == (unsigned int)(-EIO)) {
3850 + ret = msdc_tune_bread(mmc,mrq);
3853 + ret = msdc_check_busy(mmc, host);
3855 + ERR_MSG("XXX cmd13 wait program done failed");
3859 + /* Fix me: don't care card status? */
3860 + ret = msdc_tune_bwrite(mmc,mrq);
3867 +static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
3869 + struct msdc_host *host = mmc_priv(mmc);
3871 + //=== for sdio profile ===
3872 +#if 0 /* --- by chhung */
3873 + u32 old_H32, old_L32, new_H32, new_L32;
3874 + u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
3875 +#endif /* end of --- */
3878 + ERR_MSG("XXX host->mrq<0x%.8x>", (int)host->mrq);
3882 + if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
3883 + ERR_MSG("cmd<%d> card<%d> power<%d>", mrq->cmd->opcode, is_card_present(host), host->power_mode);
3884 + mrq->cmd->error = (unsigned int)-ENOMEDIUM;
3887 + mrq->done(mrq); // call done directly.
3889 + mrq->cmd->retries = 0; // please don't retry.
3890 + mmc_request_done(mmc, mrq);
3896 + /* start to process */
3897 + spin_lock(&host->lock);
3898 +#if 0 /* --- by chhung */
3899 + if (sdio_pro_enable) { //=== for sdio profile ===
3900 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3901 + GPT_GetCounter64(&old_L32, &old_H32);
3904 +#endif /* end of --- */
3908 + if (msdc_do_request(mmc,mrq)) {
3909 + if(host->hw->flags & MSDC_REMOVABLE && mrq->data && mrq->data->error) {
3910 + //msdc_tune_request(mmc,mrq);
3914 + /* ==== when request done, check if app_cmd ==== */
3915 + if (mrq->cmd->opcode == MMC_APP_CMD) {
3916 + host->app_cmd = 1;
3917 + host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
3919 + host->app_cmd = 0;
3920 + //host->app_cmd_arg = 0;
3925 +#if 0 /* --- by chhung */
3926 + //=== for sdio profile ===
3927 + if (sdio_pro_enable) {
3928 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3929 + GPT_GetCounter64(&new_L32, &new_H32);
3930 + ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
3932 + opcode = mrq->cmd->opcode;
3933 + if (mrq->cmd->data) {
3934 + sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
3935 + bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0 ;
3937 + bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
3940 + if (!mrq->cmd->error) {
3941 + msdc_performance(opcode, sizes, bRx, ticks);
3945 +#endif /* end of --- */
3946 + spin_unlock(&host->lock);
3948 + mmc_request_done(mmc, mrq);
3953 +/* called by ops.set_ios */
3954 +static void msdc_set_buswidth(struct msdc_host *host, u32 width)
3956 + u32 base = host->base;
3957 + u32 val = sdr_read32(SDC_CFG);
3959 + val &= ~SDC_CFG_BUSWIDTH;
3963 + case MMC_BUS_WIDTH_1:
3965 + val |= (MSDC_BUS_1BITS << 16);
3967 + case MMC_BUS_WIDTH_4:
3968 + val |= (MSDC_BUS_4BITS << 16);
3970 + case MMC_BUS_WIDTH_8:
3971 + val |= (MSDC_BUS_8BITS << 16);
3975 + sdr_write32(SDC_CFG, val);
3977 + N_MSG(CFG, "Bus Width = %d", width);
3981 +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
3983 + struct msdc_host *host = mmc_priv(mmc);
3984 + struct msdc_hw *hw=host->hw;
3985 + u32 base = host->base;
3988 +#ifdef MT6575_SD_DEBUG
3989 + static char *vdd[] = {
3990 + "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
3991 + "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
3992 + "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
3993 + "3.40v", "3.50v", "3.60v"
3995 + static char *power_mode[] = {
3998 + static char *bus_mode[] = {
3999 + "UNKNOWN", "OPENDRAIN", "PUSHPULL"
4001 + static char *timing[] = {
4002 + "LEGACY", "MMC_HS", "SD_HS"
4005 + printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
4006 + ios->clock / 1000, bus_mode[ios->bus_mode],
4007 + (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
4008 + power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
4011 + msdc_set_buswidth(host, ios->bus_width);
4013 + /* Power control ??? */
4014 + switch (ios->power_mode) {
4015 + case MMC_POWER_OFF:
4016 + case MMC_POWER_UP:
4017 + // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
4019 + case MMC_POWER_ON:
4020 + host->power_mode = MMC_POWER_ON;
4026 + /* Clock control */
4027 + if (host->mclk != ios->clock) {
4028 + if(ios->clock > 25000000) {
4029 + //if (!(host->hw->flags & MSDC_REMOVABLE)) {
4030 + INIT_MSG("SD data latch edge<%d>", hw->data_edge);
4031 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
4032 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
4033 + //} /* for tuning debug */
4034 + } else { /* default value */
4035 + sdr_write32(MSDC_IOCON, 0x00000000);
4036 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4037 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4038 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4039 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4040 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4042 + msdc_set_mclk(host, ddr, ios->clock);
4047 +static int msdc_ops_get_ro(struct mmc_host *mmc)
4049 + struct msdc_host *host = mmc_priv(mmc);
4050 + u32 base = host->base;
4051 + unsigned long flags;
4054 + if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
4055 + spin_lock_irqsave(&host->lock, flags);
4056 + ro = (sdr_read32(MSDC_PS) >> 31);
4057 + spin_unlock_irqrestore(&host->lock, flags);
4063 +static int msdc_ops_get_cd(struct mmc_host *mmc)
4065 + struct msdc_host *host = mmc_priv(mmc);
4066 + u32 base = host->base;
4067 + unsigned long flags;
4070 + /* for sdio, MSDC_REMOVABLE not set, always return 1 */
4071 + if (!(host->hw->flags & MSDC_REMOVABLE)) {
4072 + /* For sdio, read H/W always get<1>, but may timeout some times */
4074 + host->card_inserted = 1;
4077 + host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
4078 + INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
4079 + return host->card_inserted;
4083 + /* MSDC_CD_PIN_EN set for card */
4084 + if (host->hw->flags & MSDC_CD_PIN_EN) {
4085 + spin_lock_irqsave(&host->lock, flags);
4087 + present = host->card_inserted; /* why not read from H/W: Fix me*/
4090 + if (cd_active_low)
4091 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
4093 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 1 : 0;
4094 + host->card_inserted = present;
4096 + spin_unlock_irqrestore(&host->lock, flags);
4098 + present = 0; /* TODO? Check DAT3 pins for card detection */
4101 + INIT_MSG("ops_get_cd return<%d>", present);
4105 +/* ops.enable_sdio_irq */
4106 +static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
4108 + struct msdc_host *host = mmc_priv(mmc);
4109 + struct msdc_hw *hw = host->hw;
4110 + u32 base = host->base;
4113 + if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
4115 + hw->enable_sdio_eirq(); /* combo_sdio_enable_eirq */
4117 + hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
4120 + ERR_MSG("XXX "); /* so never enter here */
4121 + tmp = sdr_read32(SDC_CFG);
4122 + /* FIXME. Need to interrupt gap detection */
4124 + tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4126 + tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4128 + sdr_write32(SDC_CFG, tmp);
4132 +static struct mmc_host_ops mt_msdc_ops = {
4133 + .request = msdc_ops_request,
4134 + .set_ios = msdc_ops_set_ios,
4135 + .get_ro = msdc_ops_get_ro,
4136 + .get_cd = msdc_ops_get_cd,
4137 + .enable_sdio_irq = msdc_ops_enable_sdio_irq,
4140 +/*--------------------------------------------------------------------------*/
4141 +/* interrupt handler */
4142 +/*--------------------------------------------------------------------------*/
4143 +static irqreturn_t msdc_irq(int irq, void *dev_id)
4145 + struct msdc_host *host = (struct msdc_host *)dev_id;
4146 + struct mmc_data *data = host->data;
4147 + struct mmc_command *cmd = host->cmd;
4148 + u32 base = host->base;
4150 + u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
4151 + MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
4152 + MSDC_INT_ACMD19_DONE;
4153 + u32 datsts = MSDC_INT_DATCRCERR |MSDC_INT_DATTMO;
4155 + u32 intsts = sdr_read32(MSDC_INT);
4156 + u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
4158 + sdr_write32(MSDC_INT, intsts); /* clear interrupts */
4159 + /* MSG will cause fatal error */
4161 + /* card change interrupt */
4162 + if (intsts & MSDC_INT_CDSC){
4164 + return IRQ_HANDLED;
4165 + IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
4166 +#if 0 /* ---/+++ by chhung: fix slot mechanical bounce issue */
4167 + tasklet_hi_schedule(&host->card_tasklet);
4169 + schedule_delayed_work(&host->card_delaywork, HZ);
4171 + /* tuning when plug card ? */
4174 + /* sdio interrupt */
4175 + if (intsts & MSDC_INT_SDIOIRQ){
4176 + IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
4177 + //mmc_signal_sdio_irq(host->mmc);
4180 + /* transfer complete interrupt */
4181 + if (data != NULL) {
4182 + if (inten & MSDC_INT_XFER_COMPL) {
4183 + data->bytes_xfered = host->dma.xfersz;
4184 + complete(&host->xfer_done);
4187 + if (intsts & datsts) {
4188 + /* do basic reset, or stop command will sdc_busy */
4192 + atomic_set(&host->abort, 1); /* For PIO mode exit */
4194 + if (intsts & MSDC_INT_DATTMO){
4195 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
4196 + data->error = (unsigned int)-ETIMEDOUT;
4198 + else if (intsts & MSDC_INT_DATCRCERR){
4199 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
4200 + data->error = (unsigned int)-EIO;
4203 + //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
4204 + if (host->dma_xfer) {
4205 + complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
4206 + } /* PIO mode can't do complete, because not init */
4210 + /* command interrupts */
4211 + if ((cmd != NULL) && (intsts & cmdsts)) {
4212 + if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
4213 + (intsts & MSDC_INT_ACMD19_DONE)) {
4214 + u32 *rsp = &cmd->resp[0];
4216 + switch (host->cmd_rsp) {
4220 + *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
4221 + *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
4223 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
4224 + if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
4225 + *rsp = sdr_read32(SDC_ACMD_RESP);
4227 + *rsp = sdr_read32(SDC_RESP0);
4231 + } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
4232 + if(intsts & MSDC_INT_ACMDCRCERR){
4233 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR",cmd->opcode);
4236 + IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR",cmd->opcode);
4238 + cmd->error = (unsigned int)-EIO;
4239 + } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
4240 + if(intsts & MSDC_INT_ACMDTMO){
4241 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO",cmd->opcode);
4244 + IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO",cmd->opcode);
4246 + cmd->error = (unsigned int)-ETIMEDOUT;
4251 + complete(&host->cmd_done);
4254 + /* mmc irq interrupts */
4255 + if (intsts & MSDC_INT_MMCIRQ) {
4256 + printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
4259 +#ifdef MT6575_SD_DEBUG
4261 + msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
4262 + N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
4266 + int_reg->atocmdrdy,
4267 + int_reg->atocmdtmo,
4268 + int_reg->atocmdcrc,
4269 + int_reg->atocmd19done);
4270 + N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
4277 + N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
4279 + int_reg->xfercomp,
4280 + int_reg->dxferdone,
4283 + int_reg->dmaqempty);
4288 + return IRQ_HANDLED;
4291 +/*--------------------------------------------------------------------------*/
4292 +/* platform_driver members */
4293 +/*--------------------------------------------------------------------------*/
4294 +/* called by msdc_drv_probe/remove */
4295 +static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
4297 + struct msdc_hw *hw = host->hw;
4298 + u32 base = host->base;
4300 + /* for sdio, not set */
4301 + if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
4302 + /* Pull down card detection pin since it is not avaiable */
4304 + if (hw->config_gpio_pin)
4305 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4307 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4308 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4309 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4313 + N_MSG(CFG, "CD IRQ Eanable(%d)", enable);
4316 + if (hw->enable_cd_eirq) { /* not set, never enter */
4317 + hw->enable_cd_eirq();
4319 + /* card detection circuit relies on the core power so that the core power
4320 + * shouldn't be turned off. Here adds a reference count to keep
4321 + * the core power alive.
4323 + //msdc_vcore_on(host); //did in msdc_init_hw()
4325 + if (hw->config_gpio_pin) /* NULL */
4326 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
4328 + sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
4329 + sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
4330 + sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4331 + sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
4334 + if (hw->disable_cd_eirq) {
4335 + hw->disable_cd_eirq();
4337 + if (hw->config_gpio_pin) /* NULL */
4338 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4340 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4341 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4342 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4344 + /* Here decreases a reference count to core power since card
4345 + * detection circuit is shutdown.
4347 + //msdc_vcore_off(host);
4352 +/* called by msdc_drv_probe */
4353 +static void msdc_init_hw(struct msdc_host *host)
4355 + u32 base = host->base;
4356 + struct msdc_hw *hw = host->hw;
4358 +#ifdef MT6575_SD_DEBUG
4359 + msdc_reg[host->id] = (struct msdc_regs *)host->base;
4363 +#if 0 /* --- by chhung */
4364 + msdc_vcore_on(host);
4365 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
4366 + msdc_select_clksrc(host, hw->clk_src);
4367 + enable_clock(PERI_MSDC0_PDN + host->id, "SD");
4368 + msdc_vdd_on(host);
4369 +#endif /* end of --- */
4370 + /* Configure to MMC/SD mode */
4371 + sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
4377 + /* Disable card detection */
4378 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4380 + /* Disable and clear all interrupts */
4381 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4382 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4385 + /* reset tuning parameter */
4386 + sdr_write32(MSDC_PAD_CTL0, 0x00090000);
4387 + sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
4388 + sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
4389 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4390 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4391 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4392 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4393 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4394 + sdr_write32(MSDC_IOCON, 0x00000000);
4395 +#if 0 // use MT7620 default value: 0x403c004f
4396 + sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
4399 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
4400 + if (host->id == 1) {
4401 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
4402 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
4404 + /* internal clock: latch read data */
4405 + sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
4410 + /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
4411 + pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
4412 + set when kernel driver wants to use SDIO bus interrupt */
4413 + /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
4414 + sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
4416 + /* disable detect SDIO device interupt function */
4417 + sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
4419 + /* eneable SMT for glitch filter */
4420 + sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
4421 + sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
4422 + sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
4425 + /* set clk, cmd, dat pad driving */
4426 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
4427 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
4428 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
4429 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
4430 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
4431 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
4433 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
4434 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
4435 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
4436 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
4437 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
4438 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
4441 + /* set sampling edge */
4443 + /* write crc timeout detection */
4444 + sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
4446 + /* Configure to default data timeout */
4447 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
4449 + msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
4451 + N_MSG(FUC, "init hardware done!");
4454 +/* called by msdc_drv_remove */
4455 +static void msdc_deinit_hw(struct msdc_host *host)
4457 + u32 base = host->base;
4459 + /* Disable and clear all interrupts */
4460 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4461 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4463 + /* Disable card detection */
4464 + msdc_enable_cd_irq(host, 0);
4465 + // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
4468 +/* init gpd and bd list in msdc_drv_probe */
4469 +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
4471 + gpd_t *gpd = dma->gpd;
4472 + bd_t *bd = dma->bd;
4475 + /* we just support one gpd */
4476 + int bdlen = MAX_BD_PER_GPD;
4478 + /* init the 2 gpd */
4479 + memset(gpd, 0, sizeof(gpd_t) * 2);
4480 + //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */
4481 + //gpd->next = (dma->gpd_addr + 1); /* bug */
4482 + gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));
4485 + gpd->bdp = 1; /* hwo, cs, bd pointer */
4486 + //gpd->ptr = (void*)virt_to_phys(bd);
4487 + gpd->ptr = (void *)dma->bd_addr; /* physical address */
4489 + memset(bd, 0, sizeof(bd_t) * bdlen);
4490 + ptr = bd + bdlen - 1;
4491 + //ptr->eol = 1; /* 0 or 1 [Fix me]*/
4494 + while (ptr != bd) {
4496 + prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
4501 +static int msdc_drv_probe(struct platform_device *pdev)
4503 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4504 + __iomem void *base;
4505 + struct mmc_host *mmc;
4506 + struct resource *mem;
4507 + struct msdc_host *host;
4508 + struct msdc_hw *hw;
4511 + pdev->dev.platform_data = &msdc0_hw;
4513 + /* Allocate MMC host for this device */
4514 + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
4515 + if (!mmc) return -ENOMEM;
4517 + hw = (struct msdc_hw*)pdev->dev.platform_data;
4518 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4519 + irq = platform_get_irq(pdev, 0);
4521 + //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
4523 + base = devm_ioremap_resource(&pdev->dev, res);
4525 + return PTR_ERR(base);
4527 + /* Set host parameters to mmc */
4528 + mmc->ops = &mt_msdc_ops;
4529 + mmc->f_min = HOST_MIN_MCLK;
4530 + mmc->f_max = HOST_MAX_MCLK;
4531 + mmc->ocr_avail = MSDC_OCR_AVAIL;
4533 + /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
4534 + For sdio : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
4535 + if (hw->flags & MSDC_HIGHSPEED) {
4536 + mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
4538 + if (hw->data_pins == 4) { /* current data_pins are all 4*/
4539 + mmc->caps |= MMC_CAP_4_BIT_DATA;
4540 + } else if (hw->data_pins == 8) {
4541 + mmc->caps |= MMC_CAP_8_BIT_DATA;
4543 + if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
4544 + mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
4546 + cd_active_low = !of_property_read_bool(pdev->dev.of_node, "mediatek,cd-high");
4547 + mtk_sw_poll = of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll");
4550 + mmc->caps |= MMC_CAP_NEEDS_POLL;
4552 + /* MMC core transfer sizes tunable parameters */
4553 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
4554 + mmc->max_segs = MAX_HW_SGMTS;
4556 + mmc->max_hw_segs = MAX_HW_SGMTS;
4557 + mmc->max_phys_segs = MAX_PHY_SGMTS;
4559 + mmc->max_seg_size = MAX_SGMT_SZ;
4560 + mmc->max_blk_size = HOST_MAX_BLKSZ;
4561 + mmc->max_req_size = MAX_REQ_SZ;
4562 + mmc->max_blk_count = mmc->max_req_size;
4564 + host = mmc_priv(mmc);
4567 + host->id = pdev->id;
4570 + host->base = (unsigned long) base;
4571 + host->mclk = 0; /* mclk: the request clock of mmc sub-system */
4572 + host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
4573 + host->sclk = 0; /* sclk: the really clock after divition */
4574 + host->pm_state = PMSG_RESUME;
4575 + host->suspend = 0;
4576 + host->core_clkon = 0;
4577 + host->card_clkon = 0;
4578 + host->core_power = 0;
4579 + host->power_mode = MMC_POWER_OFF;
4580 +// host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
4581 + host->timeout_ns = 0;
4582 + host->timeout_clks = DEFAULT_DTOC * 65536;
4585 + //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
4587 + host->dma.used_gpd = 0;
4588 + host->dma.used_bd = 0;
4590 + /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
4591 + host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL);
4592 + host->dma.bd = dma_alloc_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), &host->dma.bd_addr, GFP_KERNEL);
4593 + BUG_ON((!host->dma.gpd) || (!host->dma.bd));
4594 + msdc_init_gpd_bd(host, &host->dma);
4596 + msdc_6575_host[pdev->id] = host;
4599 + tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
4601 + INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
4603 + spin_lock_init(&host->lock);
4604 + msdc_init_hw(host);
4606 + ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
4607 + if (ret) goto release;
4608 + // mt65xx_irq_unmask(irq); /* --- by chhung */
4610 + if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
4611 + if (hw->request_cd_eirq) { /* not set for MT6575 */
4612 + hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
4616 + if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
4617 + hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
4619 + if (hw->register_pm) {/* yes for sdio */
4621 + hw->register_pm(msdc_pm, (void*)host); /* combo_sdio_register_pm() */
4623 + if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
4624 + ERR_MSG("MSDC_SYS_SUSPEND and register_pm both set");
4626 + //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
4629 + platform_set_drvdata(pdev, mmc);
4631 + ret = mmc_add_host(mmc);
4632 + if (ret) goto free_irq;
4634 + /* Config card detection pin and enable interrupts */
4635 + if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
4636 + msdc_enable_cd_irq(host, 1);
4638 + msdc_enable_cd_irq(host, 0);
4644 + free_irq(irq, host);
4646 + platform_set_drvdata(pdev, NULL);
4647 + msdc_deinit_hw(host);
4650 + tasklet_kill(&host->card_tasklet);
4652 + cancel_delayed_work_sync(&host->card_delaywork);
4656 + release_mem_region(mem->start, mem->end - mem->start + 1);
4658 + mmc_free_host(mmc);
4663 +/* 4 device share one driver, using "drvdata" to show difference */
4664 +static int msdc_drv_remove(struct platform_device *pdev)
4666 + struct mmc_host *mmc;
4667 + struct msdc_host *host;
4668 + struct resource *mem;
4670 + mmc = platform_get_drvdata(pdev);
4673 + host = mmc_priv(mmc);
4676 + ERR_MSG("removed !!!");
4678 + platform_set_drvdata(pdev, NULL);
4679 + mmc_remove_host(host->mmc);
4680 + msdc_deinit_hw(host);
4683 + tasklet_kill(&host->card_tasklet);
4685 + cancel_delayed_work_sync(&host->card_delaywork);
4687 + free_irq(host->irq, host);
4689 + dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
4690 + dma_free_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), host->dma.bd, host->dma.bd_addr);
4692 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4695 + release_mem_region(mem->start, mem->end - mem->start + 1);
4697 + mmc_free_host(host->mmc);
4702 +/* Fix me: Power Flow */
4704 +static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
4707 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4708 + struct msdc_host *host = mmc_priv(mmc);
4710 + if (mmc && state.event == PM_EVENT_SUSPEND && (host->hw->flags & MSDC_SYS_SUSPEND)) { /* will set for card */
4711 + msdc_pm(state, (void*)host);
4717 +static int msdc_drv_resume(struct platform_device *pdev)
4720 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4721 + struct msdc_host *host = mmc_priv(mmc);
4722 + struct pm_message state;
4724 + state.event = PM_EVENT_RESUME;
4725 + if (mmc && (host->hw->flags & MSDC_SYS_SUSPEND)) {/* will set for card */
4726 + msdc_pm(state, (void*)host);
4729 + /* This mean WIFI not controller by PM */
4735 +static const struct of_device_id mt7620_sdhci_match[] = {
4736 + { .compatible = "ralink,mt7620-sdhci" },
4739 +MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
4741 +static struct platform_driver mt_msdc_driver = {
4742 + .probe = msdc_drv_probe,
4743 + .remove = msdc_drv_remove,
4745 + .suspend = msdc_drv_suspend,
4746 + .resume = msdc_drv_resume,
4750 + .owner = THIS_MODULE,
4751 + .of_match_table = mt7620_sdhci_match,
4755 +/*--------------------------------------------------------------------------*/
4756 +/* module init/exit */
4757 +/*--------------------------------------------------------------------------*/
4758 +static int __init mt_msdc_init(void)
4761 +/* +++ by chhung */
4764 +#if defined (CONFIG_MTD_ANY_RALINK)
4765 + extern int ra_check_flash_type(void);
4766 + if(ra_check_flash_type() == 2) { /* NAND */
4767 + printk("%s: !!!!! SDXC Module Initialize Fail !!!!!", __func__);
4771 + printk("MTK MSDC device init.\n");
4772 + mtk_sd_device.dev.platform_data = &msdc0_hw;
4773 +if (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7621AT) {
4774 +//#if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
4775 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<18);
4776 +//#if defined (CONFIG_RALINK_MT7620)
4777 + if (ralink_soc == MT762X_SOC_MT7620A)
4781 +//#elif defined (CONFIG_RALINK_MT7628)
4782 + /* TODO: maybe omitted when RAether already toggle AGPIO_CFG */
4783 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c));
4784 + reg |= 0x1e << 16;
4785 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c), reg);
4787 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<10);
4788 +#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
4789 + reg |= 0x3<<26 | 0x3<<28 | 0x3<<30;
4790 + msdc0_hw.data_pins = 8,
4794 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60), reg);
4795 + //platform_device_register(&mtk_sd_device);
4798 + ret = platform_driver_register(&mt_msdc_driver);
4800 + printk(KERN_ERR DRV_NAME ": Can't register driver");
4803 + printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
4805 +#if defined (MT6575_SD_DEBUG)
4806 + msdc_debug_proc_init();
4811 +static void __exit mt_msdc_exit(void)
4813 +// platform_device_unregister(&mtk_sd_device);
4814 + platform_driver_unregister(&mt_msdc_driver);
4817 +module_init(mt_msdc_init);
4818 +module_exit(mt_msdc_exit);
4819 +MODULE_LICENSE("GPL");
4820 +MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
4821 +MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
4823 +EXPORT_SYMBOL(msdc_6575_host);