1 From 3f0a06b0368d25608841843e9d65a7289ad9f14a Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 20 Jan 2013 22:01:29 +0100
4 Subject: [PATCH 05/14] MIPS: ralink: adds clkdev code
6 These SoCs have a limited number of fixed rate clocks. Add support for the
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
11 Patchwork: http://patchwork.linux-mips.org/patch/4894/
13 arch/mips/ralink/clk.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++
14 1 file changed, 72 insertions(+)
15 create mode 100644 arch/mips/ralink/clk.c
18 +++ b/arch/mips/ralink/clk.c
21 + * This program is free software; you can redistribute it and/or modify it
22 + * under the terms of the GNU General Public License version 2 as published
23 + * by the Free Software Foundation.
25 + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
26 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
29 +#include <linux/kernel.h>
30 +#include <linux/module.h>
31 +#include <linux/clkdev.h>
32 +#include <linux/clk.h>
34 +#include <asm/time.h>
39 + struct clk_lookup cl;
43 +void ralink_clk_add(const char *dev, unsigned long rate)
45 + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
48 + panic("failed to add clock\n");
50 + clk->cl.dev_id = dev;
55 + clkdev_add(&clk->cl);
61 +int clk_enable(struct clk *clk)
65 +EXPORT_SYMBOL_GPL(clk_enable);
67 +void clk_disable(struct clk *clk)
70 +EXPORT_SYMBOL_GPL(clk_disable);
72 +unsigned long clk_get_rate(struct clk *clk)
76 +EXPORT_SYMBOL_GPL(clk_get_rate);
78 +void __init plat_time_init(void)
85 + clk = clk_get_sys("cpu", NULL);
87 + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
88 + pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
89 + mips_hpt_frequency = clk_get_rate(clk) / 2;