1 From dcc7310e144c3bf17a86d2f058d60fb525d4b34a Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 31 Jan 2013 13:44:10 +0100
4 Subject: [PATCH 12/14] Document: devicetree: add OF documents for MIPS
7 Signed-off-by: John Crispin <blogic@openwrt.org>
8 Acked-by: David Daney <david.daney@cavium.com>
9 Patchwork: http://patchwork.linux-mips.org/patch/4901/
11 Documentation/devicetree/bindings/mips/cpu_irq.txt | 47 ++++++++++++++++++++
12 1 file changed, 47 insertions(+)
13 create mode 100644 Documentation/devicetree/bindings/mips/cpu_irq.txt
16 +++ b/Documentation/devicetree/bindings/mips/cpu_irq.txt
18 +MIPS CPU interrupt controller
20 +On MIPS the mips_cpu_intc_init() helper can be used to initialize the 8 CPU
21 +IRQs from a devicetree file and create a irq_domain for IRQ controller.
23 +With the irq_domain in place we can describe how the 8 IRQs are wired to the
24 +platforms internal interrupt controller cascade.
26 +Below is an example of a platform describing the cascade inside the devicetree
27 +and the code used to load it inside arch_init_irq().
30 +- compatible : Should be "mti,cpu-interrupt-controller"
33 + cpu-irq: cpu-irq@0 {
34 + #address-cells = <0>;
36 + interrupt-controller;
37 + #interrupt-cells = <1>;
39 + compatible = "mti,cpu-interrupt-controller";
43 + compatible = "ralink,rt2880-intc";
44 + reg = <0x200 0x100>;
46 + interrupt-controller;
47 + #interrupt-cells = <1>;
49 + interrupt-parent = <&cpu-irq>;
54 +Example platform irq.c:
55 +static struct of_device_id __initdata of_irq_ids[] = {
56 + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
57 + { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
61 +void __init arch_init_irq(void)
63 + of_irq_init(of_irq_ids);