[ramips] add patches for v3.8
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.8 / 0100-MIPS-ralink-fix-RT305x-clock-setup.patch
1 From eb8d7fbba907df0a51e504930c00b2c9ec837b54 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 22 Mar 2013 19:25:59 +0100
4 Subject: [PATCH 100/121] MIPS: ralink: fix RT305x clock setup
5
6 Add a few missing clocks and remove the unused sys clock.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 arch/mips/ralink/rt305x.c | 14 ++++++++++++++
11 1 file changed, 14 insertions(+)
12
13 diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
14 index 0a4bbdc..856ebff 100644
15 --- a/arch/mips/ralink/rt305x.c
16 +++ b/arch/mips/ralink/rt305x.c
17 @@ -125,6 +125,7 @@ void __init ralink_clk_init(void)
18 {
19 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
20 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
21 + int wmac_20mhz = 0;
22
23 if (soc_is_rt305x() || soc_is_rt3350()) {
24 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
25 @@ -176,11 +177,24 @@ void __init ralink_clk_init(void)
26 BUG();
27 }
28
29 + if (soc_is_rt3352() || soc_is_rt5350()) {
30 + u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
31 + if ((val & RT3352_CLKCFG0_XTAL_SEL) == 0)
32 + wmac_20mhz = 1;
33 + }
34 +
35 ralink_clk_add("cpu", cpu_rate);
36 ralink_clk_add("10000b00.spi", sys_rate);
37 ralink_clk_add("10000100.timer", wdt_rate);
38 + ralink_clk_add("10000120.watchdog", wdt_rate);
39 ralink_clk_add("10000500.uart", uart_rate);
40 ralink_clk_add("10000c00.uartlite", uart_rate);
41 + ralink_clk_add("10100000.ethernet", sys_rate);
42 +
43 + if (wmac_20mhz)
44 + ralink_clk_add("10180000.wmac", 20000000);
45 + else
46 + ralink_clk_add("10180000.wmac", 40000000);
47 }
48
49 void __init ralink_of_remap(void)
50 --
51 1.7.10.4
52