1 From b72ae753b73cbc4b488dcdbf997faec199c8bb3f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 21 Mar 2013 18:29:02 +0100
4 Subject: [PATCH 108/121] MIPS: add rt2880 dts files
6 Add a dtsi file for RT2880 SoC and a sample dts file. This SoC is first one that
7 was released in this SoC family.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/ralink/Kconfig | 4 ++
12 arch/mips/ralink/dts/Makefile | 1 +
13 arch/mips/ralink/dts/rt2880.dtsi | 116 ++++++++++++++++++++++++++++++++++
14 arch/mips/ralink/dts/rt2880_eval.dts | 52 +++++++++++++++
15 4 files changed, 173 insertions(+)
16 create mode 100644 arch/mips/ralink/dts/rt2880.dtsi
17 create mode 100644 arch/mips/ralink/dts/rt2880_eval.dts
19 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
20 index 6723b94..0d312fc 100644
21 --- a/arch/mips/ralink/Kconfig
22 +++ b/arch/mips/ralink/Kconfig
23 @@ -26,6 +26,10 @@ choice
27 + config DTB_RT2880_EVAL
28 + bool "RT2880 eval kit"
29 + depends on SOC_RT288X
31 config DTB_RT305X_EVAL
32 bool "RT305x eval kit"
34 diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile
35 index 1a69fb3..f635a01 100644
36 --- a/arch/mips/ralink/dts/Makefile
37 +++ b/arch/mips/ralink/dts/Makefile
39 +obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
40 obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
41 diff --git a/arch/mips/ralink/dts/rt2880.dtsi b/arch/mips/ralink/dts/rt2880.dtsi
43 index 0000000..b51c227
45 +++ b/arch/mips/ralink/dts/rt2880.dtsi
48 + #address-cells = <1>;
50 + compatible = "ralink,rt2880-soc";
54 + compatible = "mips,mips24KEc";
59 + bootargs = "console=ttyS0,57600 init=/init";
62 + cpuintc: cpuintc@0 {
63 + #address-cells = <0>;
64 + #interrupt-cells = <1>;
65 + interrupt-controller;
66 + compatible = "mti,cpu-interrupt-controller";
70 + compatible = "palmbus";
71 + reg = <0x10000000 0x200000>;
72 + ranges = <0x0 0x10000000 0x1FFFFF>;
74 + #address-cells = <1>;
78 + compatible = "ralink,rt2880-sysc";
79 + reg = <0x300000 0x100>;
83 + compatible = "ralink,rt2880-timer";
84 + reg = <0x300100 0x20>;
86 + interrupt-parent = <&intc>;
89 + status = "disabled";
93 + compatible = "ralink,rt2880-wdt";
94 + reg = <0x300120 0x10>;
98 + compatible = "ralink,rt2880-intc";
99 + reg = <0x300200 0x100>;
101 + interrupt-controller;
102 + #interrupt-cells = <1>;
104 + interrupt-parent = <&cpuintc>;
109 + compatible = "ralink,rt2880-memc";
110 + reg = <0x300300 0x100>;
113 + gpio0: gpio@300600 {
114 + compatible = "ralink,rt2880-gpio";
115 + reg = <0x300600 0x34>;
120 + ralink,num-gpios = <24>;
121 + ralink,register-map = [ 00 04 08 0c
126 + gpio1: gpio@300638 {
127 + compatible = "ralink,rt2880-gpio";
128 + reg = <0x300638 0x24>;
133 + ralink,num-gpios = <16>;
134 + ralink,register-map = [ 00 04 08 0c
139 + gpio2: gpio@300660 {
140 + compatible = "ralink,rt2880-gpio";
141 + reg = <0x300660 0x24>;
146 + ralink,num-gpios = <32>;
147 + ralink,register-map = [ 00 04 08 0c
153 + compatible = "ralink,rt2880-uart", "ns16550a";
154 + reg = <0x300c00 0x100>;
156 + interrupt-parent = <&intc>;
163 diff --git a/arch/mips/ralink/dts/rt2880_eval.dts b/arch/mips/ralink/dts/rt2880_eval.dts
165 index 0000000..7c74e16
167 +++ b/arch/mips/ralink/dts/rt2880_eval.dts
171 +/include/ "rt2880.dtsi"
174 + #address-cells = <1>;
176 + compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";
177 + model = "Ralink RT2880 evaluation board";
180 + reg = <0x0 0x2000000>;
185 + ralink,pinmmux = "uartlite", "spi";
186 + ralink,uartmux = "gpio";
187 + ralink,wdtmux = <0>;
192 + compatible = "cfi-flash";
193 + reg = <0x1f000000 0x800000>;
196 + device-width = <2>;
197 + #address-cells = <1>;
202 + reg = <0x0 0x30000>;
206 + label = "uboot-env";
207 + reg = <0x30000 0x10000>;
211 + label = "calibration";
212 + reg = <0x40000 0x10000>;
217 + reg = <0x50000 0x7b0000>;