1 From b72ae753b73cbc4b488dcdbf997faec199c8bb3f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 21 Mar 2013 18:29:02 +0100
4 Subject: [PATCH 108/121] MIPS: add rt2880 dts files
6 Add a dtsi file for RT2880 SoC and a sample dts file. This SoC is first one that
7 was released in this SoC family.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/ralink/Kconfig | 4 ++
12 arch/mips/ralink/dts/Makefile | 1 +
13 arch/mips/ralink/dts/rt2880.dtsi | 116 ++++++++++++++++++++++++++++++++++
14 arch/mips/ralink/dts/rt2880_eval.dts | 52 +++++++++++++++
15 4 files changed, 173 insertions(+)
16 create mode 100644 arch/mips/ralink/dts/rt2880.dtsi
17 create mode 100644 arch/mips/ralink/dts/rt2880_eval.dts
19 --- a/arch/mips/ralink/Kconfig
20 +++ b/arch/mips/ralink/Kconfig
21 @@ -26,6 +26,10 @@ choice
25 + config DTB_RT2880_EVAL
26 + bool "RT2880 eval kit"
27 + depends on SOC_RT288X
29 config DTB_RT305X_EVAL
30 bool "RT305x eval kit"
32 --- a/arch/mips/ralink/dts/Makefile
33 +++ b/arch/mips/ralink/dts/Makefile
35 +obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
36 obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
38 +++ b/arch/mips/ralink/dts/rt2880.dtsi
41 + #address-cells = <1>;
43 + compatible = "ralink,rt2880-soc";
47 + compatible = "mips,mips24KEc";
52 + bootargs = "console=ttyS0,57600 init=/init";
55 + cpuintc: cpuintc@0 {
56 + #address-cells = <0>;
57 + #interrupt-cells = <1>;
58 + interrupt-controller;
59 + compatible = "mti,cpu-interrupt-controller";
63 + compatible = "palmbus";
64 + reg = <0x10000000 0x200000>;
65 + ranges = <0x0 0x10000000 0x1FFFFF>;
67 + #address-cells = <1>;
71 + compatible = "ralink,rt2880-sysc";
72 + reg = <0x300000 0x100>;
76 + compatible = "ralink,rt2880-timer";
77 + reg = <0x300100 0x20>;
79 + interrupt-parent = <&intc>;
82 + status = "disabled";
86 + compatible = "ralink,rt2880-wdt";
87 + reg = <0x300120 0x10>;
91 + compatible = "ralink,rt2880-intc";
92 + reg = <0x300200 0x100>;
94 + interrupt-controller;
95 + #interrupt-cells = <1>;
97 + interrupt-parent = <&cpuintc>;
102 + compatible = "ralink,rt2880-memc";
103 + reg = <0x300300 0x100>;
106 + gpio0: gpio@300600 {
107 + compatible = "ralink,rt2880-gpio";
108 + reg = <0x300600 0x34>;
113 + ralink,num-gpios = <24>;
114 + ralink,register-map = [ 00 04 08 0c
119 + gpio1: gpio@300638 {
120 + compatible = "ralink,rt2880-gpio";
121 + reg = <0x300638 0x24>;
126 + ralink,num-gpios = <16>;
127 + ralink,register-map = [ 00 04 08 0c
132 + gpio2: gpio@300660 {
133 + compatible = "ralink,rt2880-gpio";
134 + reg = <0x300660 0x24>;
139 + ralink,num-gpios = <32>;
140 + ralink,register-map = [ 00 04 08 0c
146 + compatible = "ralink,rt2880-uart", "ns16550a";
147 + reg = <0x300c00 0x100>;
149 + interrupt-parent = <&intc>;
157 +++ b/arch/mips/ralink/dts/rt2880_eval.dts
161 +/include/ "rt2880.dtsi"
164 + #address-cells = <1>;
166 + compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";
167 + model = "Ralink RT2880 evaluation board";
170 + reg = <0x0 0x2000000>;
175 + ralink,pinmux = "uartlite", "spi";
176 + ralink,uartmux = "gpio";
177 + ralink,wdtmux = <0>;
182 + compatible = "cfi-flash";
183 + reg = <0x1f000000 0x800000>;
186 + device-width = <2>;
187 + #address-cells = <1>;
192 + reg = <0x0 0x30000>;
196 + label = "uboot-env";
197 + reg = <0x30000 0x10000>;
201 + label = "calibration";
202 + reg = <0x40000 0x10000>;
207 + reg = <0x50000 0x7b0000>;