1 From 8831277e0167cdcf3dc3ecc5d5a67d4fd9d0ed77 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 21 Mar 2013 17:49:02 +0100
4 Subject: [PATCH 111/121] MIPS: ralink: adds support for MT7620 SoC family
6 Add support code for mt7620 SOC.
8 The code detects the SoC and registers the clk / pinmux settings.
10 Signed-off-by: John Crispin <blogic@openwrt.org>
12 arch/mips/include/asm/mach-ralink/mt7620.h | 66 +++++++++
13 arch/mips/ralink/Kconfig | 3 +
14 arch/mips/ralink/Makefile | 1 +
15 arch/mips/ralink/Platform | 5 +
16 arch/mips/ralink/mt7620.c | 215 ++++++++++++++++++++++++++++
17 5 files changed, 290 insertions(+)
18 create mode 100644 arch/mips/include/asm/mach-ralink/mt7620.h
19 create mode 100644 arch/mips/ralink/mt7620.c
22 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
25 + * This program is free software; you can redistribute it and/or modify it
26 + * under the terms of the GNU General Public License version 2 as published
27 + * by the Free Software Foundation.
29 + * Parts of this file are based on Ralink's 2.6.21 BSP
31 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
32 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
33 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
36 +#ifndef _MT7620_REGS_H_
37 +#define _MT7620_REGS_H_
39 +#define MT7620_SYSC_BASE 0x10000000
41 +#define SYSC_REG_CHIP_NAME0 0x00
42 +#define SYSC_REG_CHIP_NAME1 0x04
43 +#define SYSC_REG_CHIP_REV 0x0c
44 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
45 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
46 +#define SYSC_REG_CPLL_CONFIG0 0x54
47 +#define SYSC_REG_CPLL_CONFIG1 0x58
49 +#define MT7620N_CHIP_NAME0 0x33365452
50 +#define MT7620N_CHIP_NAME1 0x20203235
52 +#define MT7620A_CHIP_NAME0 0x3637544d
53 +#define MT7620A_CHIP_NAME1 0x20203032
55 +#define CHIP_REV_PKG_MASK 0x1
56 +#define CHIP_REV_PKG_SHIFT 16
57 +#define CHIP_REV_VER_MASK 0xf
58 +#define CHIP_REV_VER_SHIFT 8
59 +#define CHIP_REV_ECO_MASK 0xf
61 +#define MT7620_CPLL_SW_CONFIG_SHIFT 31
62 +#define MT7620_CPLL_SW_CONFIG_MASK 0x1
63 +#define MT7620_CPLL_CPU_CLK_SHIFT 24
64 +#define MT7620_CPLL_CPU_CLK_MASK 0x1
66 +#define MT7620_GPIO_MODE_I2C BIT(0)
67 +#define MT7620_GPIO_MODE_UART0_SHIFT 2
68 +#define MT7620_GPIO_MODE_UART0_MASK 0x7
69 +#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
70 +#define MT7620_GPIO_MODE_UARTF 0x0
71 +#define MT7620_GPIO_MODE_PCM_UARTF 0x1
72 +#define MT7620_GPIO_MODE_PCM_I2S 0x2
73 +#define MT7620_GPIO_MODE_I2S_UARTF 0x3
74 +#define MT7620_GPIO_MODE_PCM_GPIO 0x4
75 +#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
76 +#define MT7620_GPIO_MODE_GPIO_I2S 0x6
77 +#define MT7620_GPIO_MODE_GPIO 0x7
78 +#define MT7620_GPIO_MODE_UART1 BIT(5)
79 +#define MT7620_GPIO_MODE_MDIO BIT(8)
80 +#define MT7620_GPIO_MODE_RGMII1 BIT(9)
81 +#define MT7620_GPIO_MODE_RGMII2 BIT(10)
82 +#define MT7620_GPIO_MODE_SPI BIT(11)
83 +#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
84 +#define MT7620_GPIO_MODE_WLED BIT(13)
85 +#define MT7620_GPIO_MODE_JTAG BIT(15)
86 +#define MT7620_GPIO_MODE_EPHY BIT(15)
87 +#define MT7620_GPIO_MODE_WDT BIT(22)
90 --- a/arch/mips/ralink/Kconfig
91 +++ b/arch/mips/ralink/Kconfig
92 @@ -20,6 +20,9 @@ choice
93 select USB_ARCH_HAS_OHCI
94 select USB_ARCH_HAS_EHCI
102 --- a/arch/mips/ralink/Makefile
103 +++ b/arch/mips/ralink/Makefile
104 @@ -11,6 +11,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
105 obj-$(CONFIG_SOC_RT288X) += rt288x.o
106 obj-$(CONFIG_SOC_RT305X) += rt305x.o
107 obj-$(CONFIG_SOC_RT3883) += rt3883.o
108 +obj-$(CONFIG_SOC_MT7620) += mt7620.o
110 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
112 --- a/arch/mips/ralink/Platform
113 +++ b/arch/mips/ralink/Platform
114 @@ -18,3 +18,8 @@ load-$(CONFIG_SOC_RT305X) += 0xffffffff8
117 load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
122 +load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
124 +++ b/arch/mips/ralink/mt7620.c
127 + * This program is free software; you can redistribute it and/or modify it
128 + * under the terms of the GNU General Public License version 2 as published
129 + * by the Free Software Foundation.
131 + * Parts of this file are based on Ralink's 2.6.21 BSP
133 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
134 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
135 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
138 +#include <linux/kernel.h>
139 +#include <linux/init.h>
140 +#include <linux/module.h>
142 +#include <asm/mipsregs.h>
143 +#include <asm/mach-ralink/ralink_regs.h>
144 +#include <asm/mach-ralink/mt7620.h>
149 +struct ralink_pinmux_grp mode_mux[] = {
152 + .mask = MT7620_GPIO_MODE_I2C,
157 + .mask = MT7620_GPIO_MODE_SPI,
161 + .name = "uartlite",
162 + .mask = MT7620_GPIO_MODE_UART1,
167 + .mask = MT7620_GPIO_MODE_WDT,
172 + .mask = MT7620_GPIO_MODE_MDIO,
177 + .mask = MT7620_GPIO_MODE_RGMII1,
181 + .name = "spi refclk",
182 + .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
187 + .mask = MT7620_GPIO_MODE_JTAG,
191 + /* shared lines with jtag */
193 + .mask = MT7620_GPIO_MODE_EPHY,
198 + .mask = MT7620_GPIO_MODE_JTAG,
203 + .mask = MT7620_GPIO_MODE_RGMII2,
208 + .mask = MT7620_GPIO_MODE_WLED,
215 +struct ralink_pinmux_grp uart_mux[] = {
218 + .mask = MT7620_GPIO_MODE_UARTF,
222 + .name = "pcm uartf",
223 + .mask = MT7620_GPIO_MODE_PCM_UARTF,
228 + .mask = MT7620_GPIO_MODE_PCM_I2S,
232 + .name = "i2s uartf",
233 + .mask = MT7620_GPIO_MODE_I2S_UARTF,
237 + .name = "pcm gpio",
238 + .mask = MT7620_GPIO_MODE_PCM_GPIO,
242 + .name = "gpio uartf",
243 + .mask = MT7620_GPIO_MODE_GPIO_UARTF,
247 + .name = "gpio i2s",
248 + .mask = MT7620_GPIO_MODE_GPIO_I2S,
253 + .mask = MT7620_GPIO_MODE_GPIO,
257 +void rt305x_wdt_reset(void)
261 + t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
262 + t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
263 + RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
264 + rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
267 +struct ralink_pinmux rt_pinmux = {
270 + .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
271 +// .wdt_reset = rt305x_wdt_reset,
274 +void __init ralink_clk_init(void)
276 + unsigned long cpu_rate, sys_rate;
277 + u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
278 + u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
280 + c0 = (c0 >> MT7620_CPLL_SW_CONFIG_SHIFT) &
281 + MT7620_CPLL_SW_CONFIG_MASK;
282 + c1 = (c1 >> MT7620_CPLL_CPU_CLK_SHIFT) &
283 + MT7620_CPLL_CPU_CLK_MASK;
285 + cpu_rate = 480000000;
288 + cpu_rate = 600000000;
290 + /* TODO calculate custom clock from pll settings */
294 + /* FIXME SDR - 4, DDR - 3 */
295 + sys_rate = cpu_rate / 4;
297 + ralink_clk_add("cpu", cpu_rate);
298 + ralink_clk_add("10000100.timer", 40000000);
299 + ralink_clk_add("10000500.uart", 40000000);
300 + ralink_clk_add("10000c00.uartlite", 40000000);
303 +void __init ralink_of_remap(void)
305 + rt_sysc_membase = plat_of_remap_node("ralink,mt7620-sysc");
306 + rt_memc_membase = plat_of_remap_node("ralink,mt7620-memc");
308 + if (!rt_sysc_membase || !rt_memc_membase)
309 + panic("Failed to remap core resources");
312 +void prom_soc_init(struct ralink_soc_info *soc_info)
314 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
315 + unsigned char *name = NULL;
320 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
321 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
323 + if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
325 + soc_info->compatible = "ralink,mt7620n-soc";
326 + } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
328 + soc_info->compatible = "ralink,mt7620a-soc";
330 + printk("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
333 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
335 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
336 + "Ralink %s ver:%u eco:%u",
338 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
339 + (rev & CHIP_REV_ECO_MASK));