1 From 8831277e0167cdcf3dc3ecc5d5a67d4fd9d0ed77 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 21 Mar 2013 17:49:02 +0100
4 Subject: [PATCH 111/121] MIPS: ralink: adds support for MT7620 SoC family
6 Add support code for mt7620 SOC.
8 The code detects the SoC and registers the clk / pinmux settings.
10 Signed-off-by: John Crispin <blogic@openwrt.org>
12 arch/mips/include/asm/mach-ralink/mt7620.h | 66 +++++++++
13 arch/mips/ralink/Kconfig | 3 +
14 arch/mips/ralink/Makefile | 1 +
15 arch/mips/ralink/Platform | 5 +
16 arch/mips/ralink/mt7620.c | 215 ++++++++++++++++++++++++++++
17 5 files changed, 290 insertions(+)
18 create mode 100644 arch/mips/include/asm/mach-ralink/mt7620.h
19 create mode 100644 arch/mips/ralink/mt7620.c
21 diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
23 index 0000000..3d51235
25 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
28 + * This program is free software; you can redistribute it and/or modify it
29 + * under the terms of the GNU General Public License version 2 as published
30 + * by the Free Software Foundation.
32 + * Parts of this file are based on Ralink's 2.6.21 BSP
34 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
35 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
36 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
39 +#ifndef _MT7620_REGS_H_
40 +#define _MT7620_REGS_H_
42 +#define MT7620_SYSC_BASE 0x10000000
44 +#define SYSC_REG_CHIP_NAME0 0x00
45 +#define SYSC_REG_CHIP_NAME1 0x04
46 +#define SYSC_REG_CHIP_REV 0x0c
47 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
48 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
49 +#define SYSC_REG_CPLL_CONFIG0 0x54
50 +#define SYSC_REG_CPLL_CONFIG1 0x58
52 +#define MT7620N_CHIP_NAME0 0x33365452
53 +#define MT7620N_CHIP_NAME1 0x20203235
55 +#define MT7620A_CHIP_NAME0 0x3637544d
56 +#define MT7620A_CHIP_NAME1 0x20203032
58 +#define CHIP_REV_PKG_MASK 0x1
59 +#define CHIP_REV_PKG_SHIFT 16
60 +#define CHIP_REV_VER_MASK 0xf
61 +#define CHIP_REV_VER_SHIFT 8
62 +#define CHIP_REV_ECO_MASK 0xf
64 +#define MT7620_CPLL_SW_CONFIG_SHIFT 31
65 +#define MT7620_CPLL_SW_CONFIG_MASK 0x1
66 +#define MT7620_CPLL_CPU_CLK_SHIFT 24
67 +#define MT7620_CPLL_CPU_CLK_MASK 0x1
69 +#define MT7620_GPIO_MODE_I2C BIT(0)
70 +#define MT7620_GPIO_MODE_UART0_SHIFT 2
71 +#define MT7620_GPIO_MODE_UART0_MASK 0x7
72 +#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
73 +#define MT7620_GPIO_MODE_UARTF 0x0
74 +#define MT7620_GPIO_MODE_PCM_UARTF 0x1
75 +#define MT7620_GPIO_MODE_PCM_I2S 0x2
76 +#define MT7620_GPIO_MODE_I2S_UARTF 0x3
77 +#define MT7620_GPIO_MODE_PCM_GPIO 0x4
78 +#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
79 +#define MT7620_GPIO_MODE_GPIO_I2S 0x6
80 +#define MT7620_GPIO_MODE_GPIO 0x7
81 +#define MT7620_GPIO_MODE_UART1 BIT(5)
82 +#define MT7620_GPIO_MODE_MDIO BIT(8)
83 +#define MT7620_GPIO_MODE_RGMII1 BIT(9)
84 +#define MT7620_GPIO_MODE_RGMII2 BIT(10)
85 +#define MT7620_GPIO_MODE_SPI BIT(11)
86 +#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
87 +#define MT7620_GPIO_MODE_WLED BIT(13)
88 +#define MT7620_GPIO_MODE_JTAG BIT(15)
89 +#define MT7620_GPIO_MODE_EPHY BIT(15)
90 +#define MT7620_GPIO_MODE_WDT BIT(22)
93 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
94 index 2ef69ee..493411f 100644
95 --- a/arch/mips/ralink/Kconfig
96 +++ b/arch/mips/ralink/Kconfig
97 @@ -20,6 +20,9 @@ choice
98 select USB_ARCH_HAS_OHCI
99 select USB_ARCH_HAS_EHCI
107 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
108 index 87f6ca9..341b4de 100644
109 --- a/arch/mips/ralink/Makefile
110 +++ b/arch/mips/ralink/Makefile
111 @@ -11,6 +11,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
112 obj-$(CONFIG_SOC_RT288X) += rt288x.o
113 obj-$(CONFIG_SOC_RT305X) += rt305x.o
114 obj-$(CONFIG_SOC_RT3883) += rt3883.o
115 +obj-$(CONFIG_SOC_MT7620) += mt7620.o
117 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
119 diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
120 index f67c08d..b2cbf16 100644
121 --- a/arch/mips/ralink/Platform
122 +++ b/arch/mips/ralink/Platform
123 @@ -18,3 +18,8 @@ load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
126 load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
131 +load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
132 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
134 index 0000000..9d0dc8b
136 +++ b/arch/mips/ralink/mt7620.c
139 + * This program is free software; you can redistribute it and/or modify it
140 + * under the terms of the GNU General Public License version 2 as published
141 + * by the Free Software Foundation.
143 + * Parts of this file are based on Ralink's 2.6.21 BSP
145 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
146 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
147 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
150 +#include <linux/kernel.h>
151 +#include <linux/init.h>
152 +#include <linux/module.h>
154 +#include <asm/mipsregs.h>
155 +#include <asm/mach-ralink/ralink_regs.h>
156 +#include <asm/mach-ralink/mt7620.h>
161 +struct ralink_pinmux_grp mode_mux[] = {
164 + .mask = MT7620_GPIO_MODE_I2C,
169 + .mask = MT7620_GPIO_MODE_SPI,
173 + .name = "uartlite",
174 + .mask = MT7620_GPIO_MODE_UART1,
179 + .mask = MT7620_GPIO_MODE_WDT,
184 + .mask = MT7620_GPIO_MODE_MDIO,
189 + .mask = MT7620_GPIO_MODE_RGMII1,
193 + .name = "spi refclk",
194 + .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
199 + .mask = MT7620_GPIO_MODE_JTAG,
203 + /* shared lines with jtag */
205 + .mask = MT7620_GPIO_MODE_EPHY,
210 + .mask = MT7620_GPIO_MODE_JTAG,
215 + .mask = MT7620_GPIO_MODE_RGMII2,
220 + .mask = MT7620_GPIO_MODE_WLED,
227 +struct ralink_pinmux_grp uart_mux[] = {
230 + .mask = MT7620_GPIO_MODE_UARTF,
234 + .name = "pcm uartf",
235 + .mask = MT7620_GPIO_MODE_PCM_UARTF,
240 + .mask = MT7620_GPIO_MODE_PCM_I2S,
244 + .name = "i2s uartf",
245 + .mask = MT7620_GPIO_MODE_I2S_UARTF,
249 + .name = "pcm gpio",
250 + .mask = MT7620_GPIO_MODE_PCM_GPIO,
254 + .name = "gpio uartf",
255 + .mask = MT7620_GPIO_MODE_GPIO_UARTF,
259 + .name = "gpio i2s",
260 + .mask = MT7620_GPIO_MODE_GPIO_I2S,
265 + .mask = MT7620_GPIO_MODE_GPIO,
269 +void rt305x_wdt_reset(void)
273 + t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
274 + t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
275 + RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
276 + rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
279 +struct ralink_pinmux rt_pinmux = {
282 + .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
283 +// .wdt_reset = rt305x_wdt_reset,
286 +void __init ralink_clk_init(void)
288 + unsigned long cpu_rate, sys_rate;
289 + u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
290 + u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
292 + c0 = (c0 >> MT7620_CPLL_SW_CONFIG_SHIFT) &
293 + MT7620_CPLL_SW_CONFIG_MASK;
294 + c1 = (c1 >> MT7620_CPLL_CPU_CLK_SHIFT) &
295 + MT7620_CPLL_CPU_CLK_MASK;
297 + cpu_rate = 480000000;
300 + cpu_rate = 600000000;
302 + /* TODO calculate custom clock from pll settings */
306 + /* FIXME SDR - 4, DDR - 3 */
307 + sys_rate = cpu_rate / 4;
309 + ralink_clk_add("cpu", cpu_rate);
310 + ralink_clk_add("10000100.timer", 40000000);
311 + ralink_clk_add("10000500.uart", 40000000);
312 + ralink_clk_add("10000c00.uartlite", 40000000);
315 +void __init ralink_of_remap(void)
317 + rt_sysc_membase = plat_of_remap_node("ralink,mt7620-sysc");
318 + rt_memc_membase = plat_of_remap_node("ralink,mt7620-memc");
320 + if (!rt_sysc_membase || !rt_memc_membase)
321 + panic("Failed to remap core resources");
324 +void prom_soc_init(struct ralink_soc_info *soc_info)
326 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
327 + unsigned char *name = NULL;
332 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
333 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
335 + if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
337 + soc_info->compatible = "ralink,mt7620n-soc";
338 + } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
340 + soc_info->compatible = "ralink,mt7620a-soc";
342 + printk("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
345 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
347 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
348 + "Ralink %s ver:%u eco:%u",
350 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
351 + (rev & CHIP_REV_ECO_MASK));