1 From 9c83b58b49f88a48565fad6acea921a0ae222856 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 21 Mar 2013 17:50:05 +0100
4 Subject: [PATCH 112/121] MIPS: add MT7620 dts files
6 Adds the dtsi file for MT7620 SoC. This is the latest and greatest SoC shipped
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/ralink/Kconfig | 4 +
12 arch/mips/ralink/dts/Makefile | 1 +
13 arch/mips/ralink/dts/mt7620.dtsi | 138 ++++++++++++++++++++++++++++++++++
14 arch/mips/ralink/dts/mt7620_eval.dts | 22 ++++++
15 4 files changed, 165 insertions(+)
16 create mode 100644 arch/mips/ralink/dts/mt7620.dtsi
17 create mode 100644 arch/mips/ralink/dts/mt7620_eval.dts
19 --- a/arch/mips/ralink/Kconfig
20 +++ b/arch/mips/ralink/Kconfig
21 @@ -46,6 +46,10 @@ choice
22 bool "RT3883 eval kit"
25 + config DTB_MT7620_EVAL
26 + bool "MT7620 eval kit"
27 + depends on SOC_MT7620
32 --- a/arch/mips/ralink/dts/Makefile
33 +++ b/arch/mips/ralink/dts/Makefile
35 obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
36 obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
37 obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
38 +obj-$(CONFIG_DTB_MT7620_EVAL) := mt7620_eval.dtb.o
40 +++ b/arch/mips/ralink/dts/mt7620.dtsi
43 + #address-cells = <1>;
45 + compatible = "ralink,mtk7620n-soc", "ralink,mt7620-soc";
49 + compatible = "mips,mips24KEc";
54 + bootargs = "console=ttyS0,57600 init=/init";
57 + cpuintc: cpuintc@0 {
58 + #address-cells = <0>;
59 + #interrupt-cells = <1>;
60 + interrupt-controller;
61 + compatible = "mti,cpu-interrupt-controller";
65 + compatible = "palmbus";
66 + reg = <0x10000000 0x200000>;
67 + ranges = <0x0 0x10000000 0x1FFFFF>;
69 + #address-cells = <1>;
73 + compatible = "ralink,mt7620-sysc", "ralink,mt7620n-sysc";
78 + compatible = "ralink,mt7620-timer", "ralink,rt2880-timer";
81 + interrupt-parent = <&intc>;
84 + status = "disabled";
88 + compatible = "ralink,mt7620-wdt", "ralink,rt2880-wdt";
93 + compatible = "ralink,mt7620-intc", "ralink,rt2880-intc";
94 + reg = <0x200 0x100>;
96 + interrupt-controller;
97 + #interrupt-cells = <1>;
99 + interrupt-parent = <&cpuintc>;
104 + compatible = "ralink,mt7620-memc", "ralink,rt3050-memc";
105 + reg = <0x300 0x100>;
109 + compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
110 + reg = <0x600 0x34>;
115 + ralink,num-gpios = <24>;
116 + ralink,register-map = [ 00 04 08 0c
122 + compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
123 + reg = <0x638 0x24>;
128 + ralink,num-gpios = <16>;
129 + ralink,register-map = [ 00 04 08 0c
135 + compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
136 + reg = <0x660 0x24>;
141 + ralink,num-gpios = <32>;
142 + ralink,register-map = [ 00 04 08 0c
148 + compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
149 + reg = <0x688 0x24>;
154 + ralink,num-gpios = <1>;
155 + ralink,register-map = [ 00 04 08 0c
161 + compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
162 + reg = <0xb00 0x100>;
163 + #address-cells = <1>;
166 + status = "disabled";
170 + compatible = "ralink,mt7620-uart", "ralink,rt2880-uart", "ns16550a";
171 + reg = <0xc00 0x100>;
173 + interrupt-parent = <&intc>;
181 +++ b/arch/mips/ralink/dts/mt7620_eval.dts
185 +/include/ "mt7620.dtsi"
188 + #address-cells = <1>;
190 + compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
191 + model = "Ralink MT7620 evaluation board";
194 + reg = <0x0 0x4000000>;
199 + ralink,pinmmux = "uartlite", "spi";
200 + ralink,uartmux = "gpio";
201 + ralink,wdtmux = <0>;