target/linux/ramips/patches-3.8/0113-MIPS-ralink-adds-support-for-MT7620-SoC-family.patch

   1 From a8d7045a9530d0a9e0c65c0f81852bd57ebde53c Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 17:49:02 +0100
   4 Subject: [PATCH 113/137] MIPS: ralink: adds support for MT7620 SoC family
   5
   6 Add support code for mt7620 SOC.
   7
   8 The code detects the SoC and registers the clk / pinmux settings.
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Acked-by: Gabor Juhos <juhosg@openwrt.org>
  12 Patchwork: http://patchwork.linux-mips.org/patch/5177/
  13 ---
  14  arch/mips/include/asm/mach-ralink/mt7620.h |   76 ++++++++++
  15  arch/mips/ralink/Kconfig                   |    3 +
  16  arch/mips/ralink/Makefile                  |    1 +
  17  arch/mips/ralink/Platform                  |    5 +
  18  arch/mips/ralink/mt7620.c                  |  214 ++++++++++++++++++++++++++++
  19  5 files changed, 299 insertions(+)
  20  create mode 100644 arch/mips/include/asm/mach-ralink/mt7620.h
  21  create mode 100644 arch/mips/ralink/mt7620.c
  22
  23 --- /dev/null
  24 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
  25 @@ -0,0 +1,76 @@
  26 +/*
  27 + * This program is free software; you can redistribute it and/or modify it
  28 + * under the terms of the GNU General Public License version 2 as published
  29 + * by the Free Software Foundation.
  30 + *
  31 + * Parts of this file are based on Ralink's 2.6.21 BSP
  32 + *
  33 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  34 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  35 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  36 + */
  37 +
  38 +#ifndef _MT7620_REGS_H_
  39 +#define _MT7620_REGS_H_
  40 +
  41 +#define MT7620_SYSC_BASE               0x10000000
  42 +
  43 +#define SYSC_REG_CHIP_NAME0            0x00
  44 +#define SYSC_REG_CHIP_NAME1            0x04
  45 +#define SYSC_REG_CHIP_REV              0x0c
  46 +#define SYSC_REG_SYSTEM_CONFIG0                0x10
  47 +#define SYSC_REG_SYSTEM_CONFIG1                0x14
  48 +#define SYSC_REG_CPLL_CONFIG0          0x54
  49 +#define SYSC_REG_CPLL_CONFIG1          0x58
  50 +
  51 +#define MT7620N_CHIP_NAME0             0x33365452
  52 +#define MT7620N_CHIP_NAME1             0x20203235
  53 +
  54 +#define MT7620A_CHIP_NAME0             0x3637544d
  55 +#define MT7620A_CHIP_NAME1             0x20203032
  56 +
  57 +#define CHIP_REV_PKG_MASK              0x1
  58 +#define CHIP_REV_PKG_SHIFT             16
  59 +#define CHIP_REV_VER_MASK              0xf
  60 +#define CHIP_REV_VER_SHIFT             8
  61 +#define CHIP_REV_ECO_MASK              0xf
  62 +
  63 +#define CPLL_SW_CONFIG_SHIFT           31
  64 +#define CPLL_SW_CONFIG_MASK            0x1
  65 +#define CPLL_CPU_CLK_SHIFT             24
  66 +#define CPLL_CPU_CLK_MASK              0x1
  67 +#define CPLL_MULT_RATIO_SHIFT           16
  68 +#define CPLL_MULT_RATIO                 0x7
  69 +#define CPLL_DIV_RATIO_SHIFT            10
  70 +#define CPLL_DIV_RATIO                  0x3
  71 +
  72 +#define SYSCFG0_DRAM_TYPE_MASK         0x3
  73 +#define SYSCFG0_DRAM_TYPE_SHIFT                4
  74 +#define SYSCFG0_DRAM_TYPE_SDRAM                0
  75 +#define SYSCFG0_DRAM_TYPE_DDR1         1
  76 +#define SYSCFG0_DRAM_TYPE_DDR2         2
  77 +
  78 +#define MT7620_GPIO_MODE_I2C           BIT(0)
  79 +#define MT7620_GPIO_MODE_UART0_SHIFT   2
  80 +#define MT7620_GPIO_MODE_UART0_MASK    0x7
  81 +#define MT7620_GPIO_MODE_UART0(x)      ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
  82 +#define MT7620_GPIO_MODE_UARTF         0x0
  83 +#define MT7620_GPIO_MODE_PCM_UARTF     0x1
  84 +#define MT7620_GPIO_MODE_PCM_I2S       0x2
  85 +#define MT7620_GPIO_MODE_I2S_UARTF     0x3
  86 +#define MT7620_GPIO_MODE_PCM_GPIO      0x4
  87 +#define MT7620_GPIO_MODE_GPIO_UARTF    0x5
  88 +#define MT7620_GPIO_MODE_GPIO_I2S      0x6
  89 +#define MT7620_GPIO_MODE_GPIO          0x7
  90 +#define MT7620_GPIO_MODE_UART1         BIT(5)
  91 +#define MT7620_GPIO_MODE_MDIO          BIT(8)
  92 +#define MT7620_GPIO_MODE_RGMII1                BIT(9)
  93 +#define MT7620_GPIO_MODE_RGMII2                BIT(10)
  94 +#define MT7620_GPIO_MODE_SPI           BIT(11)
  95 +#define MT7620_GPIO_MODE_SPI_REF_CLK   BIT(12)
  96 +#define MT7620_GPIO_MODE_WLED          BIT(13)
  97 +#define MT7620_GPIO_MODE_JTAG          BIT(15)
  98 +#define MT7620_GPIO_MODE_EPHY          BIT(15)
  99 +#define MT7620_GPIO_MODE_WDT           BIT(22)
 100 +
 101 +#endif
 102 --- a/arch/mips/ralink/Kconfig
 103 +++ b/arch/mips/ralink/Kconfig
 104 @@ -20,6 +20,9 @@ choice
 105                 select USB_ARCH_HAS_OHCI
 106                 select USB_ARCH_HAS_EHCI
 107
 108 +       config SOC_MT7620
 109 +               bool "MT7620"
 110 +
 111  endchoice
 112
 113  choice
 114 --- a/arch/mips/ralink/Makefile
 115 +++ b/arch/mips/ralink/Makefile
 116 @@ -11,6 +11,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
 117  obj-$(CONFIG_SOC_RT288X) += rt288x.o
 118  obj-$(CONFIG_SOC_RT305X) += rt305x.o
 119  obj-$(CONFIG_SOC_RT3883) += rt3883.o
 120 +obj-$(CONFIG_SOC_MT7620) += mt7620.o
 121
 122  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 123
 124 --- a/arch/mips/ralink/Platform
 125 +++ b/arch/mips/ralink/Platform
 126 @@ -18,3 +18,8 @@ load-$(CONFIG_SOC_RT305X)     += 0xffffffff8
 127  # Ralink RT3883
 128  #
 129  load-$(CONFIG_SOC_RT3883)      += 0xffffffff80000000
 130 +
 131 +#
 132 +# Ralink MT7620
 133 +#
 134 +load-$(CONFIG_SOC_MT7620)      += 0xffffffff80000000
 135 --- /dev/null
 136 +++ b/arch/mips/ralink/mt7620.c
 137 @@ -0,0 +1,214 @@
 138 +/*
 139 + * This program is free software; you can redistribute it and/or modify it
 140 + * under the terms of the GNU General Public License version 2 as published
 141 + * by the Free Software Foundation.
 142 + *
 143 + * Parts of this file are based on Ralink's 2.6.21 BSP
 144 + *
 145 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 146 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 147 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 148 + */
 149 +
 150 +#include <linux/kernel.h>
 151 +#include <linux/init.h>
 152 +#include <linux/module.h>
 153 +
 154 +#include <asm/mipsregs.h>
 155 +#include <asm/mach-ralink/ralink_regs.h>
 156 +#include <asm/mach-ralink/mt7620.h>
 157 +
 158 +#include "common.h"
 159 +
 160 +/* does the board have sdram or ddram */
 161 +static int dram_type;
 162 +
 163 +/* the pll dividers */
 164 +static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
 165 +
 166 +static struct ralink_pinmux_grp mode_mux[] = {
 167 +       {
 168 +               .name = "i2c",
 169 +               .mask = MT7620_GPIO_MODE_I2C,
 170 +               .gpio_first = 1,
 171 +               .gpio_last = 2,
 172 +       }, {
 173 +               .name = "spi",
 174 +               .mask = MT7620_GPIO_MODE_SPI,
 175 +               .gpio_first = 3,
 176 +               .gpio_last = 6,
 177 +       }, {
 178 +               .name = "uartlite",
 179 +               .mask = MT7620_GPIO_MODE_UART1,
 180 +               .gpio_first = 15,
 181 +               .gpio_last = 16,
 182 +       }, {
 183 +               .name = "wdt",
 184 +               .mask = MT7620_GPIO_MODE_WDT,
 185 +               .gpio_first = 17,
 186 +               .gpio_last = 17,
 187 +       }, {
 188 +               .name = "mdio",
 189 +               .mask = MT7620_GPIO_MODE_MDIO,
 190 +               .gpio_first = 22,
 191 +               .gpio_last = 23,
 192 +       }, {
 193 +               .name = "rgmii1",
 194 +               .mask = MT7620_GPIO_MODE_RGMII1,
 195 +               .gpio_first = 24,
 196 +               .gpio_last = 35,
 197 +       }, {
 198 +               .name = "spi refclk",
 199 +               .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
 200 +               .gpio_first = 37,
 201 +               .gpio_last = 39,
 202 +       }, {
 203 +               .name = "jtag",
 204 +               .mask = MT7620_GPIO_MODE_JTAG,
 205 +               .gpio_first = 40,
 206 +               .gpio_last = 44,
 207 +       }, {
 208 +               /* shared lines with jtag */
 209 +               .name = "ephy",
 210 +               .mask = MT7620_GPIO_MODE_EPHY,
 211 +               .gpio_first = 40,
 212 +               .gpio_last = 44,
 213 +       }, {
 214 +               .name = "nand",
 215 +               .mask = MT7620_GPIO_MODE_JTAG,
 216 +               .gpio_first = 45,
 217 +               .gpio_last = 59,
 218 +       }, {
 219 +               .name = "rgmii2",
 220 +               .mask = MT7620_GPIO_MODE_RGMII2,
 221 +               .gpio_first = 60,
 222 +               .gpio_last = 71,
 223 +       }, {
 224 +               .name = "wled",
 225 +               .mask = MT7620_GPIO_MODE_WLED,
 226 +               .gpio_first = 72,
 227 +               .gpio_last = 72,
 228 +       }, {0}
 229 +};
 230 +
 231 +static struct ralink_pinmux_grp uart_mux[] = {
 232 +       {
 233 +               .name = "uartf",
 234 +               .mask = MT7620_GPIO_MODE_UARTF,
 235 +               .gpio_first = 7,
 236 +               .gpio_last = 14,
 237 +       }, {
 238 +               .name = "pcm uartf",
 239 +               .mask = MT7620_GPIO_MODE_PCM_UARTF,
 240 +               .gpio_first = 7,
 241 +               .gpio_last = 14,
 242 +       }, {
 243 +               .name = "pcm i2s",
 244 +               .mask = MT7620_GPIO_MODE_PCM_I2S,
 245 +               .gpio_first = 7,
 246 +               .gpio_last = 14,
 247 +       }, {
 248 +               .name = "i2s uartf",
 249 +               .mask = MT7620_GPIO_MODE_I2S_UARTF,
 250 +               .gpio_first = 7,
 251 +               .gpio_last = 14,
 252 +       }, {
 253 +               .name = "pcm gpio",
 254 +               .mask = MT7620_GPIO_MODE_PCM_GPIO,
 255 +               .gpio_first = 11,
 256 +               .gpio_last = 14,
 257 +       }, {
 258 +               .name = "gpio uartf",
 259 +               .mask = MT7620_GPIO_MODE_GPIO_UARTF,
 260 +               .gpio_first = 7,
 261 +               .gpio_last = 10,
 262 +       }, {
 263 +               .name = "gpio i2s",
 264 +               .mask = MT7620_GPIO_MODE_GPIO_I2S,
 265 +               .gpio_first = 7,
 266 +               .gpio_last = 10,
 267 +       }, {
 268 +               .name = "gpio",
 269 +               .mask = MT7620_GPIO_MODE_GPIO,
 270 +       }, {0}
 271 +};
 272 +
 273 +struct ralink_pinmux rt_gpio_pinmux = {
 274 +       .mode = mode_mux,
 275 +       .uart = uart_mux,
 276 +       .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
 277 +       .uart_mask = MT7620_GPIO_MODE_GPIO,
 278 +};
 279 +
 280 +void __init ralink_clk_init(void)
 281 +{
 282 +       unsigned long cpu_rate, sys_rate;
 283 +       u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
 284 +       u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
 285 +       u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
 286 +       u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
 287 +
 288 +       if (cpu_clk) {
 289 +               cpu_rate = 480000000;
 290 +       } else if (!swconfig) {
 291 +               cpu_rate = 600000000;
 292 +       } else {
 293 +               u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
 294 +               u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
 295 +
 296 +               cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
 297 +       }
 298 +
 299 +       if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
 300 +               sys_rate = cpu_rate / 4;
 301 +       else
 302 +               sys_rate = cpu_rate / 3;
 303 +
 304 +       ralink_clk_add("cpu", cpu_rate);
 305 +       ralink_clk_add("10000100.timer", 40000000);
 306 +       ralink_clk_add("10000500.uart", 40000000);
 307 +       ralink_clk_add("10000c00.uartlite", 40000000);
 308 +}
 309 +
 310 +void __init ralink_of_remap(void)
 311 +{
 312 +       rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
 313 +       rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
 314 +
 315 +       if (!rt_sysc_membase || !rt_memc_membase)
 316 +               panic("Failed to remap core resources");
 317 +}
 318 +
 319 +void prom_soc_init(struct ralink_soc_info *soc_info)
 320 +{
 321 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
 322 +       unsigned char *name = NULL;
 323 +       u32 n0;
 324 +       u32 n1;
 325 +       u32 rev;
 326 +       u32 cfg0;
 327 +
 328 +       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 329 +       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 330 +
 331 +       if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
 332 +               name = "MT7620N";
 333 +               soc_info->compatible = "ralink,mt7620n-soc";
 334 +       } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
 335 +               name = "MT7620A";
 336 +               soc_info->compatible = "ralink,mt7620a-soc";
 337 +       } else {
 338 +               panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 339 +       }
 340 +
 341 +       rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
 342 +
 343 +       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 344 +               "Ralink %s ver:%u eco:%u",
 345 +               name,
 346 +               (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
 347 +               (rev & CHIP_REV_ECO_MASK));
 348 +
 349 +       cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
 350 +       dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
 351 +}