1 From f01830fcc57273bd9ec5f6733ab3d28adeb71955 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 21 Mar 2013 17:34:08 +0100
4 Subject: [PATCH 119/121] PCI: MIPS: adds rt3883 pci support
6 Add support for the pcie found on the rt3883 SoC.
8 Signed-off-by: John Crispin <blogic@openwrt.org>
10 arch/mips/pci/Makefile | 1 +
11 arch/mips/pci/pci-rt3883.c | 487 ++++++++++++++++++++++++++++++++++++++++++++
12 arch/mips/ralink/Kconfig | 1 +
13 3 files changed, 489 insertions(+)
14 create mode 100644 arch/mips/pci/pci-rt3883.c
16 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
17 index 77974ba..3cbfd9b 100644
18 --- a/arch/mips/pci/Makefile
19 +++ b/arch/mips/pci/Makefile
20 @@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
21 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
22 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
23 obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
24 +obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
25 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
26 obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
27 obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
28 diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
30 index 0000000..8a4c8ce
32 +++ b/arch/mips/pci/pci-rt3883.c
35 + * Ralink RT3883 SoC PCI support
37 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
39 + * Parts of this file are based on Ralink's 2.6.21 BSP
41 + * This program is free software; you can redistribute it and/or modify it
42 + * under the terms of the GNU General Public License version 2 as published
43 + * by the Free Software Foundation.
46 +#include <linux/types.h>
47 +#include <linux/pci.h>
48 +#include <linux/io.h>
49 +#include <linux/init.h>
50 +#include <linux/delay.h>
51 +#include <linux/interrupt.h>
53 +#include <asm/mach-ralink/rt3883.h>
54 +#include <asm/mach-ralink/rt3883_regs.h>
56 +#define RT3883_MEMORY_BASE 0x00000000
57 +#define RT3883_MEMORY_SIZE 0x02000000
59 +#define RT3883_PCI_MEM_BASE 0x20000000
60 +#define RT3883_PCI_MEM_SIZE 0x10000000
61 +#define RT3883_PCI_IO_BASE 0x10160000
62 +#define RT3883_PCI_IO_SIZE 0x00010000
64 +#define RT3883_PCI_REG_PCICFG_ADDR 0x00
65 +#define RT3883_PCI_REG_PCIRAW_ADDR 0x04
66 +#define RT3883_PCI_REG_PCIINT_ADDR 0x08
67 +#define RT3883_PCI_REG_PCIMSK_ADDR 0x0c
68 +#define RT3833_PCI_PCIINT_PCIE BIT(20)
69 +#define RT3833_PCI_PCIINT_PCI1 BIT(19)
70 +#define RT3833_PCI_PCIINT_PCI0 BIT(18)
72 +#define RT3883_PCI_REG_CONFIG_ADDR 0x20
73 +#define RT3883_PCI_REG_CONFIG_DATA 0x24
74 +#define RT3883_PCI_REG_MEMBASE 0x28
75 +#define RT3883_PCI_REG_IOBASE 0x2c
76 +#define RT3883_PCI_REG_ARBCTL 0x80
78 +#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
79 +#define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
80 +#define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
81 +#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
82 +#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
83 +#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
84 +#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
86 +static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev);
87 +static void __iomem *rt3883_pci_base;
88 +static DEFINE_SPINLOCK(rt3883_pci_lock);
90 +static inline u32 rt3883_pci_rr(unsigned reg)
92 + return readl(rt3883_pci_base + reg);
95 +static inline void rt3883_pci_wr(u32 val, unsigned reg)
97 + writel(val, rt3883_pci_base + reg);
100 +static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
101 + unsigned int func, unsigned int where)
103 + return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
107 +static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot,
108 + unsigned func, unsigned reg)
110 + unsigned long flags;
114 + address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
116 + spin_lock_irqsave(&rt3883_pci_lock, flags);
117 + rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
118 + ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
119 + spin_unlock_irqrestore(&rt3883_pci_lock, flags);
124 +static void rt3883_pci_write_u32(unsigned bus, unsigned slot,
125 + unsigned func, unsigned reg, u32 val)
127 + unsigned long flags;
130 + address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
132 + spin_lock_irqsave(&rt3883_pci_lock, flags);
133 + rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
134 + rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA);
135 + spin_unlock_irqrestore(&rt3883_pci_lock, flags);
138 +static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
142 + pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) &
143 + rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
146 + spurious_interrupt();
150 + if (pending & RT3833_PCI_PCIINT_PCI0)
151 + generic_handle_irq(RT3883_PCI_IRQ_PCI0);
153 + if (pending & RT3833_PCI_PCIINT_PCI1)
154 + generic_handle_irq(RT3883_PCI_IRQ_PCI1);
156 + if (pending & RT3833_PCI_PCIINT_PCIE)
157 + generic_handle_irq(RT3883_PCI_IRQ_PCIE);
160 +static void rt3883_pci_irq_unmask(struct irq_data *d)
167 + case RT3883_PCI_IRQ_PCI0:
168 + mask = RT3833_PCI_PCIINT_PCI0;
170 + case RT3883_PCI_IRQ_PCI1:
171 + mask = RT3833_PCI_PCIINT_PCI1;
173 + case RT3883_PCI_IRQ_PCIE:
174 + mask = RT3833_PCI_PCIINT_PCIE;
180 + t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
181 + rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR);
183 + rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
186 +static void rt3883_pci_irq_mask(struct irq_data *d)
193 + case RT3883_PCI_IRQ_PCI0:
194 + mask = RT3833_PCI_PCIINT_PCI0;
196 + case RT3883_PCI_IRQ_PCI1:
197 + mask = RT3833_PCI_PCIINT_PCI1;
199 + case RT3883_PCI_IRQ_PCIE:
200 + mask = RT3833_PCI_PCIINT_PCIE;
206 + t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
207 + rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR);
209 + rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
212 +static struct irq_chip rt3883_pci_irq_chip = {
213 + .name = "RT3883 PCI",
214 + .irq_mask = rt3883_pci_irq_mask,
215 + .irq_unmask = rt3883_pci_irq_unmask,
216 + .irq_mask_ack = rt3883_pci_irq_mask,
219 +static void __init rt3883_pci_irq_init(void)
223 + /* disable all interrupts */
224 + rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR);
226 + for (i = RT3883_PCI_IRQ_BASE;
227 + i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) {
228 + irq_set_chip_and_handler(i, &rt3883_pci_irq_chip,
232 + irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler);
235 +static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
236 + int where, int size, u32 *val)
238 + unsigned long flags;
242 + address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
243 + PCI_FUNC(devfn), where);
245 + spin_lock_irqsave(&rt3883_pci_lock, flags);
246 + rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
247 + data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
248 + spin_unlock_irqrestore(&rt3883_pci_lock, flags);
252 + *val = (data >> ((where & 3) << 3)) & 0xff;
255 + *val = (data >> ((where & 3) << 3)) & 0xffff;
262 + return PCIBIOS_SUCCESSFUL;
265 +static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
266 + int where, int size, u32 val)
268 + unsigned long flags;
272 + address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
273 + PCI_FUNC(devfn), where);
275 + spin_lock_irqsave(&rt3883_pci_lock, flags);
276 + rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
277 + data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
281 + data = (data & ~(0xff << ((where & 3) << 3))) |
282 + (val << ((where & 3) << 3));
285 + data = (data & ~(0xffff << ((where & 3) << 3))) |
286 + (val << ((where & 3) << 3));
293 + rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA);
294 + spin_unlock_irqrestore(&rt3883_pci_lock, flags);
296 + return PCIBIOS_SUCCESSFUL;
299 +static struct pci_ops rt3883_pci_ops = {
300 + .read = rt3883_pci_config_read,
301 + .write = rt3883_pci_config_write,
304 +static struct resource rt3883_pci_mem_resource = {
305 + .name = "PCI MEM space",
306 + .start = RT3883_PCI_MEM_BASE,
307 + .end = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1,
308 + .flags = IORESOURCE_MEM,
311 +static struct resource rt3883_pci_io_resource = {
312 + .name = "PCI IO space",
313 + .start = RT3883_PCI_IO_BASE,
314 + .end = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1,
315 + .flags = IORESOURCE_IO,
318 +static struct pci_controller rt3883_pci_controller = {
319 + .pci_ops = &rt3883_pci_ops,
320 + .mem_resource = &rt3883_pci_mem_resource,
321 + .io_resource = &rt3883_pci_io_resource,
324 +static void rt3883_pci_preinit(unsigned mode)
330 + if (mode & RT3883_PCI_MODE_PCIE) {
333 + val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
336 + rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1);
338 + val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
340 + rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
342 + val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
344 + rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
346 + val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
348 + rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
350 + val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
352 + rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
357 + syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
358 + syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE |
359 + RT3883_SYSCFG1_PCI_HOST_MODE);
361 + rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
362 + rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE);
364 + clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
365 + clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN |
366 + RT3883_CLKCFG1_PCIE_CLK_EN);
368 + if (mode & RT3883_PCI_MODE_PCI) {
369 + syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE;
370 + clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
371 + rstctrl &= ~RT3883_RSTCTRL_PCI;
373 + if (mode & RT3883_PCI_MODE_PCIE) {
374 + syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE |
375 + RT3883_SYSCFG1_PCIE_RC_MODE;
376 + clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
377 + rstctrl &= ~RT3883_RSTCTRL_PCIE;
380 + rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1);
381 + rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL);
382 + rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
387 +static int rt3883_pcie_ready(void)
393 + status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1));
394 + if (status & BIT(0))
397 + /* TODO: reset PCIe and turn off PCIe clock */
402 +void __init rt3883_pci_init(unsigned mode)
407 + rt3883_pci_preinit(mode);
409 + rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE);
410 + if (rt3883_pci_base == NULL) {
411 + pr_err("failed to ioremap PCI registers\n");
415 + rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR);
416 + if (mode & RT3883_PCI_MODE_PCI)
417 + rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR);
421 + if (mode & RT3883_PCI_MODE_PCIE) {
422 + err = rt3883_pcie_ready();
427 + if (mode & RT3883_PCI_MODE_PCI)
428 + rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL);
430 + rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE);
431 + rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE);
434 + rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0));
435 + rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0));
436 + rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0));
437 + rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0));
438 + rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0));
441 + rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1));
442 + rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1));
443 + rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1));
444 + rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1));
445 + rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1));
447 + rt3883_pci_irq_init();
450 + val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND);
452 + rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val);
455 + val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND);
457 + rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val);
459 + ioport_resource.start = rt3883_pci_io_resource.start;
460 + ioport_resource.end = rt3883_pci_io_resource.end;
462 + register_pci_controller(&rt3883_pci_controller);
465 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
469 + switch (dev->bus->number) {
471 + switch (PCI_SLOT(dev->devfn)) {
473 + rt3883_pci_wr(0x03ff0001,
474 + RT3883_PCI_REG_BAR0SETUP_ADDR(0));
475 + rt3883_pci_wr(0x03ff0001,
476 + RT3883_PCI_REG_BAR0SETUP_ADDR(1));
478 + rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0,
479 + RT3883_MEMORY_BASE);
480 + rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0);
482 + irq = RT3883_CPU_IRQ_PCI;
485 + rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE,
489 + irq = RT3883_PCI_IRQ_PCI0;
492 + irq = RT3883_PCI_IRQ_PCI1;
498 + irq = RT3883_PCI_IRQ_PCIE;
502 + dev_err(&dev->dev, "no IRQ specified\n");
509 +void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev))
511 + rt3883_pci_plat_dev_init = f;
514 +int pcibios_plat_dev_init(struct pci_dev *dev)
516 + if (rt3883_pci_plat_dev_init)
517 + return rt3883_pci_plat_dev_init(dev);
521 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
522 index a3eec2a..2b7b70a 100644
523 --- a/arch/mips/ralink/Kconfig
524 +++ b/arch/mips/ralink/Kconfig
525 @@ -20,6 +20,7 @@ choice
527 select USB_ARCH_HAS_OHCI
528 select USB_ARCH_HAS_EHCI