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[openwrt/staging/chunkeey.git] / target / linux / ramips / patches-3.8 / 0120-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
1 From 1c31c288bc1e853e3226ba593a13a0492b39c9e8 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 15 Mar 2013 19:07:05 +0100
4 Subject: [PATCH 120/121] NET: MIPS: add ralink SoC ethernet driver
5
6 Add support for Ralink FE and ESW.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ramips/Kconfig | 18 +
15 drivers/net/ethernet/ramips/Makefile | 9 +
16 drivers/net/ethernet/ramips/ramips_debugfs.c | 127 ++
17 drivers/net/ethernet/ramips/ramips_esw.c | 1220 +++++++++++++++++++
18 drivers/net/ethernet/ramips/ramips_eth.h | 375 ++++++
19 drivers/net/ethernet/ramips/ramips_main.c | 1285 ++++++++++++++++++++
20 10 files changed, 3064 insertions(+)
21 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
22 create mode 100644 drivers/net/ethernet/ramips/Kconfig
23 create mode 100644 drivers/net/ethernet/ramips/Makefile
24 create mode 100644 drivers/net/ethernet/ramips/ramips_debugfs.c
25 create mode 100644 drivers/net/ethernet/ramips/ramips_esw.c
26 create mode 100644 drivers/net/ethernet/ramips/ramips_eth.h
27 create mode 100644 drivers/net/ethernet/ramips/ramips_main.c
28
29 Index: linux-3.8.3/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
30 ===================================================================
31 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
32 +++ linux-3.8.3/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h 2013-04-02 11:45:25.221274467 +0200
33 @@ -0,0 +1,27 @@
34 +/*
35 + * Ralink RT305x SoC platform device registration
36 + *
37 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
38 + *
39 + * This program is free software; you can redistribute it and/or modify it
40 + * under the terms of the GNU General Public License version 2 as published
41 + * by the Free Software Foundation.
42 + */
43 +
44 +#ifndef _RT305X_ESW_PLATFORM_H
45 +#define _RT305X_ESW_PLATFORM_H
46 +
47 +enum {
48 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
49 + RT305X_ESW_VLAN_CONFIG_LLLLW,
50 + RT305X_ESW_VLAN_CONFIG_WLLLL,
51 +};
52 +
53 +struct rt305x_esw_platform_data
54 +{
55 + u8 vlan_config;
56 + u32 reg_initval_fct2;
57 + u32 reg_initval_fpa2;
58 +};
59 +
60 +#endif /* _RT305X_ESW_PLATFORM_H */
61 Index: linux-3.8.3/arch/mips/ralink/rt305x.c
62 ===================================================================
63 --- linux-3.8.3.orig/arch/mips/ralink/rt305x.c 2013-04-02 11:45:25.025274462 +0200
64 +++ linux-3.8.3/arch/mips/ralink/rt305x.c 2013-04-02 11:45:25.221274467 +0200
65 @@ -182,6 +182,7 @@
66 }
67
68 ralink_clk_add("cpu", cpu_rate);
69 + ralink_clk_add("sys", sys_rate);
70 ralink_clk_add("10000b00.spi", sys_rate);
71 ralink_clk_add("10000100.timer", wdt_rate);
72 ralink_clk_add("10000120.watchdog", wdt_rate);
73 Index: linux-3.8.3/drivers/net/ethernet/Kconfig
74 ===================================================================
75 --- linux-3.8.3.orig/drivers/net/ethernet/Kconfig 2013-03-14 19:27:14.000000000 +0100
76 +++ linux-3.8.3/drivers/net/ethernet/Kconfig 2013-04-02 11:45:25.221274467 +0200
77 @@ -136,6 +136,7 @@
78 source "drivers/net/ethernet/pasemi/Kconfig"
79 source "drivers/net/ethernet/qlogic/Kconfig"
80 source "drivers/net/ethernet/racal/Kconfig"
81 +source "drivers/net/ethernet/ramips/Kconfig"
82 source "drivers/net/ethernet/realtek/Kconfig"
83 source "drivers/net/ethernet/renesas/Kconfig"
84 source "drivers/net/ethernet/rdc/Kconfig"
85 Index: linux-3.8.3/drivers/net/ethernet/Makefile
86 ===================================================================
87 --- linux-3.8.3.orig/drivers/net/ethernet/Makefile 2013-03-14 19:27:14.000000000 +0100
88 +++ linux-3.8.3/drivers/net/ethernet/Makefile 2013-04-02 11:45:25.221274467 +0200
89 @@ -54,6 +54,7 @@
90 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
91 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
92 obj-$(CONFIG_NET_VENDOR_RACAL) += racal/
93 +obj-$(CONFIG_NET_RAMIPS) += ramips/
94 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
95 obj-$(CONFIG_SH_ETH) += renesas/
96 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
97 Index: linux-3.8.3/drivers/net/ethernet/ramips/Kconfig
98 ===================================================================
99 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
100 +++ linux-3.8.3/drivers/net/ethernet/ramips/Kconfig 2013-04-02 11:45:25.221274467 +0200
101 @@ -0,0 +1,18 @@
102 +config NET_RAMIPS
103 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883 ethernet driver"
104 + depends on RALINK
105 + select PHYLIB if (SOC_RT288X || SOC_RT3883)
106 + select SWCONFIG if SOC_RT305X
107 + help
108 + This driver supports the etehrnet mac inside the ralink wisocs
109 +
110 +if NET_RAMIPS
111 +
112 +config NET_RAMIPS_DEBUG
113 + bool "Enable debug messages in the Ralink ethernet driver"
114 +
115 +config NET_RAMIPS_DEBUG_FS
116 + bool "Enable debugfs support for the Ralink ethernet driver"
117 + depends on DEBUG_FS
118 +
119 +endif
120 Index: linux-3.8.3/drivers/net/ethernet/ramips/Makefile
121 ===================================================================
122 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
123 +++ linux-3.8.3/drivers/net/ethernet/ramips/Makefile 2013-04-02 11:45:25.221274467 +0200
124 @@ -0,0 +1,9 @@
125 +#
126 +# Makefile for the Ramips SoCs built-in ethernet macs
127 +#
128 +
129 +ramips-y += ramips_main.o
130 +
131 +ramips-$(CONFIG_NET_RAMIPS_DEBUG_FS) += ramips_debugfs.o
132 +
133 +obj-$(CONFIG_NET_RAMIPS) += ramips.o
134 Index: linux-3.8.3/drivers/net/ethernet/ramips/ramips_debugfs.c
135 ===================================================================
136 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
137 +++ linux-3.8.3/drivers/net/ethernet/ramips/ramips_debugfs.c 2013-04-02 11:45:25.225274468 +0200
138 @@ -0,0 +1,127 @@
139 +/*
140 + * Ralink SoC ethernet driver debugfs code
141 + *
142 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
143 + *
144 + * This program is free software; you can redistribute it and/or modify it
145 + * under the terms of the GNU General Public License version 2 as published
146 + * by the Free Software Foundation.
147 + */
148 +
149 +#include <linux/debugfs.h>
150 +#include <linux/module.h>
151 +#include <linux/phy.h>
152 +
153 +#include "ramips_eth.h"
154 +
155 +static struct dentry *raeth_debugfs_root;
156 +
157 +static int raeth_debugfs_generic_open(struct inode *inode, struct file *file)
158 +{
159 + file->private_data = inode->i_private;
160 + return 0;
161 +}
162 +
163 +void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status)
164 +{
165 + re->debug.int_stats.total += !!status;
166 +
167 + re->debug.int_stats.rx_delayed += !!(status & RAMIPS_RX_DLY_INT);
168 + re->debug.int_stats.rx_done0 += !!(status & RAMIPS_RX_DONE_INT0);
169 + re->debug.int_stats.rx_coherent += !!(status & RAMIPS_RX_COHERENT);
170 +
171 + re->debug.int_stats.tx_delayed += !!(status & RAMIPS_TX_DLY_INT);
172 + re->debug.int_stats.tx_done0 += !!(status & RAMIPS_TX_DONE_INT0);
173 + re->debug.int_stats.tx_done1 += !!(status & RAMIPS_TX_DONE_INT1);
174 + re->debug.int_stats.tx_done2 += !!(status & RAMIPS_TX_DONE_INT2);
175 + re->debug.int_stats.tx_done3 += !!(status & RAMIPS_TX_DONE_INT3);
176 + re->debug.int_stats.tx_coherent += !!(status & RAMIPS_TX_COHERENT);
177 +
178 + re->debug.int_stats.pse_fq_empty += !!(status & RAMIPS_PSE_FQ_EMPTY);
179 + re->debug.int_stats.pse_p0_fc += !!(status & RAMIPS_PSE_P0_FC);
180 + re->debug.int_stats.pse_p1_fc += !!(status & RAMIPS_PSE_P1_FC);
181 + re->debug.int_stats.pse_p2_fc += !!(status & RAMIPS_PSE_P2_FC);
182 + re->debug.int_stats.pse_buf_drop += !!(status & RAMIPS_PSE_BUF_DROP);
183 +}
184 +
185 +static ssize_t read_file_int_stats(struct file *file, char __user *user_buf,
186 + size_t count, loff_t *ppos)
187 +{
188 +#define PR_INT_STAT(_label, _field) \
189 + len += snprintf(buf + len, sizeof(buf) - len, \
190 + "%-18s: %10lu\n", _label, re->debug.int_stats._field);
191 +
192 + struct raeth_priv *re = file->private_data;
193 + char buf[512];
194 + unsigned int len = 0;
195 + unsigned long flags;
196 +
197 + spin_lock_irqsave(&re->page_lock, flags);
198 +
199 + PR_INT_STAT("RX Delayed", rx_delayed);
200 + PR_INT_STAT("RX Done 0", rx_done0);
201 + PR_INT_STAT("RX Coherent", rx_coherent);
202 +
203 + PR_INT_STAT("TX Delayed", tx_delayed);
204 + PR_INT_STAT("TX Done 0", tx_done0);
205 + PR_INT_STAT("TX Done 1", tx_done1);
206 + PR_INT_STAT("TX Done 2", tx_done2);
207 + PR_INT_STAT("TX Done 3", tx_done3);
208 + PR_INT_STAT("TX Coherent", tx_coherent);
209 +
210 + PR_INT_STAT("PSE FQ empty", pse_fq_empty);
211 + PR_INT_STAT("CDMA Flow control", pse_p0_fc);
212 + PR_INT_STAT("GDMA1 Flow control", pse_p1_fc);
213 + PR_INT_STAT("GDMA2 Flow control", pse_p2_fc);
214 + PR_INT_STAT("PSE discard", pse_buf_drop);
215 +
216 + len += snprintf(buf + len, sizeof(buf) - len, "\n");
217 + PR_INT_STAT("Total", total);
218 +
219 + spin_unlock_irqrestore(&re->page_lock, flags);
220 +
221 + return simple_read_from_buffer(user_buf, count, ppos, buf, len);
222 +#undef PR_INT_STAT
223 +}
224 +
225 +static const struct file_operations raeth_fops_int_stats = {
226 + .open = raeth_debugfs_generic_open,
227 + .read = read_file_int_stats,
228 + .owner = THIS_MODULE
229 +};
230 +
231 +void raeth_debugfs_exit(struct raeth_priv *re)
232 +{
233 + debugfs_remove_recursive(re->debug.debugfs_dir);
234 +}
235 +
236 +int raeth_debugfs_init(struct raeth_priv *re)
237 +{
238 + re->debug.debugfs_dir = debugfs_create_dir(re->netdev->name,
239 + raeth_debugfs_root);
240 + if (!re->debug.debugfs_dir)
241 + return -ENOMEM;
242 +
243 + debugfs_create_file("int_stats", S_IRUGO, re->debug.debugfs_dir,
244 + re, &raeth_fops_int_stats);
245 +
246 + return 0;
247 +}
248 +
249 +int raeth_debugfs_root_init(void)
250 +{
251 + if (raeth_debugfs_root)
252 + return -EBUSY;
253 +
254 + raeth_debugfs_root = debugfs_create_dir("raeth", NULL);
255 + if (!raeth_debugfs_root)
256 + return -ENOENT;
257 +
258 + return 0;
259 +}
260 +
261 +void raeth_debugfs_root_exit(void)
262 +{
263 + debugfs_remove(raeth_debugfs_root);
264 + raeth_debugfs_root = NULL;
265 +}
266 Index: linux-3.8.3/drivers/net/ethernet/ramips/ramips_esw.c
267 ===================================================================
268 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
269 +++ linux-3.8.3/drivers/net/ethernet/ramips/ramips_esw.c 2013-04-02 11:45:25.225274468 +0200
270 @@ -0,0 +1,1220 @@
271 +#include <linux/ioport.h>
272 +#include <linux/switch.h>
273 +#include <linux/mii.h>
274 +
275 +#include <ralink_regs.h>
276 +#include <rt305x.h>
277 +#include <rt305x_esw_platform.h>
278 +
279 +/*
280 + * HW limitations for this switch:
281 + * - No large frame support (PKT_MAX_LEN at most 1536)
282 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
283 + * though this might be possible using the undocumented PPE.
284 + */
285 +
286 +#define RT305X_ESW_REG_ISR 0x00
287 +#define RT305X_ESW_REG_IMR 0x04
288 +#define RT305X_ESW_REG_FCT0 0x08
289 +#define RT305X_ESW_REG_PFC1 0x14
290 +#define RT305X_ESW_REG_ATS 0x24
291 +#define RT305X_ESW_REG_ATS0 0x28
292 +#define RT305X_ESW_REG_ATS1 0x2c
293 +#define RT305X_ESW_REG_ATS2 0x30
294 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
295 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
296 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
297 +#define RT305X_ESW_REG_POA 0x80
298 +#define RT305X_ESW_REG_FPA 0x84
299 +#define RT305X_ESW_REG_SOCPC 0x8c
300 +#define RT305X_ESW_REG_POC0 0x90
301 +#define RT305X_ESW_REG_POC1 0x94
302 +#define RT305X_ESW_REG_POC2 0x98
303 +#define RT305X_ESW_REG_SGC 0x9c
304 +#define RT305X_ESW_REG_STRT 0xa0
305 +#define RT305X_ESW_REG_PCR0 0xc0
306 +#define RT305X_ESW_REG_PCR1 0xc4
307 +#define RT305X_ESW_REG_FPA2 0xc8
308 +#define RT305X_ESW_REG_FCT2 0xcc
309 +#define RT305X_ESW_REG_SGC2 0xe4
310 +#define RT305X_ESW_REG_P0LED 0xa4
311 +#define RT305X_ESW_REG_P1LED 0xa8
312 +#define RT305X_ESW_REG_P2LED 0xac
313 +#define RT305X_ESW_REG_P3LED 0xb0
314 +#define RT305X_ESW_REG_P4LED 0xb4
315 +#define RT305X_ESW_REG_P0PC 0xe8
316 +#define RT305X_ESW_REG_P1PC 0xec
317 +#define RT305X_ESW_REG_P2PC 0xf0
318 +#define RT305X_ESW_REG_P3PC 0xf4
319 +#define RT305X_ESW_REG_P4PC 0xf8
320 +#define RT305X_ESW_REG_P5PC 0xfc
321 +
322 +#define RT305X_ESW_LED_LINK 0
323 +#define RT305X_ESW_LED_100M 1
324 +#define RT305X_ESW_LED_DUPLEX 2
325 +#define RT305X_ESW_LED_ACTIVITY 3
326 +#define RT305X_ESW_LED_COLLISION 4
327 +#define RT305X_ESW_LED_LINKACT 5
328 +#define RT305X_ESW_LED_DUPLCOLL 6
329 +#define RT305X_ESW_LED_10MACT 7
330 +#define RT305X_ESW_LED_100MACT 8
331 +/* Additional led states not in datasheet: */
332 +#define RT305X_ESW_LED_BLINK 10
333 +#define RT305X_ESW_LED_ON 12
334 +
335 +#define RT305X_ESW_LINK_S 25
336 +#define RT305X_ESW_DUPLEX_S 9
337 +#define RT305X_ESW_SPD_S 0
338 +
339 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
340 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
341 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
342 +
343 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
344 +
345 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
346 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
347 +
348 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
349 +#define RT305X_ESW_PVIDC_PVID_S 12
350 +
351 +#define RT305X_ESW_VLANI_VID_M 0xfff
352 +#define RT305X_ESW_VLANI_VID_S 12
353 +
354 +#define RT305X_ESW_VMSC_MSC_M 0xff
355 +#define RT305X_ESW_VMSC_MSC_S 8
356 +
357 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
358 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
359 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
360 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
361 +
362 +#define RT305X_ESW_POC0_EN_BP_S 0
363 +#define RT305X_ESW_POC0_EN_FC_S 8
364 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
365 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
366 +#define RT305X_ESW_POC0_DIS_PORT_S 23
367 +
368 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
369 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
370 +#define RT305X_ESW_POC2_ENAGING_S 8
371 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
372 +
373 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
374 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
375 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
376 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
377 +
378 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
379 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
380 +#define RT305X_ESW_PFC1_EN_TOS_S 24
381 +
382 +#define RT305X_ESW_VLAN_NONE 0xfff
383 +
384 +#define RT305X_ESW_POA_LINK_MASK 0x1f
385 +#define RT305X_ESW_POA_LINK_SHIFT 25
386 +
387 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
388 +#define RT305X_ESW_PORT0 0
389 +#define RT305X_ESW_PORT1 1
390 +#define RT305X_ESW_PORT2 2
391 +#define RT305X_ESW_PORT3 3
392 +#define RT305X_ESW_PORT4 4
393 +#define RT305X_ESW_PORT5 5
394 +#define RT305X_ESW_PORT6 6
395 +
396 +#define RT305X_ESW_PORTS_NONE 0
397 +
398 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
399 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
400 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
401 +
402 +#define RT305X_ESW_PORTS_INTERNAL \
403 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
404 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
405 + BIT(RT305X_ESW_PORT4))
406 +
407 +#define RT305X_ESW_PORTS_NOCPU \
408 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
409 +
410 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
411 +
412 +#define RT305X_ESW_PORTS_ALL \
413 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
414 +
415 +#define RT305X_ESW_NUM_VLANS 16
416 +#define RT305X_ESW_NUM_VIDS 4096
417 +#define RT305X_ESW_NUM_PORTS 7
418 +#define RT305X_ESW_NUM_LANWAN 6
419 +#define RT305X_ESW_NUM_LEDS 5
420 +
421 +enum {
422 + /* Global attributes. */
423 + RT305X_ESW_ATTR_ENABLE_VLAN,
424 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
425 + /* Port attributes. */
426 + RT305X_ESW_ATTR_PORT_DISABLE,
427 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
428 + RT305X_ESW_ATTR_PORT_UNTAG,
429 + RT305X_ESW_ATTR_PORT_LED,
430 + RT305X_ESW_ATTR_PORT_LAN,
431 + RT305X_ESW_ATTR_PORT_RECV_BAD,
432 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
433 +};
434 +
435 +struct rt305x_esw_port {
436 + bool disable;
437 + bool doubletag;
438 + bool untag;
439 + u8 led;
440 + u16 pvid;
441 +};
442 +
443 +struct rt305x_esw_vlan {
444 + u8 ports;
445 + u16 vid;
446 +};
447 +
448 +struct rt305x_esw {
449 + struct device *dev;
450 + void __iomem *base;
451 + int irq;
452 + const struct rt305x_esw_platform_data *pdata;
453 + /* Protects against concurrent register rmw operations. */
454 + spinlock_t reg_rw_lock;
455 +
456 + unsigned char port_map;
457 + unsigned int reg_initval_fct2;
458 + unsigned int reg_initval_fpa2;
459 +
460 +
461 + struct switch_dev swdev;
462 + bool global_vlan_enable;
463 + bool alt_vlan_disable;
464 + struct rt305x_esw_vlan vlans[RT305X_ESW_NUM_VLANS];
465 + struct rt305x_esw_port ports[RT305X_ESW_NUM_PORTS];
466 +
467 +};
468 +
469 +static inline void
470 +rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
471 +{
472 + __raw_writel(val, esw->base + reg);
473 +}
474 +
475 +static inline u32
476 +rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
477 +{
478 + return __raw_readl(esw->base + reg);
479 +}
480 +
481 +static inline void
482 +rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
483 + unsigned long val)
484 +{
485 + unsigned long t;
486 +
487 + t = __raw_readl(esw->base + reg) & ~mask;
488 + __raw_writel(t | val, esw->base + reg);
489 +}
490 +
491 +static void
492 +rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
493 + unsigned long val)
494 +{
495 + unsigned long flags;
496 +
497 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
498 + rt305x_esw_rmw_raw(esw, reg, mask, val);
499 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
500 +}
501 +
502 +static u32
503 +rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
504 + u32 write_data)
505 +{
506 + unsigned long t_start = jiffies;
507 + int ret = 0;
508 +
509 + while (1) {
510 + if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
511 + RT305X_ESW_PCR1_WT_DONE))
512 + break;
513 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
514 + ret = 1;
515 + goto out;
516 + }
517 + }
518 +
519 + write_data &= 0xffff;
520 + rt305x_esw_wr(esw,
521 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
522 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
523 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
524 + RT305X_ESW_REG_PCR0);
525 +
526 + t_start = jiffies;
527 + while (1) {
528 + if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
529 + RT305X_ESW_PCR1_WT_DONE)
530 + break;
531 +
532 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
533 + ret = 1;
534 + break;
535 + }
536 + }
537 +out:
538 + if (ret)
539 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
540 + return ret;
541 +}
542 +
543 +static unsigned
544 +rt305x_esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
545 +{
546 + unsigned s;
547 + unsigned val;
548 +
549 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
550 + val = rt305x_esw_rr(esw, RT305X_ESW_REG_VLANI(vlan / 2));
551 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
552 +
553 + return val;
554 +}
555 +
556 +static void
557 +rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
558 +{
559 + unsigned s;
560 +
561 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
562 + rt305x_esw_rmw(esw,
563 + RT305X_ESW_REG_VLANI(vlan / 2),
564 + RT305X_ESW_VLANI_VID_M << s,
565 + (vid & RT305X_ESW_VLANI_VID_M) << s);
566 +}
567 +
568 +static unsigned
569 +rt305x_esw_get_pvid(struct rt305x_esw *esw, unsigned port)
570 +{
571 + unsigned s, val;
572 +
573 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
574 + val = rt305x_esw_rr(esw, RT305X_ESW_REG_PVIDC(port / 2));
575 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
576 +}
577 +
578 +static void
579 +rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
580 +{
581 + unsigned s;
582 +
583 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
584 + rt305x_esw_rmw(esw,
585 + RT305X_ESW_REG_PVIDC(port / 2),
586 + RT305X_ESW_PVIDC_PVID_M << s,
587 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
588 +}
589 +
590 +static unsigned
591 +rt305x_esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
592 +{
593 + unsigned s, val;
594 +
595 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
596 + val = rt305x_esw_rr(esw, RT305X_ESW_REG_VMSC(vlan / 4));
597 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
598 +
599 + return val;
600 +}
601 +
602 +static void
603 +rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
604 +{
605 + unsigned s;
606 +
607 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
608 + rt305x_esw_rmw(esw,
609 + RT305X_ESW_REG_VMSC(vlan / 4),
610 + RT305X_ESW_VMSC_MSC_M << s,
611 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
612 +}
613 +
614 +static unsigned
615 +rt305x_esw_get_port_disable(struct rt305x_esw *esw)
616 +{
617 + unsigned reg;
618 + reg = rt305x_esw_rr(esw, RT305X_ESW_REG_POC0);
619 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
620 + RT305X_ESW_POC0_DIS_PORT_M;
621 +}
622 +
623 +static void
624 +rt305x_esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
625 +{
626 + unsigned old_mask;
627 + unsigned enable_mask;
628 + unsigned changed;
629 + int i;
630 +
631 + old_mask = rt305x_esw_get_port_disable(esw);
632 + changed = old_mask ^ disable_mask;
633 + enable_mask = old_mask & disable_mask;
634 +
635 + /* enable before writing to MII */
636 + rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
637 + (RT305X_ESW_POC0_DIS_PORT_M <<
638 + RT305X_ESW_POC0_DIS_PORT_S),
639 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
640 +
641 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
642 + if (!(changed & (1 << i)))
643 + continue;
644 + if (disable_mask & (1 << i)) {
645 + /* disable */
646 + rt305x_mii_write(esw, i, MII_BMCR,
647 + BMCR_PDOWN);
648 + } else {
649 + /* enable */
650 + rt305x_mii_write(esw, i, MII_BMCR,
651 + BMCR_FULLDPLX |
652 + BMCR_ANENABLE |
653 + BMCR_ANRESTART |
654 + BMCR_SPEED100);
655 + }
656 + }
657 +
658 + /* disable after writing to MII */
659 + rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
660 + (RT305X_ESW_POC0_DIS_PORT_M <<
661 + RT305X_ESW_POC0_DIS_PORT_S),
662 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
663 +}
664 +
665 +static int
666 +rt305x_esw_apply_config(struct switch_dev *dev);
667 +
668 +static void
669 +rt305x_esw_hw_init(struct rt305x_esw *esw)
670 +{
671 + int i;
672 + u8 port_disable = 0;
673 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
674 +
675 + /* vodoo from original driver */
676 + rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
677 + rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
678 + /* Port priority 1 for all ports, vlan enabled. */
679 + rt305x_esw_wr(esw, 0x00005555 |
680 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
681 + RT305X_ESW_REG_PFC1);
682 +
683 + /* Enable Back Pressure, and Flow Control */
684 + rt305x_esw_wr(esw,
685 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
686 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
687 + RT305X_ESW_REG_POC0);
688 +
689 + /* Enable Aging, and VLAN TAG removal */
690 + rt305x_esw_wr(esw,
691 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
692 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
693 + RT305X_ESW_REG_POC2);
694 +
695 + if (esw->reg_initval_fct2)
696 + rt305x_esw_wr(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
697 + else
698 + rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
699 +
700 + /*
701 + * 300s aging timer, max packet len 1536, broadcast storm prevention
702 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
703 + * pressure jam, GMII disable was_transmit, back pressure disabled,
704 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
705 + * ports.
706 + */
707 + rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
708 +
709 + /* Setup SoC Port control register */
710 + rt305x_esw_wr(esw,
711 + (RT305X_ESW_SOCPC_CRC_PADDING |
712 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
713 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
714 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
715 + RT305X_ESW_REG_SOCPC);
716 +
717 + if (esw->reg_initval_fpa2)
718 + rt305x_esw_wr(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
719 + else
720 + rt305x_esw_wr(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
721 + rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
722 +
723 + /* Force Link/Activity on ports */
724 + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED);
725 + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED);
726 + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED);
727 + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED);
728 + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED);
729 +
730 + /* Copy disabled port configuration from bootloader setup */
731 + port_disable = rt305x_esw_get_port_disable(esw);
732 + for (i = 0; i < 6; i++)
733 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
734 +
735 + rt305x_mii_write(esw, 0, 31, 0x8000);
736 + for (i = 0; i < 5; i++) {
737 + if (esw->ports[i].disable) {
738 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
739 + } else {
740 + rt305x_mii_write(esw, i, MII_BMCR,
741 + BMCR_FULLDPLX |
742 + BMCR_ANENABLE |
743 + BMCR_SPEED100);
744 + }
745 + /* TX10 waveform coefficient */
746 + rt305x_mii_write(esw, i, 26, 0x1601);
747 + /* TX100/TX10 AD/DA current bias */
748 + rt305x_mii_write(esw, i, 29, 0x7058);
749 + /* TX100 slew rate control */
750 + rt305x_mii_write(esw, i, 30, 0x0018);
751 + }
752 +
753 + /* PHY IOT */
754 + /* select global register */
755 + rt305x_mii_write(esw, 0, 31, 0x0);
756 + /* tune TP_IDL tail and head waveform */
757 + rt305x_mii_write(esw, 0, 22, 0x052f);
758 + /* set TX10 signal amplitude threshold to minimum */
759 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
760 + /* set squelch amplitude to higher threshold */
761 + rt305x_mii_write(esw, 0, 18, 0x40ba);
762 + /* longer TP_IDL tail length */
763 + rt305x_mii_write(esw, 0, 14, 0x65);
764 + /* select local register */
765 + rt305x_mii_write(esw, 0, 31, 0x8000);
766 +
767 + if (esw->port_map)
768 + port_map = esw->port_map;
769 + else
770 + port_map = RT305X_ESW_PMAP_LLLLLL;
771 +
772 + /*
773 + * Unused HW feature, but still nice to be consistent here...
774 + * This is also exported to userspace ('lan' attribute) so it's
775 + * conveniently usable to decide which ports go into the wan vlan by
776 + * default.
777 + */
778 + rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
779 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
780 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
781 +
782 + /* make the switch leds blink */
783 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
784 + esw->ports[i].led = 0x05;
785 +
786 + /* Apply the empty config. */
787 + rt305x_esw_apply_config(&esw->swdev);
788 +}
789 +
790 +static irqreturn_t
791 +rt305x_esw_interrupt(int irq, void *_esw)
792 +{
793 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
794 + u32 status;
795 +
796 + status = rt305x_esw_rr(esw, RT305X_ESW_REG_ISR);
797 + if (status & RT305X_ESW_PORT_ST_CHG) {
798 + u32 link = rt305x_esw_rr(esw, RT305X_ESW_REG_POA);
799 + link >>= RT305X_ESW_POA_LINK_SHIFT;
800 + link &= RT305X_ESW_POA_LINK_MASK;
801 + dev_info(esw->dev, "link changed 0x%02X\n", link);
802 + }
803 + rt305x_esw_wr(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
804 +
805 + return IRQ_HANDLED;
806 +}
807 +
808 +static void
809 +rt305x_esw_request_irq(struct rt305x_esw *esw)
810 +{
811 + /* Only unmask the port change interrupt */
812 + rt305x_esw_wr(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
813 +
814 + /* request the irq handler */
815 + request_irq(esw->irq, rt305x_esw_interrupt, 0, "esw", esw);
816 +}
817 +
818 +static int
819 +rt305x_esw_apply_config(struct switch_dev *dev)
820 +{
821 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
822 + int i;
823 + u8 disable = 0;
824 + u8 doubletag = 0;
825 + u8 en_vlan = 0;
826 + u8 untag = 0;
827 +
828 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
829 + u32 vid, vmsc;
830 + if (esw->global_vlan_enable) {
831 + vid = esw->vlans[i].vid;
832 + vmsc = esw->vlans[i].ports;
833 + } else {
834 + vid = RT305X_ESW_VLAN_NONE;
835 + vmsc = RT305X_ESW_PORTS_NONE;
836 + }
837 + rt305x_esw_set_vlan_id(esw, i, vid);
838 + rt305x_esw_set_vmsc(esw, i, vmsc);
839 + }
840 +
841 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
842 + u32 pvid;
843 + disable |= esw->ports[i].disable << i;
844 + if (esw->global_vlan_enable) {
845 + doubletag |= esw->ports[i].doubletag << i;
846 + en_vlan |= 1 << i;
847 + untag |= esw->ports[i].untag << i;
848 + pvid = esw->ports[i].pvid;
849 + } else {
850 + int x = esw->alt_vlan_disable ? 0 : 1;
851 + doubletag |= x << i;
852 + en_vlan |= x << i;
853 + untag |= x << i;
854 + pvid = 0;
855 + }
856 + rt305x_esw_set_pvid(esw, i, pvid);
857 + if (i < RT305X_ESW_NUM_LEDS)
858 + rt305x_esw_wr(esw, esw->ports[i].led,
859 + RT305X_ESW_REG_P0LED + 4*i);
860 + }
861 +
862 + rt305x_esw_set_port_disable(esw, disable);
863 + rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
864 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
865 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
866 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
867 + rt305x_esw_rmw(esw, RT305X_ESW_REG_PFC1,
868 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
869 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
870 + rt305x_esw_rmw(esw, RT305X_ESW_REG_POC2,
871 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
872 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
873 +
874 + if (!esw->global_vlan_enable) {
875 + /*
876 + * Still need to put all ports into vlan 0 or they'll be
877 + * isolated.
878 + * NOTE: vlan 0 is special, no vlan tag is prepended
879 + */
880 + rt305x_esw_set_vlan_id(esw, 0, 0);
881 + rt305x_esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
882 + }
883 +
884 + return 0;
885 +}
886 +
887 +static int
888 +rt305x_esw_reset_switch(struct switch_dev *dev)
889 +{
890 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
891 + esw->global_vlan_enable = 0;
892 + memset(esw->ports, 0, sizeof(esw->ports));
893 + memset(esw->vlans, 0, sizeof(esw->vlans));
894 + rt305x_esw_hw_init(esw);
895 +
896 + return 0;
897 +}
898 +
899 +static int
900 +rt305x_esw_get_vlan_enable(struct switch_dev *dev,
901 + const struct switch_attr *attr,
902 + struct switch_val *val)
903 +{
904 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
905 +
906 + val->value.i = esw->global_vlan_enable;
907 +
908 + return 0;
909 +}
910 +
911 +static int
912 +rt305x_esw_set_vlan_enable(struct switch_dev *dev,
913 + const struct switch_attr *attr,
914 + struct switch_val *val)
915 +{
916 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
917 +
918 + esw->global_vlan_enable = val->value.i != 0;
919 +
920 + return 0;
921 +}
922 +
923 +static int
924 +rt305x_esw_get_alt_vlan_disable(struct switch_dev *dev,
925 + const struct switch_attr *attr,
926 + struct switch_val *val)
927 +{
928 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
929 +
930 + val->value.i = esw->alt_vlan_disable;
931 +
932 + return 0;
933 +}
934 +
935 +static int
936 +rt305x_esw_set_alt_vlan_disable(struct switch_dev *dev,
937 + const struct switch_attr *attr,
938 + struct switch_val *val)
939 +{
940 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
941 +
942 + esw->alt_vlan_disable = val->value.i != 0;
943 +
944 + return 0;
945 +}
946 +
947 +static int
948 +rt305x_esw_get_port_link(struct switch_dev *dev,
949 + int port,
950 + struct switch_port_link *link)
951 +{
952 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
953 + u32 speed, poa;
954 +
955 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
956 + return -EINVAL;
957 +
958 + poa = rt305x_esw_rr(esw, RT305X_ESW_REG_POA) >> port;
959 +
960 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
961 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
962 + if (port < RT305X_ESW_NUM_LEDS) {
963 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
964 + } else {
965 + if (port == RT305X_ESW_NUM_PORTS - 1)
966 + poa >>= 1;
967 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
968 + }
969 + switch (speed) {
970 + case 0:
971 + link->speed = SWITCH_PORT_SPEED_10;
972 + break;
973 + case 1:
974 + link->speed = SWITCH_PORT_SPEED_100;
975 + break;
976 + case 2:
977 + case 3: /* forced gige speed can be 2 or 3 */
978 + link->speed = SWITCH_PORT_SPEED_1000;
979 + break;
980 + default:
981 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
982 + break;
983 + }
984 +
985 + return 0;
986 +}
987 +
988 +static int
989 +rt305x_esw_get_port_bool(struct switch_dev *dev,
990 + const struct switch_attr *attr,
991 + struct switch_val *val)
992 +{
993 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
994 + int idx = val->port_vlan;
995 + u32 x, reg, shift;
996 +
997 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
998 + return -EINVAL;
999 +
1000 + switch (attr->id) {
1001 + case RT305X_ESW_ATTR_PORT_DISABLE:
1002 + reg = RT305X_ESW_REG_POC0;
1003 + shift = RT305X_ESW_POC0_DIS_PORT_S;
1004 + break;
1005 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1006 + reg = RT305X_ESW_REG_SGC2;
1007 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1008 + break;
1009 + case RT305X_ESW_ATTR_PORT_UNTAG:
1010 + reg = RT305X_ESW_REG_POC2;
1011 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
1012 + break;
1013 + case RT305X_ESW_ATTR_PORT_LAN:
1014 + reg = RT305X_ESW_REG_SGC2;
1015 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1016 + if (idx >= RT305X_ESW_NUM_LANWAN)
1017 + return -EINVAL;
1018 + break;
1019 + default:
1020 + return -EINVAL;
1021 + }
1022 +
1023 + x = rt305x_esw_rr(esw, reg);
1024 + val->value.i = (x >> (idx + shift)) & 1;
1025 +
1026 + return 0;
1027 +}
1028 +
1029 +static int
1030 +rt305x_esw_set_port_bool(struct switch_dev *dev,
1031 + const struct switch_attr *attr,
1032 + struct switch_val *val)
1033 +{
1034 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1035 + int idx = val->port_vlan;
1036 +
1037 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1038 + val->value.i < 0 || val->value.i > 1)
1039 + return -EINVAL;
1040 +
1041 + switch (attr->id) {
1042 + case RT305X_ESW_ATTR_PORT_DISABLE:
1043 + esw->ports[idx].disable = val->value.i;
1044 + break;
1045 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1046 + esw->ports[idx].doubletag = val->value.i;
1047 + break;
1048 + case RT305X_ESW_ATTR_PORT_UNTAG:
1049 + esw->ports[idx].untag = val->value.i;
1050 + break;
1051 + default:
1052 + return -EINVAL;
1053 + }
1054 +
1055 + return 0;
1056 +}
1057 +
1058 +static int
1059 +rt305x_esw_get_port_recv_badgood(struct switch_dev *dev,
1060 + const struct switch_attr *attr,
1061 + struct switch_val *val)
1062 +{
1063 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1064 + int idx = val->port_vlan;
1065 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1066 + u32 reg;
1067 +
1068 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1069 + return -EINVAL;
1070 +
1071 + reg = rt305x_esw_rr(esw, RT305X_ESW_REG_P0PC + 4*idx);
1072 + val->value.i = (reg >> shift) & 0xffff;
1073 +
1074 + return 0;
1075 +}
1076 +
1077 +static int
1078 +rt305x_esw_get_port_led(struct switch_dev *dev,
1079 + const struct switch_attr *attr,
1080 + struct switch_val *val)
1081 +{
1082 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1083 + int idx = val->port_vlan;
1084 +
1085 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1086 + idx >= RT305X_ESW_NUM_LEDS)
1087 + return -EINVAL;
1088 +
1089 + val->value.i = rt305x_esw_rr(esw, RT305X_ESW_REG_P0LED + 4*idx);
1090 +
1091 + return 0;
1092 +}
1093 +
1094 +static int
1095 +rt305x_esw_set_port_led(struct switch_dev *dev,
1096 + const struct switch_attr *attr,
1097 + struct switch_val *val)
1098 +{
1099 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1100 + int idx = val->port_vlan;
1101 +
1102 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1103 + return -EINVAL;
1104 +
1105 + esw->ports[idx].led = val->value.i;
1106 +
1107 + return 0;
1108 +}
1109 +
1110 +static int
1111 +rt305x_esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1112 +{
1113 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1114 +
1115 + if (port >= RT305X_ESW_NUM_PORTS)
1116 + return -EINVAL;
1117 +
1118 + *val = rt305x_esw_get_pvid(esw, port);
1119 +
1120 + return 0;
1121 +}
1122 +
1123 +static int
1124 +rt305x_esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1125 +{
1126 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1127 +
1128 + if (port >= RT305X_ESW_NUM_PORTS)
1129 + return -EINVAL;
1130 +
1131 + esw->ports[port].pvid = val;
1132 +
1133 + return 0;
1134 +}
1135 +
1136 +static int
1137 +rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1138 +{
1139 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1140 + u32 vmsc, poc2;
1141 + int vlan_idx = -1;
1142 + int i;
1143 +
1144 + val->len = 0;
1145 +
1146 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1147 + return -EINVAL;
1148 +
1149 + /* valid vlan? */
1150 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1151 + if (rt305x_esw_get_vlan_id(esw, i) == val->port_vlan &&
1152 + rt305x_esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1153 + vlan_idx = i;
1154 + break;
1155 + }
1156 + }
1157 +
1158 + if (vlan_idx == -1)
1159 + return -EINVAL;
1160 +
1161 + vmsc = rt305x_esw_get_vmsc(esw, vlan_idx);
1162 + poc2 = rt305x_esw_rr(esw, RT305X_ESW_REG_POC2);
1163 +
1164 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1165 + struct switch_port *p;
1166 + int port_mask = 1 << i;
1167 +
1168 + if (!(vmsc & port_mask))
1169 + continue;
1170 +
1171 + p = &val->value.ports[val->len++];
1172 + p->id = i;
1173 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1174 + p->flags = 0;
1175 + else
1176 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1177 + }
1178 +
1179 + return 0;
1180 +}
1181 +
1182 +static int
1183 +rt305x_esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1184 +{
1185 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1186 + int ports;
1187 + int vlan_idx = -1;
1188 + int i;
1189 +
1190 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1191 + val->len > RT305X_ESW_NUM_PORTS)
1192 + return -EINVAL;
1193 +
1194 + /* one of the already defined vlans? */
1195 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1196 + if (esw->vlans[i].vid == val->port_vlan &&
1197 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1198 + vlan_idx = i;
1199 + break;
1200 + }
1201 + }
1202 +
1203 + /* select a free slot */
1204 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1205 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1206 + vlan_idx = i;
1207 + }
1208 +
1209 + /* bail if all slots are in use */
1210 + if (vlan_idx == -1)
1211 + return -EINVAL;
1212 +
1213 + ports = RT305X_ESW_PORTS_NONE;
1214 + for (i = 0; i < val->len; i++) {
1215 + struct switch_port *p = &val->value.ports[i];
1216 + int port_mask = 1 << p->id;
1217 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1218 +
1219 + if (p->id >= RT305X_ESW_NUM_PORTS)
1220 + return -EINVAL;
1221 +
1222 + ports |= port_mask;
1223 + esw->ports[p->id].untag = untagged;
1224 + }
1225 + esw->vlans[vlan_idx].ports = ports;
1226 + if (ports == RT305X_ESW_PORTS_NONE)
1227 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1228 + else
1229 + esw->vlans[vlan_idx].vid = val->port_vlan;
1230 +
1231 + return 0;
1232 +}
1233 +
1234 +static const struct switch_attr rt305x_esw_global[] = {
1235 + {
1236 + .type = SWITCH_TYPE_INT,
1237 + .name = "enable_vlan",
1238 + .description = "VLAN mode (1:enabled)",
1239 + .max = 1,
1240 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1241 + .get = rt305x_esw_get_vlan_enable,
1242 + .set = rt305x_esw_set_vlan_enable,
1243 + },
1244 + {
1245 + .type = SWITCH_TYPE_INT,
1246 + .name = "alternate_vlan_disable",
1247 + .description = "Use en_vlan instead of doubletag to disable"
1248 + " VLAN mode",
1249 + .max = 1,
1250 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1251 + .get = rt305x_esw_get_alt_vlan_disable,
1252 + .set = rt305x_esw_set_alt_vlan_disable,
1253 + },
1254 +};
1255 +
1256 +static const struct switch_attr rt305x_esw_port[] = {
1257 + {
1258 + .type = SWITCH_TYPE_INT,
1259 + .name = "disable",
1260 + .description = "Port state (1:disabled)",
1261 + .max = 1,
1262 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1263 + .get = rt305x_esw_get_port_bool,
1264 + .set = rt305x_esw_set_port_bool,
1265 + },
1266 + {
1267 + .type = SWITCH_TYPE_INT,
1268 + .name = "doubletag",
1269 + .description = "Double tagging for incoming vlan packets "
1270 + "(1:enabled)",
1271 + .max = 1,
1272 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1273 + .get = rt305x_esw_get_port_bool,
1274 + .set = rt305x_esw_set_port_bool,
1275 + },
1276 + {
1277 + .type = SWITCH_TYPE_INT,
1278 + .name = "untag",
1279 + .description = "Untag (1:strip outgoing vlan tag)",
1280 + .max = 1,
1281 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1282 + .get = rt305x_esw_get_port_bool,
1283 + .set = rt305x_esw_set_port_bool,
1284 + },
1285 + {
1286 + .type = SWITCH_TYPE_INT,
1287 + .name = "led",
1288 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1289 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1290 + " 8:100mact, 10:blink, 12:on)",
1291 + .max = 15,
1292 + .id = RT305X_ESW_ATTR_PORT_LED,
1293 + .get = rt305x_esw_get_port_led,
1294 + .set = rt305x_esw_set_port_led,
1295 + },
1296 + {
1297 + .type = SWITCH_TYPE_INT,
1298 + .name = "lan",
1299 + .description = "HW port group (0:wan, 1:lan)",
1300 + .max = 1,
1301 + .id = RT305X_ESW_ATTR_PORT_LAN,
1302 + .get = rt305x_esw_get_port_bool,
1303 + },
1304 + {
1305 + .type = SWITCH_TYPE_INT,
1306 + .name = "recv_bad",
1307 + .description = "Receive bad packet counter",
1308 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1309 + .get = rt305x_esw_get_port_recv_badgood,
1310 + },
1311 + {
1312 + .type = SWITCH_TYPE_INT,
1313 + .name = "recv_good",
1314 + .description = "Receive good packet counter",
1315 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1316 + .get = rt305x_esw_get_port_recv_badgood,
1317 + },
1318 +};
1319 +
1320 +static const struct switch_attr rt305x_esw_vlan[] = {
1321 +};
1322 +
1323 +static const struct switch_dev_ops rt305x_esw_ops = {
1324 + .attr_global = {
1325 + .attr = rt305x_esw_global,
1326 + .n_attr = ARRAY_SIZE(rt305x_esw_global),
1327 + },
1328 + .attr_port = {
1329 + .attr = rt305x_esw_port,
1330 + .n_attr = ARRAY_SIZE(rt305x_esw_port),
1331 + },
1332 + .attr_vlan = {
1333 + .attr = rt305x_esw_vlan,
1334 + .n_attr = ARRAY_SIZE(rt305x_esw_vlan),
1335 + },
1336 + .get_vlan_ports = rt305x_esw_get_vlan_ports,
1337 + .set_vlan_ports = rt305x_esw_set_vlan_ports,
1338 + .get_port_pvid = rt305x_esw_get_port_pvid,
1339 + .set_port_pvid = rt305x_esw_set_port_pvid,
1340 + .get_port_link = rt305x_esw_get_port_link,
1341 + .apply_config = rt305x_esw_apply_config,
1342 + .reset_switch = rt305x_esw_reset_switch,
1343 +};
1344 +
1345 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1346 + /* All ports are LAN ports. */
1347 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1348 + .reg_initval_fct2 = 0x00d6500c,
1349 + /*
1350 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1351 + * turbo mii off, rgmi 3.3v off
1352 + * port5: disabled
1353 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1354 + */
1355 + .reg_initval_fpa2 = 0x3f502b28,
1356 +};
1357 +
1358 +static const struct of_device_id ralink_esw_match[] = {
1359 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1360 + {},
1361 +};
1362 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1363 +
1364 +static int
1365 +rt305x_esw_probe(struct platform_device *pdev)
1366 +{
1367 + struct device_node *np = pdev->dev.of_node;
1368 + const struct rt305x_esw_platform_data *pdata;
1369 + const __be32 *port_map, *reg_init;
1370 + struct rt305x_esw *esw;
1371 + struct switch_dev *swdev;
1372 + struct resource *res, *irq;
1373 + int err;
1374 +
1375 + pdata = pdev->dev.platform_data;
1376 + if (!pdata) {
1377 + const struct of_device_id *match;
1378 + match = of_match_device(ralink_esw_match, &pdev->dev);
1379 + if (match)
1380 + pdata = (struct rt305x_esw_platform_data *) match->data;
1381 + }
1382 + if (!pdata)
1383 + return -EINVAL;
1384 +
1385 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386 + if (!res) {
1387 + dev_err(&pdev->dev, "no memory resource found\n");
1388 + return -ENOMEM;
1389 + }
1390 +
1391 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1392 + if (!irq) {
1393 + dev_err(&pdev->dev, "no irq resource found\n");
1394 + return -ENOMEM;
1395 + }
1396 +
1397 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1398 + if (!esw) {
1399 + dev_err(&pdev->dev, "no memory for private data\n");
1400 + return -ENOMEM;
1401 + }
1402 +
1403 + esw->dev = &pdev->dev;
1404 + esw->irq = irq->start;
1405 + esw->base = ioremap(res->start, resource_size(res));
1406 + if (!esw->base) {
1407 + dev_err(&pdev->dev, "ioremap failed\n");
1408 + err = -ENOMEM;
1409 + goto free_esw;
1410 + }
1411 +
1412 + port_map = of_get_property(np, "ralink,portmap", NULL);
1413 + if (port_map)
1414 + esw->port_map = be32_to_cpu(*port_map);
1415 +
1416 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1417 + if (reg_init)
1418 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1419 +
1420 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1421 + if (reg_init)
1422 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1423 +
1424 + swdev = &esw->swdev;
1425 + swdev->name = "rt305x-esw";
1426 + swdev->alias = "rt305x";
1427 + swdev->cpu_port = RT305X_ESW_PORT6;
1428 + swdev->ports = RT305X_ESW_NUM_PORTS;
1429 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1430 + swdev->ops = &rt305x_esw_ops;
1431 +
1432 + err = register_switch(swdev, NULL);
1433 + if (err < 0) {
1434 + dev_err(&pdev->dev, "register_switch failed\n");
1435 + goto unmap_base;
1436 + }
1437 +
1438 + platform_set_drvdata(pdev, esw);
1439 +
1440 + esw->pdata = pdata;
1441 + spin_lock_init(&esw->reg_rw_lock);
1442 + rt305x_esw_hw_init(esw);
1443 + rt305x_esw_request_irq(esw);
1444 +
1445 + return 0;
1446 +
1447 +unmap_base:
1448 + iounmap(esw->base);
1449 +free_esw:
1450 + kfree(esw);
1451 + return err;
1452 +}
1453 +
1454 +static int
1455 +rt305x_esw_remove(struct platform_device *pdev)
1456 +{
1457 + struct rt305x_esw *esw;
1458 +
1459 + esw = platform_get_drvdata(pdev);
1460 + if (esw) {
1461 + unregister_switch(&esw->swdev);
1462 + platform_set_drvdata(pdev, NULL);
1463 + iounmap(esw->base);
1464 + kfree(esw);
1465 + }
1466 +
1467 + return 0;
1468 +}
1469 +
1470 +static struct platform_driver rt305x_esw_driver = {
1471 + .probe = rt305x_esw_probe,
1472 + .remove = rt305x_esw_remove,
1473 + .driver = {
1474 + .name = "rt305x-esw",
1475 + .owner = THIS_MODULE,
1476 + .of_match_table = ralink_esw_match,
1477 + },
1478 +};
1479 +
1480 +static int __init
1481 +rt305x_esw_init(void)
1482 +{
1483 + return platform_driver_register(&rt305x_esw_driver);
1484 +}
1485 +
1486 +static void
1487 +rt305x_esw_exit(void)
1488 +{
1489 + platform_driver_unregister(&rt305x_esw_driver);
1490 +}
1491 Index: linux-3.8.3/drivers/net/ethernet/ramips/ramips_eth.h
1492 ===================================================================
1493 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1494 +++ linux-3.8.3/drivers/net/ethernet/ramips/ramips_eth.h 2013-04-02 11:45:25.225274468 +0200
1495 @@ -0,0 +1,375 @@
1496 +/*
1497 + * This program is free software; you can redistribute it and/or modify
1498 + * it under the terms of the GNU General Public License as published by
1499 + * the Free Software Foundation; version 2 of the License
1500 + *
1501 + * This program is distributed in the hope that it will be useful,
1502 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1503 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1504 + * GNU General Public License for more details.
1505 + *
1506 + * You should have received a copy of the GNU General Public License
1507 + * along with this program; if not, write to the Free Software
1508 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1509 + *
1510 + * based on Ralink SDK3.3
1511 + * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
1512 + */
1513 +
1514 +#ifndef RAMIPS_ETH_H
1515 +#define RAMIPS_ETH_H
1516 +
1517 +#include <linux/mii.h>
1518 +#include <linux/interrupt.h>
1519 +#include <linux/netdevice.h>
1520 +#include <linux/dma-mapping.h>
1521 +
1522 +#define NUM_RX_DESC 256
1523 +#define NUM_TX_DESC 256
1524 +
1525 +#define RAMIPS_DELAY_EN_INT 0x80
1526 +#define RAMIPS_DELAY_MAX_INT 0x04
1527 +#define RAMIPS_DELAY_MAX_TOUT 0x04
1528 +#define RAMIPS_DELAY_CHAN (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT)
1529 +#define RAMIPS_DELAY_INIT ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN)
1530 +#define RAMIPS_PSE_FQFC_CFG_INIT 0x80504000
1531 +
1532 +/* interrupt bits */
1533 +#define RAMIPS_CNT_PPE_AF BIT(31)
1534 +#define RAMIPS_CNT_GDM_AF BIT(29)
1535 +#define RAMIPS_PSE_P2_FC BIT(26)
1536 +#define RAMIPS_PSE_BUF_DROP BIT(24)
1537 +#define RAMIPS_GDM_OTHER_DROP BIT(23)
1538 +#define RAMIPS_PSE_P1_FC BIT(22)
1539 +#define RAMIPS_PSE_P0_FC BIT(21)
1540 +#define RAMIPS_PSE_FQ_EMPTY BIT(20)
1541 +#define RAMIPS_GE1_STA_CHG BIT(18)
1542 +#define RAMIPS_TX_COHERENT BIT(17)
1543 +#define RAMIPS_RX_COHERENT BIT(16)
1544 +#define RAMIPS_TX_DONE_INT3 BIT(11)
1545 +#define RAMIPS_TX_DONE_INT2 BIT(10)
1546 +#define RAMIPS_TX_DONE_INT1 BIT(9)
1547 +#define RAMIPS_TX_DONE_INT0 BIT(8)
1548 +#define RAMIPS_RX_DONE_INT0 BIT(2)
1549 +#define RAMIPS_TX_DLY_INT BIT(1)
1550 +#define RAMIPS_RX_DLY_INT BIT(0)
1551 +
1552 +#define RT5350_RX_DLY_INT BIT(30)
1553 +#define RT5350_TX_DLY_INT BIT(28)
1554 +
1555 +/* registers */
1556 +#define RAMIPS_FE_OFFSET 0x0000
1557 +#define RAMIPS_GDMA_OFFSET 0x0020
1558 +#define RAMIPS_PSE_OFFSET 0x0040
1559 +#define RAMIPS_GDMA2_OFFSET 0x0060
1560 +#define RAMIPS_CDMA_OFFSET 0x0080
1561 +#define RAMIPS_PDMA_OFFSET 0x0100
1562 +#define RAMIPS_PPE_OFFSET 0x0200
1563 +#define RAMIPS_CMTABLE_OFFSET 0x0400
1564 +#define RAMIPS_POLICYTABLE_OFFSET 0x1000
1565 +
1566 +#define RT5350_PDMA_OFFSET 0x0800
1567 +#define RT5350_SDM_OFFSET 0x0c00
1568 +
1569 +#define RAMIPS_MDIO_ACCESS (RAMIPS_FE_OFFSET + 0x00)
1570 +#define RAMIPS_MDIO_CFG (RAMIPS_FE_OFFSET + 0x04)
1571 +#define RAMIPS_FE_GLO_CFG (RAMIPS_FE_OFFSET + 0x08)
1572 +#define RAMIPS_FE_RST_GL (RAMIPS_FE_OFFSET + 0x0C)
1573 +#define RAMIPS_FE_INT_STATUS (RAMIPS_FE_OFFSET + 0x10)
1574 +#define RAMIPS_FE_INT_ENABLE (RAMIPS_FE_OFFSET + 0x14)
1575 +#define RAMIPS_MDIO_CFG2 (RAMIPS_FE_OFFSET + 0x18)
1576 +#define RAMIPS_FOC_TS_T (RAMIPS_FE_OFFSET + 0x1C)
1577 +
1578 +#define RAMIPS_GDMA1_FWD_CFG (RAMIPS_GDMA_OFFSET + 0x00)
1579 +#define RAMIPS_GDMA1_SCH_CFG (RAMIPS_GDMA_OFFSET + 0x04)
1580 +#define RAMIPS_GDMA1_SHPR_CFG (RAMIPS_GDMA_OFFSET + 0x08)
1581 +#define RAMIPS_GDMA1_MAC_ADRL (RAMIPS_GDMA_OFFSET + 0x0C)
1582 +#define RAMIPS_GDMA1_MAC_ADRH (RAMIPS_GDMA_OFFSET + 0x10)
1583 +
1584 +#define RAMIPS_GDMA2_FWD_CFG (RAMIPS_GDMA2_OFFSET + 0x00)
1585 +#define RAMIPS_GDMA2_SCH_CFG (RAMIPS_GDMA2_OFFSET + 0x04)
1586 +#define RAMIPS_GDMA2_SHPR_CFG (RAMIPS_GDMA2_OFFSET + 0x08)
1587 +#define RAMIPS_GDMA2_MAC_ADRL (RAMIPS_GDMA2_OFFSET + 0x0C)
1588 +#define RAMIPS_GDMA2_MAC_ADRH (RAMIPS_GDMA2_OFFSET + 0x10)
1589 +
1590 +#define RAMIPS_PSE_FQ_CFG (RAMIPS_PSE_OFFSET + 0x00)
1591 +#define RAMIPS_CDMA_FC_CFG (RAMIPS_PSE_OFFSET + 0x04)
1592 +#define RAMIPS_GDMA1_FC_CFG (RAMIPS_PSE_OFFSET + 0x08)
1593 +#define RAMIPS_GDMA2_FC_CFG (RAMIPS_PSE_OFFSET + 0x0C)
1594 +
1595 +#define RAMIPS_CDMA_CSG_CFG (RAMIPS_CDMA_OFFSET + 0x00)
1596 +#define RAMIPS_CDMA_SCH_CFG (RAMIPS_CDMA_OFFSET + 0x04)
1597 +
1598 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
1599 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
1600 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
1601 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
1602 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
1603 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
1604 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
1605 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
1606 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
1607 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
1608 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
1609 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
1610 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
1611 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
1612 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
1613 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
1614 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
1615 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
1616 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
1617 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
1618 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
1619 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
1620 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
1621 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
1622 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
1623 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
1624 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
1625 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
1626 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
1627 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
1628 +
1629 +
1630 +#define RAMIPS_PDMA_GLO_CFG (RAMIPS_PDMA_OFFSET + 0x00)
1631 +#define RAMIPS_PDMA_RST_CFG (RAMIPS_PDMA_OFFSET + 0x04)
1632 +#define RAMIPS_PDMA_SCH_CFG (RAMIPS_PDMA_OFFSET + 0x08)
1633 +#define RAMIPS_DLY_INT_CFG (RAMIPS_PDMA_OFFSET + 0x0C)
1634 +#define RAMIPS_TX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x10)
1635 +#define RAMIPS_TX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x14)
1636 +#define RAMIPS_TX_CTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x18)
1637 +#define RAMIPS_TX_DTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x1C)
1638 +#define RAMIPS_TX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x20)
1639 +#define RAMIPS_TX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x24)
1640 +#define RAMIPS_TX_CTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x28)
1641 +#define RAMIPS_TX_DTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x2C)
1642 +#define RAMIPS_RX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x30)
1643 +#define RAMIPS_RX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x34)
1644 +#define RAMIPS_RX_CALC_IDX0 (RAMIPS_PDMA_OFFSET + 0x38)
1645 +#define RAMIPS_RX_DRX_IDX0 (RAMIPS_PDMA_OFFSET + 0x3C)
1646 +#define RAMIPS_TX_BASE_PTR2 (RAMIPS_PDMA_OFFSET + 0x40)
1647 +#define RAMIPS_TX_MAX_CNT2 (RAMIPS_PDMA_OFFSET + 0x44)
1648 +#define RAMIPS_TX_CTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x48)
1649 +#define RAMIPS_TX_DTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x4C)
1650 +#define RAMIPS_TX_BASE_PTR3 (RAMIPS_PDMA_OFFSET + 0x50)
1651 +#define RAMIPS_TX_MAX_CNT3 (RAMIPS_PDMA_OFFSET + 0x54)
1652 +#define RAMIPS_TX_CTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x58)
1653 +#define RAMIPS_TX_DTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x5C)
1654 +#define RAMIPS_RX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x60)
1655 +#define RAMIPS_RX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x64)
1656 +#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68)
1657 +#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C)
1658 +
1659 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
1660 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
1661 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
1662 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
1663 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
1664 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
1665 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
1666 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
1667 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
1668 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
1669 +
1670 +#define RT5350_SDM_ICS_EN BIT(16)
1671 +#define RT5350_SDM_TCS_EN BIT(17)
1672 +#define RT5350_SDM_UCS_EN BIT(18)
1673 +
1674 +
1675 +/* MDIO_CFG register bits */
1676 +#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29)
1677 +#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16)
1678 +#define RAMIPS_MDIO_CFG_GP1_FRC_EN BIT(15)
1679 +#define RAMIPS_MDIO_CFG_GP1_SPEED_10 (0 << 13)
1680 +#define RAMIPS_MDIO_CFG_GP1_SPEED_100 (1 << 13)
1681 +#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
1682 +#define RAMIPS_MDIO_CFG_GP1_DUPLEX BIT(12)
1683 +#define RAMIPS_MDIO_CFG_GP1_FC_TX BIT(11)
1684 +#define RAMIPS_MDIO_CFG_GP1_FC_RX BIT(10)
1685 +#define RAMIPS_MDIO_CFG_GP1_LNK_DWN BIT(9)
1686 +#define RAMIPS_MDIO_CFG_GP1_AN_FAIL BIT(8)
1687 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
1688 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
1689 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
1690 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
1691 +#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5)
1692 +#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4)
1693 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
1694 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
1695 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
1696 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
1697 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0 0
1698 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1
1699 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2
1700 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3
1701 +
1702 +/* uni-cast port */
1703 +#define RAMIPS_GDM1_ICS_EN BIT(22)
1704 +#define RAMIPS_GDM1_TCS_EN BIT(21)
1705 +#define RAMIPS_GDM1_UCS_EN BIT(20)
1706 +#define RAMIPS_GDM1_JMB_EN BIT(19)
1707 +#define RAMIPS_GDM1_STRPCRC BIT(16)
1708 +#define RAMIPS_GDM1_UFRC_P_CPU (0 << 12)
1709 +#define RAMIPS_GDM1_UFRC_P_GDMA1 (1 << 12)
1710 +#define RAMIPS_GDM1_UFRC_P_PPE (6 << 12)
1711 +
1712 +/* checksums */
1713 +#define RAMIPS_ICS_GEN_EN BIT(2)
1714 +#define RAMIPS_UCS_GEN_EN BIT(1)
1715 +#define RAMIPS_TCS_GEN_EN BIT(0)
1716 +
1717 +/* dma ring */
1718 +#define RAMIPS_PST_DRX_IDX0 BIT(16)
1719 +#define RAMIPS_PST_DTX_IDX3 BIT(3)
1720 +#define RAMIPS_PST_DTX_IDX2 BIT(2)
1721 +#define RAMIPS_PST_DTX_IDX1 BIT(1)
1722 +#define RAMIPS_PST_DTX_IDX0 BIT(0)
1723 +
1724 +#define RAMIPS_TX_WB_DDONE BIT(6)
1725 +#define RAMIPS_RX_DMA_BUSY BIT(3)
1726 +#define RAMIPS_TX_DMA_BUSY BIT(1)
1727 +#define RAMIPS_RX_DMA_EN BIT(2)
1728 +#define RAMIPS_TX_DMA_EN BIT(0)
1729 +
1730 +#define RAMIPS_PDMA_SIZE_4DWORDS (0 << 4)
1731 +#define RAMIPS_PDMA_SIZE_8DWORDS (1 << 4)
1732 +#define RAMIPS_PDMA_SIZE_16DWORDS (2 << 4)
1733 +
1734 +#define RAMIPS_US_CYC_CNT_MASK 0xff
1735 +#define RAMIPS_US_CYC_CNT_SHIFT 0x8
1736 +#define RAMIPS_US_CYC_CNT_DIVISOR 1000000
1737 +
1738 +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
1739 +#define RX_DMA_LSO BIT(30)
1740 +#define RX_DMA_DONE BIT(31)
1741 +
1742 +struct ramips_rx_dma {
1743 + unsigned int rxd1;
1744 + unsigned int rxd2;
1745 + unsigned int rxd3;
1746 + unsigned int rxd4;
1747 +} __packed __aligned(4);
1748 +
1749 +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
1750 +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
1751 +#define TX_DMA_LSO BIT(30)
1752 +#define TX_DMA_DONE BIT(31)
1753 +#define TX_DMA_QN(_x) ((_x) << 16)
1754 +#define TX_DMA_PN(_x) ((_x) << 24)
1755 +#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
1756 +#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
1757 +
1758 +struct ramips_tx_dma {
1759 + unsigned int txd1;
1760 + unsigned int txd2;
1761 + unsigned int txd3;
1762 + unsigned int txd4;
1763 +} __packed __aligned(4);
1764 +
1765 +struct raeth_tx_info {
1766 + struct ramips_tx_dma *tx_desc;
1767 + struct sk_buff *tx_skb;
1768 +};
1769 +
1770 +struct raeth_rx_info {
1771 + struct ramips_rx_dma *rx_desc;
1772 + struct sk_buff *rx_skb;
1773 + dma_addr_t rx_dma;
1774 + unsigned int pad;
1775 +};
1776 +
1777 +struct raeth_int_stats {
1778 + unsigned long rx_delayed;
1779 + unsigned long tx_delayed;
1780 + unsigned long rx_done0;
1781 + unsigned long tx_done0;
1782 + unsigned long tx_done1;
1783 + unsigned long tx_done2;
1784 + unsigned long tx_done3;
1785 + unsigned long rx_coherent;
1786 + unsigned long tx_coherent;
1787 +
1788 + unsigned long pse_fq_empty;
1789 + unsigned long pse_p0_fc;
1790 + unsigned long pse_p1_fc;
1791 + unsigned long pse_p2_fc;
1792 + unsigned long pse_buf_drop;
1793 +
1794 + unsigned long total;
1795 +};
1796 +
1797 +struct raeth_debug {
1798 + struct dentry *debugfs_dir;
1799 +
1800 + struct raeth_int_stats int_stats;
1801 +};
1802 +
1803 +struct raeth_priv
1804 +{
1805 + struct device_node *of_node;
1806 +
1807 + struct raeth_rx_info *rx_info;
1808 + dma_addr_t rx_desc_dma;
1809 + struct tasklet_struct rx_tasklet;
1810 + struct ramips_rx_dma *rx;
1811 +
1812 + struct raeth_tx_info *tx_info;
1813 + dma_addr_t tx_desc_dma;
1814 + struct tasklet_struct tx_housekeeping_tasklet;
1815 + struct ramips_tx_dma *tx;
1816 +
1817 + unsigned int skb_free_idx;
1818 +
1819 + spinlock_t page_lock;
1820 + struct net_device *netdev;
1821 + struct device *parent;
1822 +
1823 + int link;
1824 + int speed;
1825 + int duplex;
1826 + int tx_fc;
1827 + int rx_fc;
1828 +
1829 + struct mii_bus *mii_bus;
1830 + int mii_irq[PHY_MAX_ADDR];
1831 + struct phy_device *phy_dev;
1832 + spinlock_t phy_lock;
1833 + unsigned long sys_freq;
1834 +
1835 + unsigned char mac[6];
1836 + void (*reset_fe)(void);
1837 + int min_pkt_len;
1838 +
1839 + u32 phy_mask;
1840 + phy_interface_t phy_if_mode;
1841 +
1842 +#ifdef CONFIG_NET_RAMIPS_DEBUG_FS
1843 + struct raeth_debug debug;
1844 +#endif
1845 +};
1846 +
1847 +struct ramips_soc_data
1848 +{
1849 + unsigned char mac[6];
1850 + void (*reset_fe)(void);
1851 + int min_pkt_len;
1852 +};
1853 +
1854 +
1855 +#ifdef CONFIG_NET_RAMIPS_DEBUG_FS
1856 +int raeth_debugfs_root_init(void);
1857 +void raeth_debugfs_root_exit(void);
1858 +int raeth_debugfs_init(struct raeth_priv *re);
1859 +void raeth_debugfs_exit(struct raeth_priv *re);
1860 +void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status);
1861 +#else
1862 +static inline int raeth_debugfs_root_init(void) { return 0; }
1863 +static inline void raeth_debugfs_root_exit(void) {}
1864 +static inline int raeth_debugfs_init(struct raeth_priv *re) { return 0; }
1865 +static inline void raeth_debugfs_exit(struct raeth_priv *re) {}
1866 +static inline void raeth_debugfs_update_int_stats(struct raeth_priv *re,
1867 + u32 status) {}
1868 +#endif /* CONFIG_NET_RAMIPS_DEBUG_FS */
1869 +
1870 +#endif /* RAMIPS_ETH_H */
1871 Index: linux-3.8.3/drivers/net/ethernet/ramips/ramips_main.c
1872 ===================================================================
1873 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1874 +++ linux-3.8.3/drivers/net/ethernet/ramips/ramips_main.c 2013-04-02 12:07:58.749306720 +0200
1875 @@ -0,0 +1,1285 @@
1876 +/*
1877 + * This program is free software; you can redistribute it and/or modify
1878 + * it under the terms of the GNU General Public License as published by
1879 + * the Free Software Foundation; version 2 of the License
1880 + *
1881 + * This program is distributed in the hope that it will be useful,
1882 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1883 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1884 + * GNU General Public License for more details.
1885 + *
1886 + * You should have received a copy of the GNU General Public License
1887 + * along with this program; if not, write to the Free Software
1888 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1889 + *
1890 + * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
1891 + */
1892 +
1893 +#include <linux/module.h>
1894 +#include <linux/kernel.h>
1895 +#include <linux/types.h>
1896 +#include <linux/dma-mapping.h>
1897 +#include <linux/init.h>
1898 +#include <linux/skbuff.h>
1899 +#include <linux/etherdevice.h>
1900 +#include <linux/ethtool.h>
1901 +#include <linux/platform_device.h>
1902 +#include <linux/phy.h>
1903 +#include <linux/of_device.h>
1904 +#include <linux/clk.h>
1905 +#include <linux/of_net.h>
1906 +
1907 +#include "ramips_eth.h"
1908 +
1909 +#define TX_TIMEOUT (20 * HZ / 100)
1910 +#define MAX_RX_LENGTH 1600
1911 +
1912 +#ifdef CONFIG_SOC_RT305X
1913 +#include <rt305x.h>
1914 +#include "ramips_esw.c"
1915 +#else
1916 +#include <asm/mach-ralink/ralink_regs.h>
1917 +static inline int rt305x_esw_init(void) { return 0; }
1918 +static inline void rt305x_esw_exit(void) { }
1919 +static inline int soc_is_rt5350(void) { return 0; }
1920 +#endif
1921 +
1922 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
1923 +
1924 +#ifdef CONFIG_NET_RAMIPS_DEBUG
1925 +#define RADEBUG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
1926 +#else
1927 +#define RADEBUG(fmt, args...) do {} while (0)
1928 +#endif
1929 +
1930 +#define RX_DLY_INT ((soc_is_rt5350())?(RT5350_RX_DLY_INT):(RAMIPS_RX_DLY_INT))
1931 +#define TX_DLY_INT ((soc_is_rt5350())?(RT5350_TX_DLY_INT):(RAMIPS_TX_DLY_INT))
1932 +
1933 +enum raeth_reg {
1934 + RAETH_REG_PDMA_GLO_CFG = 0,
1935 + RAETH_REG_PDMA_RST_CFG,
1936 + RAETH_REG_DLY_INT_CFG,
1937 + RAETH_REG_TX_BASE_PTR0,
1938 + RAETH_REG_TX_MAX_CNT0,
1939 + RAETH_REG_TX_CTX_IDX0,
1940 + RAETH_REG_RX_BASE_PTR0,
1941 + RAETH_REG_RX_MAX_CNT0,
1942 + RAETH_REG_RX_CALC_IDX0,
1943 + RAETH_REG_FE_INT_ENABLE,
1944 + RAETH_REG_FE_INT_STATUS,
1945 + RAETH_REG_COUNT
1946 +};
1947 +
1948 +static const u32 ramips_reg_table[RAETH_REG_COUNT] = {
1949 + [RAETH_REG_PDMA_GLO_CFG] = RAMIPS_PDMA_GLO_CFG,
1950 + [RAETH_REG_PDMA_RST_CFG] = RAMIPS_PDMA_RST_CFG,
1951 + [RAETH_REG_DLY_INT_CFG] = RAMIPS_DLY_INT_CFG,
1952 + [RAETH_REG_TX_BASE_PTR0] = RAMIPS_TX_BASE_PTR0,
1953 + [RAETH_REG_TX_MAX_CNT0] = RAMIPS_TX_MAX_CNT0,
1954 + [RAETH_REG_TX_CTX_IDX0] = RAMIPS_TX_CTX_IDX0,
1955 + [RAETH_REG_RX_BASE_PTR0] = RAMIPS_RX_BASE_PTR0,
1956 + [RAETH_REG_RX_MAX_CNT0] = RAMIPS_RX_MAX_CNT0,
1957 + [RAETH_REG_RX_CALC_IDX0] = RAMIPS_RX_CALC_IDX0,
1958 + [RAETH_REG_FE_INT_ENABLE] = RAMIPS_FE_INT_ENABLE,
1959 + [RAETH_REG_FE_INT_STATUS] = RAMIPS_FE_INT_STATUS,
1960 +};
1961 +
1962 +static const u32 rt5350_reg_table[RAETH_REG_COUNT] = {
1963 + [RAETH_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
1964 + [RAETH_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
1965 + [RAETH_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
1966 + [RAETH_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
1967 + [RAETH_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
1968 + [RAETH_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
1969 + [RAETH_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
1970 + [RAETH_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
1971 + [RAETH_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
1972 + [RAETH_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
1973 + [RAETH_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
1974 +};
1975 +
1976 +static struct net_device * ramips_dev;
1977 +static void __iomem *ramips_fe_base = 0;
1978 +
1979 +static inline u32 get_reg_offset(enum raeth_reg reg)
1980 +{
1981 + const u32 *table;
1982 +
1983 + if (soc_is_rt5350())
1984 + table = rt5350_reg_table;
1985 + else
1986 + table = ramips_reg_table;
1987 +
1988 + return table[reg];
1989 +}
1990 +
1991 +static inline void
1992 +ramips_fe_wr(u32 val, unsigned reg)
1993 +{
1994 + __raw_writel(val, ramips_fe_base + reg);
1995 +}
1996 +
1997 +static inline u32
1998 +ramips_fe_rr(unsigned reg)
1999 +{
2000 + return __raw_readl(ramips_fe_base + reg);
2001 +}
2002 +
2003 +static inline void
2004 +ramips_fe_twr(u32 val, enum raeth_reg reg)
2005 +{
2006 + ramips_fe_wr(val, get_reg_offset(reg));
2007 +}
2008 +
2009 +static inline u32
2010 +ramips_fe_trr(enum raeth_reg reg)
2011 +{
2012 + return ramips_fe_rr(get_reg_offset(reg));
2013 +}
2014 +
2015 +static inline void
2016 +ramips_fe_int_disable(u32 mask)
2017 +{
2018 + ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) & ~mask,
2019 + RAETH_REG_FE_INT_ENABLE);
2020 + /* flush write */
2021 + ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2022 +}
2023 +
2024 +static inline void
2025 +ramips_fe_int_enable(u32 mask)
2026 +{
2027 + ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) | mask,
2028 + RAETH_REG_FE_INT_ENABLE);
2029 + /* flush write */
2030 + ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2031 +}
2032 +
2033 +static inline void
2034 +ramips_hw_set_macaddr(unsigned char *mac)
2035 +{
2036 + if (soc_is_rt5350()) {
2037 + ramips_fe_wr((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
2038 + ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2039 + RT5350_SDM_MAC_ADRL);
2040 + } else {
2041 + ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH);
2042 + ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2043 + RAMIPS_GDMA1_MAC_ADRL);
2044 + }
2045 +}
2046 +
2047 +static struct sk_buff *
2048 +ramips_alloc_skb(struct raeth_priv *re)
2049 +{
2050 + struct sk_buff *skb;
2051 +
2052 + skb = netdev_alloc_skb(re->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
2053 + if (!skb)
2054 + return NULL;
2055 +
2056 + skb_reserve(skb, NET_IP_ALIGN);
2057 +
2058 + return skb;
2059 +}
2060 +
2061 +static void
2062 +ramips_ring_setup(struct raeth_priv *re)
2063 +{
2064 + int len;
2065 + int i;
2066 +
2067 + memset(re->tx_info, 0, NUM_TX_DESC * sizeof(struct raeth_tx_info));
2068 +
2069 + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2070 + memset(re->tx, 0, len);
2071 +
2072 + for (i = 0; i < NUM_TX_DESC; i++) {
2073 + struct raeth_tx_info *txi;
2074 + struct ramips_tx_dma *txd;
2075 +
2076 + txd = &re->tx[i];
2077 + txd->txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
2078 + txd->txd2 = TX_DMA_LSO | TX_DMA_DONE;
2079 +
2080 + txi = &re->tx_info[i];
2081 + txi->tx_desc = txd;
2082 + if (txi->tx_skb != NULL) {
2083 + netdev_warn(re->netdev,
2084 + "dirty skb for TX desc %d\n", i);
2085 + txi->tx_skb = NULL;
2086 + }
2087 + }
2088 +
2089 + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2090 + memset(re->rx, 0, len);
2091 +
2092 + for (i = 0; i < NUM_RX_DESC; i++) {
2093 + struct raeth_rx_info *rxi;
2094 + struct ramips_rx_dma *rxd;
2095 + dma_addr_t dma_addr;
2096 +
2097 + rxd = &re->rx[i];
2098 + rxi = &re->rx_info[i];
2099 + BUG_ON(rxi->rx_skb == NULL);
2100 + dma_addr = dma_map_single(&re->netdev->dev, rxi->rx_skb->data,
2101 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
2102 + rxi->rx_dma = dma_addr;
2103 + rxi->rx_desc = rxd;
2104 +
2105 + rxd->rxd1 = (unsigned int) dma_addr;
2106 + rxd->rxd2 = RX_DMA_LSO;
2107 + }
2108 +
2109 + /* flush descriptors */
2110 + wmb();
2111 +}
2112 +
2113 +static void
2114 +ramips_ring_cleanup(struct raeth_priv *re)
2115 +{
2116 + int i;
2117 +
2118 + for (i = 0; i < NUM_RX_DESC; i++) {
2119 + struct raeth_rx_info *rxi;
2120 +
2121 + rxi = &re->rx_info[i];
2122 + if (rxi->rx_skb)
2123 + dma_unmap_single(&re->netdev->dev, rxi->rx_dma,
2124 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
2125 + }
2126 +
2127 + for (i = 0; i < NUM_TX_DESC; i++) {
2128 + struct raeth_tx_info *txi;
2129 +
2130 + txi = &re->tx_info[i];
2131 + if (txi->tx_skb) {
2132 + dev_kfree_skb_any(txi->tx_skb);
2133 + txi->tx_skb = NULL;
2134 + }
2135 + }
2136 +
2137 + netdev_reset_queue(re->netdev);
2138 +}
2139 +
2140 +#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT3883)
2141 +
2142 +#define RAMIPS_MDIO_RETRY 1000
2143 +
2144 +static unsigned char *ramips_speed_str(struct raeth_priv *re)
2145 +{
2146 + switch (re->speed) {
2147 + case SPEED_1000:
2148 + return "1000";
2149 + case SPEED_100:
2150 + return "100";
2151 + case SPEED_10:
2152 + return "10";
2153 + }
2154 +
2155 + return "?";
2156 +}
2157 +
2158 +static void ramips_link_adjust(struct raeth_priv *re)
2159 +{
2160 + u32 mdio_cfg;
2161 +
2162 + if (!re->link) {
2163 + netif_carrier_off(re->netdev);
2164 + netdev_info(re->netdev, "link down\n");
2165 + return;
2166 + }
2167 +
2168 + mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
2169 + RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
2170 + RAMIPS_MDIO_CFG_GP1_FRC_EN;
2171 +
2172 + if (re->duplex == DUPLEX_FULL)
2173 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX;
2174 +
2175 + if (re->tx_fc)
2176 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX;
2177 +
2178 + if (re->rx_fc)
2179 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX;
2180 +
2181 + switch (re->speed) {
2182 + case SPEED_10:
2183 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10;
2184 + break;
2185 + case SPEED_100:
2186 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100;
2187 + break;
2188 + case SPEED_1000:
2189 + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000;
2190 + break;
2191 + default:
2192 + BUG();
2193 + }
2194 +
2195 + ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG);
2196 +
2197 + netif_carrier_on(re->netdev);
2198 + netdev_info(re->netdev, "link up (%sMbps/%s duplex)\n",
2199 + ramips_speed_str(re),
2200 + (DUPLEX_FULL == re->duplex) ? "Full" : "Half");
2201 +}
2202 +
2203 +static int
2204 +ramips_mdio_wait_ready(struct raeth_priv *re)
2205 +{
2206 + int retries;
2207 +
2208 + retries = RAMIPS_MDIO_RETRY;
2209 + while (1) {
2210 + u32 t;
2211 +
2212 + t = ramips_fe_rr(RAMIPS_MDIO_ACCESS);
2213 + if ((t & (0x1 << 31)) == 0)
2214 + return 0;
2215 +
2216 + if (retries-- == 0)
2217 + break;
2218 +
2219 + udelay(1);
2220 + }
2221 +
2222 + dev_err(re->parent, "MDIO operation timed out\n");
2223 + return -ETIMEDOUT;
2224 +}
2225 +
2226 +static int
2227 +ramips_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2228 +{
2229 + struct raeth_priv *re = bus->priv;
2230 + int err;
2231 + u32 t;
2232 +
2233 + err = ramips_mdio_wait_ready(re);
2234 + if (err)
2235 + return 0xffff;
2236 +
2237 + t = (phy_addr << 24) | (phy_reg << 16);
2238 + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2239 + t |= (1 << 31);
2240 + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2241 +
2242 + err = ramips_mdio_wait_ready(re);
2243 + if (err)
2244 + return 0xffff;
2245 +
2246 + RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2247 + phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff);
2248 +
2249 + return ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff;
2250 +}
2251 +
2252 +static int
2253 +ramips_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2254 +{
2255 + struct raeth_priv *re = bus->priv;
2256 + int err;
2257 + u32 t;
2258 +
2259 + RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2260 + phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff);
2261 +
2262 + err = ramips_mdio_wait_ready(re);
2263 + if (err)
2264 + return err;
2265 +
2266 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2267 + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2268 + t |= (1 << 31);
2269 + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2270 +
2271 + return ramips_mdio_wait_ready(re);
2272 +}
2273 +
2274 +static int
2275 +ramips_mdio_reset(struct mii_bus *bus)
2276 +{
2277 + /* TODO */
2278 + return 0;
2279 +}
2280 +
2281 +static int
2282 +ramips_mdio_init(struct raeth_priv *re)
2283 +{
2284 + int err;
2285 + int i;
2286 +
2287 + re->mii_bus = mdiobus_alloc();
2288 + if (re->mii_bus == NULL)
2289 + return -ENOMEM;
2290 +
2291 + re->mii_bus->name = "ramips_mdio";
2292 + re->mii_bus->read = ramips_mdio_read;
2293 + re->mii_bus->write = ramips_mdio_write;
2294 + re->mii_bus->reset = ramips_mdio_reset;
2295 + re->mii_bus->irq = re->mii_irq;
2296 + re->mii_bus->priv = re;
2297 + re->mii_bus->parent = re->parent;
2298 +
2299 + snprintf(re->mii_bus->id, MII_BUS_ID_SIZE, "%s", "ramips_mdio");
2300 + re->mii_bus->phy_mask = 0;
2301 +
2302 + for (i = 0; i < PHY_MAX_ADDR; i++)
2303 + re->mii_irq[i] = PHY_POLL;
2304 +
2305 + err = mdiobus_register(re->mii_bus);
2306 + if (err)
2307 + goto err_free_bus;
2308 +
2309 + return 0;
2310 +
2311 +err_free_bus:
2312 + kfree(re->mii_bus);
2313 + return err;
2314 +}
2315 +
2316 +static void
2317 +ramips_mdio_cleanup(struct raeth_priv *re)
2318 +{
2319 + mdiobus_unregister(re->mii_bus);
2320 + kfree(re->mii_bus);
2321 +}
2322 +
2323 +static void
2324 +ramips_phy_link_adjust(struct net_device *dev)
2325 +{
2326 + struct raeth_priv *re = netdev_priv(dev);
2327 + struct phy_device *phydev = re->phy_dev;
2328 + unsigned long flags;
2329 + int status_change = 0;
2330 +
2331 + spin_lock_irqsave(&re->phy_lock, flags);
2332 +
2333 + if (phydev->link)
2334 + if (re->duplex != phydev->duplex ||
2335 + re->speed != phydev->speed)
2336 + status_change = 1;
2337 +
2338 + if (phydev->link != re->link)
2339 + status_change = 1;
2340 +
2341 + re->link = phydev->link;
2342 + re->duplex = phydev->duplex;
2343 + re->speed = phydev->speed;
2344 +
2345 + if (status_change)
2346 + ramips_link_adjust(re);
2347 +
2348 + spin_unlock_irqrestore(&re->phy_lock, flags);
2349 +}
2350 +
2351 +static int
2352 +ramips_phy_connect_multi(struct raeth_priv *re)
2353 +{
2354 + struct net_device *netdev = re->netdev;
2355 + struct phy_device *phydev = NULL;
2356 + int phy_addr;
2357 + int ret = 0;
2358 +
2359 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2360 + if (!(re->phy_mask & (1 << phy_addr)))
2361 + continue;
2362 +
2363 + if (re->mii_bus->phy_map[phy_addr] == NULL)
2364 + continue;
2365 +
2366 + RADEBUG("%s: PHY found at %s, uid=%08x\n",
2367 + netdev->name,
2368 + dev_name(&re->mii_bus->phy_map[phy_addr]->dev),
2369 + re->mii_bus->phy_map[phy_addr]->phy_id);
2370 +
2371 + if (phydev == NULL)
2372 + phydev = re->mii_bus->phy_map[phy_addr];
2373 + }
2374 +
2375 + if (!phydev) {
2376 + netdev_err(netdev, "no PHY found with phy_mask=%08x\n",
2377 + re->phy_mask);
2378 + return -ENODEV;
2379 + }
2380 +
2381 + re->phy_dev = phy_connect(netdev, dev_name(&phydev->dev),
2382 + ramips_phy_link_adjust, 0, re->phy_if_mode);
2383 +
2384 + if (IS_ERR(re->phy_dev)) {
2385 + netdev_err(netdev, "could not connect to PHY at %s\n",
2386 + dev_name(&phydev->dev));
2387 + return PTR_ERR(re->phy_dev);
2388 + }
2389 +
2390 + phydev->supported &= PHY_GBIT_FEATURES;
2391 + phydev->advertising = phydev->supported;
2392 +
2393 + RADEBUG("%s: connected to PHY at %s [uid=%08x, driver=%s]\n",
2394 + netdev->name, dev_name(&phydev->dev),
2395 + phydev->phy_id, phydev->drv->name);
2396 +
2397 + re->link = 0;
2398 + re->speed = 0;
2399 + re->duplex = -1;
2400 + re->rx_fc = 0;
2401 + re->tx_fc = 0;
2402 +
2403 + return ret;
2404 +}
2405 +
2406 +static int
2407 +ramips_phy_connect_fixed(struct raeth_priv *re)
2408 +{
2409 + if (!re->speed) {
2410 + const __be32 *link;
2411 + int size;
2412 +
2413 + link = of_get_property(re->of_node,
2414 + "ralink,fixed-link", &size);
2415 + if (!link || size != (4 * sizeof(*link)))
2416 + return -ENOENT;
2417 +
2418 + re->speed = be32_to_cpup(link++);
2419 + re->duplex = be32_to_cpup(link++);
2420 + re->tx_fc = be32_to_cpup(link++);
2421 + re->rx_fc = be32_to_cpup(link++);
2422 + }
2423 +
2424 + switch (re->speed) {
2425 + case SPEED_10:
2426 + case SPEED_100:
2427 + case SPEED_1000:
2428 + break;
2429 + default:
2430 + netdev_err(re->netdev, "invalid speed specified\n");
2431 + return -EINVAL;
2432 + }
2433 +
2434 + pr_info("%s: using fixed link parameters\n", re->netdev->name);
2435 + return 0;
2436 +}
2437 +
2438 +static int
2439 +ramips_phy_connect(struct raeth_priv *re)
2440 +{
2441 + const __be32 *mask;
2442 +
2443 + mask = of_get_property(re->of_node, "ralink,phy-mask", NULL);
2444 + re->phy_if_mode = of_get_phy_mode(re->of_node);
2445 +
2446 + if (!re->phy_if_mode || !mask)
2447 + return ramips_phy_connect_fixed(re);
2448 +
2449 + re->phy_mask = be32_to_cpup(mask);
2450 + return ramips_phy_connect_multi(re);
2451 +
2452 +}
2453 +
2454 +static void
2455 +ramips_phy_disconnect(struct raeth_priv *re)
2456 +{
2457 + if (re->phy_dev)
2458 + phy_disconnect(re->phy_dev);
2459 +}
2460 +
2461 +static void
2462 +ramips_phy_start(struct raeth_priv *re)
2463 +{
2464 + unsigned long flags;
2465 +
2466 + if (re->phy_dev) {
2467 + phy_start(re->phy_dev);
2468 + } else {
2469 + spin_lock_irqsave(&re->phy_lock, flags);
2470 + re->link = 1;
2471 + ramips_link_adjust(re);
2472 + spin_unlock_irqrestore(&re->phy_lock, flags);
2473 + }
2474 +}
2475 +
2476 +static void
2477 +ramips_phy_stop(struct raeth_priv *re)
2478 +{
2479 + unsigned long flags;
2480 +
2481 + if (re->phy_dev)
2482 + phy_stop(re->phy_dev);
2483 +
2484 + spin_lock_irqsave(&re->phy_lock, flags);
2485 + re->link = 0;
2486 + ramips_link_adjust(re);
2487 + spin_unlock_irqrestore(&re->phy_lock, flags);
2488 +}
2489 +#else
2490 +static inline int
2491 +ramips_mdio_init(struct raeth_priv *re)
2492 +{
2493 + return 0;
2494 +}
2495 +
2496 +static inline void
2497 +ramips_mdio_cleanup(struct raeth_priv *re)
2498 +{
2499 +}
2500 +
2501 +static inline int
2502 +ramips_phy_connect(struct raeth_priv *re)
2503 +{
2504 + return 0;
2505 +}
2506 +
2507 +static inline void
2508 +ramips_phy_disconnect(struct raeth_priv *re)
2509 +{
2510 +}
2511 +
2512 +static inline void
2513 +ramips_phy_start(struct raeth_priv *re)
2514 +{
2515 +}
2516 +
2517 +static inline void
2518 +ramips_phy_stop(struct raeth_priv *re)
2519 +{
2520 +}
2521 +#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT3883 */
2522 +
2523 +static void
2524 +ramips_ring_free(struct raeth_priv *re)
2525 +{
2526 + int len;
2527 + int i;
2528 +
2529 + if (re->rx_info) {
2530 + for (i = 0; i < NUM_RX_DESC; i++) {
2531 + struct raeth_rx_info *rxi;
2532 +
2533 + rxi = &re->rx_info[i];
2534 + if (rxi->rx_skb)
2535 + dev_kfree_skb_any(rxi->rx_skb);
2536 + }
2537 + kfree(re->rx_info);
2538 + }
2539 +
2540 + if (re->rx) {
2541 + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2542 + dma_free_coherent(&re->netdev->dev, len, re->rx,
2543 + re->rx_desc_dma);
2544 + }
2545 +
2546 + if (re->tx) {
2547 + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2548 + dma_free_coherent(&re->netdev->dev, len, re->tx,
2549 + re->tx_desc_dma);
2550 + }
2551 +
2552 + kfree(re->tx_info);
2553 +}
2554 +
2555 +static int
2556 +ramips_ring_alloc(struct raeth_priv *re)
2557 +{
2558 + int len;
2559 + int err = -ENOMEM;
2560 + int i;
2561 +
2562 + re->tx_info = kzalloc(NUM_TX_DESC * sizeof(struct raeth_tx_info),
2563 + GFP_ATOMIC);
2564 + if (!re->tx_info)
2565 + goto err_cleanup;
2566 +
2567 + re->rx_info = kzalloc(NUM_RX_DESC * sizeof(struct raeth_rx_info),
2568 + GFP_ATOMIC);
2569 + if (!re->rx_info)
2570 + goto err_cleanup;
2571 +
2572 + /* allocate tx ring */
2573 + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2574 + re->tx = dma_alloc_coherent(&re->netdev->dev, len,
2575 + &re->tx_desc_dma, GFP_ATOMIC);
2576 + if (!re->tx)
2577 + goto err_cleanup;
2578 +
2579 + /* allocate rx ring */
2580 + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2581 + re->rx = dma_alloc_coherent(&re->netdev->dev, len,
2582 + &re->rx_desc_dma, GFP_ATOMIC);
2583 + if (!re->rx)
2584 + goto err_cleanup;
2585 +
2586 + for (i = 0; i < NUM_RX_DESC; i++) {
2587 + struct sk_buff *skb;
2588 +
2589 + skb = ramips_alloc_skb(re);
2590 + if (!skb)
2591 + goto err_cleanup;
2592 +
2593 + re->rx_info[i].rx_skb = skb;
2594 + }
2595 +
2596 + return 0;
2597 +
2598 +err_cleanup:
2599 + ramips_ring_free(re);
2600 + return err;
2601 +}
2602 +
2603 +static void
2604 +ramips_setup_dma(struct raeth_priv *re)
2605 +{
2606 + ramips_fe_twr(re->tx_desc_dma, RAETH_REG_TX_BASE_PTR0);
2607 + ramips_fe_twr(NUM_TX_DESC, RAETH_REG_TX_MAX_CNT0);
2608 + ramips_fe_twr(0, RAETH_REG_TX_CTX_IDX0);
2609 + ramips_fe_twr(RAMIPS_PST_DTX_IDX0, RAETH_REG_PDMA_RST_CFG);
2610 +
2611 + ramips_fe_twr(re->rx_desc_dma, RAETH_REG_RX_BASE_PTR0);
2612 + ramips_fe_twr(NUM_RX_DESC, RAETH_REG_RX_MAX_CNT0);
2613 + ramips_fe_twr((NUM_RX_DESC - 1), RAETH_REG_RX_CALC_IDX0);
2614 + ramips_fe_twr(RAMIPS_PST_DRX_IDX0, RAETH_REG_PDMA_RST_CFG);
2615 +}
2616 +
2617 +static int
2618 +ramips_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
2619 +{
2620 + struct raeth_priv *re = netdev_priv(dev);
2621 + struct raeth_tx_info *txi, *txi_next;
2622 + struct ramips_tx_dma *txd, *txd_next;
2623 + unsigned long tx;
2624 + unsigned int tx_next;
2625 + dma_addr_t mapped_addr;
2626 +
2627 + if (re->min_pkt_len) {
2628 + if (skb->len < re->min_pkt_len) {
2629 + if (skb_padto(skb, re->min_pkt_len)) {
2630 + printk(KERN_ERR
2631 + "ramips_eth: skb_padto failed\n");
2632 + kfree_skb(skb);
2633 + return 0;
2634 + }
2635 + skb_put(skb, re->min_pkt_len - skb->len);
2636 + }
2637 + }
2638 +
2639 + dev->trans_start = jiffies;
2640 + mapped_addr = dma_map_single(&re->netdev->dev, skb->data, skb->len,
2641 + DMA_TO_DEVICE);
2642 +
2643 + spin_lock(&re->page_lock);
2644 + tx = ramips_fe_trr(RAETH_REG_TX_CTX_IDX0);
2645 + tx_next = (tx + 1) % NUM_TX_DESC;
2646 +
2647 + txi = &re->tx_info[tx];
2648 + txd = txi->tx_desc;
2649 + txi_next = &re->tx_info[tx_next];
2650 + txd_next = txi_next->tx_desc;
2651 +
2652 + if ((txi->tx_skb) || (txi_next->tx_skb) ||
2653 + !(txd->txd2 & TX_DMA_DONE) ||
2654 + !(txd_next->txd2 & TX_DMA_DONE))
2655 + goto out;
2656 +
2657 + txi->tx_skb = skb;
2658 +
2659 + txd->txd1 = (unsigned int) mapped_addr;
2660 + wmb();
2661 + txd->txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
2662 + dev->stats.tx_packets++;
2663 + dev->stats.tx_bytes += skb->len;
2664 + ramips_fe_twr(tx_next, RAETH_REG_TX_CTX_IDX0);
2665 + netdev_sent_queue(dev, skb->len);
2666 + spin_unlock(&re->page_lock);
2667 + return NETDEV_TX_OK;
2668 +
2669 + out:
2670 + spin_unlock(&re->page_lock);
2671 + dev->stats.tx_dropped++;
2672 + kfree_skb(skb);
2673 + return NETDEV_TX_OK;
2674 +}
2675 +
2676 +static void
2677 +ramips_eth_rx_hw(unsigned long ptr)
2678 +{
2679 + struct net_device *dev = (struct net_device *) ptr;
2680 + struct raeth_priv *re = netdev_priv(dev);
2681 + int rx;
2682 + int max_rx = 16;
2683 +
2684 + rx = ramips_fe_trr(RAETH_REG_RX_CALC_IDX0);
2685 +
2686 + while (max_rx) {
2687 + struct raeth_rx_info *rxi;
2688 + struct ramips_rx_dma *rxd;
2689 + struct sk_buff *rx_skb, *new_skb;
2690 + int pktlen;
2691 +
2692 + rx = (rx + 1) % NUM_RX_DESC;
2693 +
2694 + rxi = &re->rx_info[rx];
2695 + rxd = rxi->rx_desc;
2696 + if (!(rxd->rxd2 & RX_DMA_DONE))
2697 + break;
2698 +
2699 + rx_skb = rxi->rx_skb;
2700 + pktlen = RX_DMA_PLEN0(rxd->rxd2);
2701 +
2702 + new_skb = ramips_alloc_skb(re);
2703 + /* Reuse the buffer on allocation failures */
2704 + if (new_skb) {
2705 + dma_addr_t dma_addr;
2706 +
2707 + dma_unmap_single(&re->netdev->dev, rxi->rx_dma,
2708 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
2709 +
2710 + skb_put(rx_skb, pktlen);
2711 + rx_skb->dev = dev;
2712 + rx_skb->protocol = eth_type_trans(rx_skb, dev);
2713 + rx_skb->ip_summed = CHECKSUM_NONE;
2714 + dev->stats.rx_packets++;
2715 + dev->stats.rx_bytes += pktlen;
2716 + netif_rx(rx_skb);
2717 +
2718 + rxi->rx_skb = new_skb;
2719 +
2720 + dma_addr = dma_map_single(&re->netdev->dev,
2721 + new_skb->data,
2722 + MAX_RX_LENGTH,
2723 + DMA_FROM_DEVICE);
2724 + rxi->rx_dma = dma_addr;
2725 + rxd->rxd1 = (unsigned int) dma_addr;
2726 + wmb();
2727 + } else {
2728 + dev->stats.rx_dropped++;
2729 + }
2730 +
2731 + rxd->rxd2 = RX_DMA_LSO;
2732 + ramips_fe_twr(rx, RAETH_REG_RX_CALC_IDX0);
2733 + max_rx--;
2734 + }
2735 +
2736 + if (max_rx == 0)
2737 + tasklet_schedule(&re->rx_tasklet);
2738 + else
2739 + ramips_fe_int_enable(RX_DLY_INT);
2740 +}
2741 +
2742 +static void
2743 +ramips_eth_tx_housekeeping(unsigned long ptr)
2744 +{
2745 + struct net_device *dev = (struct net_device*)ptr;
2746 + struct raeth_priv *re = netdev_priv(dev);
2747 + unsigned int bytes_compl = 0, pkts_compl = 0;
2748 +
2749 + spin_lock(&re->page_lock);
2750 + while (1) {
2751 + struct raeth_tx_info *txi;
2752 + struct ramips_tx_dma *txd;
2753 +
2754 + txi = &re->tx_info[re->skb_free_idx];
2755 + txd = txi->tx_desc;
2756 +
2757 + if (!(txd->txd2 & TX_DMA_DONE) || !(txi->tx_skb))
2758 + break;
2759 +
2760 + pkts_compl++;
2761 + bytes_compl += txi->tx_skb->len;
2762 +
2763 + dev_kfree_skb_irq(txi->tx_skb);
2764 + txi->tx_skb = NULL;
2765 + re->skb_free_idx++;
2766 + if (re->skb_free_idx >= NUM_TX_DESC)
2767 + re->skb_free_idx = 0;
2768 + }
2769 + netdev_completed_queue(dev, pkts_compl, bytes_compl);
2770 + spin_unlock(&re->page_lock);
2771 +
2772 + ramips_fe_int_enable(TX_DLY_INT);
2773 +}
2774 +
2775 +static void
2776 +ramips_eth_timeout(struct net_device *dev)
2777 +{
2778 + struct raeth_priv *re = netdev_priv(dev);
2779 +
2780 + tasklet_schedule(&re->tx_housekeeping_tasklet);
2781 +}
2782 +
2783 +static irqreturn_t
2784 +ramips_eth_irq(int irq, void *dev)
2785 +{
2786 + struct raeth_priv *re = netdev_priv(dev);
2787 + unsigned int status;
2788 +
2789 + status = ramips_fe_trr(RAETH_REG_FE_INT_STATUS);
2790 + status &= ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2791 +
2792 + if (!status)
2793 + return IRQ_NONE;
2794 +
2795 + ramips_fe_twr(status, RAETH_REG_FE_INT_STATUS);
2796 +
2797 + if (status & RX_DLY_INT) {
2798 + ramips_fe_int_disable(RX_DLY_INT);
2799 + tasklet_schedule(&re->rx_tasklet);
2800 + }
2801 +
2802 + if (status & TX_DLY_INT) {
2803 + ramips_fe_int_disable(TX_DLY_INT);
2804 + tasklet_schedule(&re->tx_housekeeping_tasklet);
2805 + }
2806 +
2807 + raeth_debugfs_update_int_stats(re, status);
2808 +
2809 + return IRQ_HANDLED;
2810 +}
2811 +
2812 +static int
2813 +ramips_eth_hw_init(struct net_device *dev)
2814 +{
2815 + struct raeth_priv *re = netdev_priv(dev);
2816 + int err;
2817 +
2818 + err = request_irq(dev->irq, ramips_eth_irq, IRQF_DISABLED,
2819 + dev_name(re->parent), dev);
2820 + if (err)
2821 + return err;
2822 +
2823 + err = ramips_ring_alloc(re);
2824 + if (err)
2825 + goto err_free_irq;
2826 +
2827 + ramips_ring_setup(re);
2828 + ramips_hw_set_macaddr(dev->dev_addr);
2829 +
2830 + ramips_setup_dma(re);
2831 + ramips_fe_wr((ramips_fe_rr(RAMIPS_FE_GLO_CFG) &
2832 + ~(RAMIPS_US_CYC_CNT_MASK << RAMIPS_US_CYC_CNT_SHIFT)) |
2833 + ((re->sys_freq / RAMIPS_US_CYC_CNT_DIVISOR) << RAMIPS_US_CYC_CNT_SHIFT),
2834 + RAMIPS_FE_GLO_CFG);
2835 +
2836 + tasklet_init(&re->tx_housekeeping_tasklet, ramips_eth_tx_housekeeping,
2837 + (unsigned long)dev);
2838 + tasklet_init(&re->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev);
2839 +
2840 +
2841 + ramips_fe_twr(RAMIPS_DELAY_INIT, RAETH_REG_DLY_INT_CFG);
2842 + ramips_fe_twr(TX_DLY_INT | RX_DLY_INT, RAETH_REG_FE_INT_ENABLE);
2843 + if (soc_is_rt5350()) {
2844 + ramips_fe_wr(ramips_fe_rr(RT5350_SDM_CFG) &
2845 + ~(RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN | 0xffff),
2846 + RT5350_SDM_CFG);
2847 + } else {
2848 + ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) &
2849 + ~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff),
2850 + RAMIPS_GDMA1_FWD_CFG);
2851 + ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) &
2852 + ~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN),
2853 + RAMIPS_CDMA_CSG_CFG);
2854 + ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG);
2855 + }
2856 + ramips_fe_wr(1, RAMIPS_FE_RST_GL);
2857 + ramips_fe_wr(0, RAMIPS_FE_RST_GL);
2858 +
2859 + return 0;
2860 +
2861 +err_free_irq:
2862 + free_irq(dev->irq, dev);
2863 + return err;
2864 +}
2865 +
2866 +static int
2867 +ramips_eth_open(struct net_device *dev)
2868 +{
2869 + struct raeth_priv *re = netdev_priv(dev);
2870 +
2871 + ramips_fe_twr((ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) & 0xff) |
2872 + (RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN |
2873 + RAMIPS_TX_DMA_EN | RAMIPS_PDMA_SIZE_4DWORDS),
2874 + RAETH_REG_PDMA_GLO_CFG);
2875 + ramips_phy_start(re);
2876 + netif_start_queue(dev);
2877 + return 0;
2878 +}
2879 +
2880 +static int
2881 +ramips_eth_stop(struct net_device *dev)
2882 +{
2883 + struct raeth_priv *re = netdev_priv(dev);
2884 +
2885 + ramips_fe_twr(ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) &
2886 + ~(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | RAMIPS_TX_DMA_EN),
2887 + RAETH_REG_PDMA_GLO_CFG);
2888 +
2889 + netif_stop_queue(dev);
2890 + ramips_phy_stop(re);
2891 + RADEBUG("ramips_eth: stopped\n");
2892 + return 0;
2893 +}
2894 +
2895 +static int __init
2896 +ramips_eth_probe(struct net_device *dev)
2897 +{
2898 + struct raeth_priv *re = netdev_priv(dev);
2899 + int err;
2900 +
2901 + BUG_ON(!re->reset_fe);
2902 + re->reset_fe();
2903 + net_srandom(jiffies);
2904 + memcpy(dev->dev_addr, re->mac, ETH_ALEN);
2905 + of_get_mac_address_mtd(re->of_node, dev->dev_addr);
2906 + ether_setup(dev);
2907 + dev->mtu = 1500;
2908 + dev->watchdog_timeo = TX_TIMEOUT;
2909 + spin_lock_init(&re->page_lock);
2910 + spin_lock_init(&re->phy_lock);
2911 +
2912 + err = ramips_mdio_init(re);
2913 + if (err)
2914 + return err;
2915 +
2916 + err = ramips_phy_connect(re);
2917 + if (err)
2918 + goto err_mdio_cleanup;
2919 +
2920 + err = raeth_debugfs_init(re);
2921 + if (err)
2922 + goto err_phy_disconnect;
2923 +
2924 + err = ramips_eth_hw_init(dev);
2925 + if (err)
2926 + goto err_debugfs;
2927 +
2928 + return 0;
2929 +
2930 +err_debugfs:
2931 + raeth_debugfs_exit(re);
2932 +err_phy_disconnect:
2933 + ramips_phy_disconnect(re);
2934 +err_mdio_cleanup:
2935 + ramips_mdio_cleanup(re);
2936 + return err;
2937 +}
2938 +
2939 +static void
2940 +ramips_eth_uninit(struct net_device *dev)
2941 +{
2942 + struct raeth_priv *re = netdev_priv(dev);
2943 +
2944 + raeth_debugfs_exit(re);
2945 + ramips_phy_disconnect(re);
2946 + ramips_mdio_cleanup(re);
2947 + ramips_fe_twr(0, RAETH_REG_FE_INT_ENABLE);
2948 + free_irq(dev->irq, dev);
2949 + tasklet_kill(&re->tx_housekeeping_tasklet);
2950 + tasklet_kill(&re->rx_tasklet);
2951 + ramips_ring_cleanup(re);
2952 + ramips_ring_free(re);
2953 +}
2954 +
2955 +static const struct net_device_ops ramips_eth_netdev_ops = {
2956 + .ndo_init = ramips_eth_probe,
2957 + .ndo_uninit = ramips_eth_uninit,
2958 + .ndo_open = ramips_eth_open,
2959 + .ndo_stop = ramips_eth_stop,
2960 + .ndo_start_xmit = ramips_eth_hard_start_xmit,
2961 + .ndo_tx_timeout = ramips_eth_timeout,
2962 + .ndo_change_mtu = eth_change_mtu,
2963 + .ndo_set_mac_address = eth_mac_addr,
2964 + .ndo_validate_addr = eth_validate_addr,
2965 +};
2966 +
2967 +#ifdef CONFIG_SOC_RT305X
2968 +static void rt305x_fe_reset(void)
2969 +{
2970 +#define RT305X_RESET_FE BIT(21)
2971 +#define RT305X_RESET_ESW BIT(23)
2972 +#define SYSC_REG_RESET_CTRL 0x034
2973 + u32 reset_bits = RT305X_RESET_FE;
2974 +
2975 + if (soc_is_rt5350())
2976 + reset_bits |= RT305X_RESET_ESW;
2977 + rt_sysc_w32(reset_bits, SYSC_REG_RESET_CTRL);
2978 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
2979 +}
2980 +
2981 +struct ramips_soc_data rt3050_data = {
2982 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
2983 + .reset_fe = rt305x_fe_reset,
2984 + .min_pkt_len = 64,
2985 +};
2986 +
2987 +static const struct of_device_id ralink_eth_match[] = {
2988 + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
2989 + {},
2990 +};
2991 +#else
2992 +static void rt3883_fe_reset(void)
2993 +{
2994 +#define RT3883_SYSC_REG_RSTCTRL 0x34
2995 +#define RT3883_RSTCTRL_FE BIT(21)
2996 + u32 t;
2997 +
2998 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
2999 + t |= RT3883_RSTCTRL_FE;
3000 + rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
3001 +
3002 + t &= ~RT3883_RSTCTRL_FE;
3003 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
3004 +}
3005 +
3006 +struct ramips_soc_data rt3883_data = {
3007 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
3008 + .reset_fe = rt3883_fe_reset,
3009 + .min_pkt_len = 64,
3010 +};
3011 +
3012 +static const struct of_device_id ralink_eth_match[] = {
3013 + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
3014 + {},
3015 +};
3016 +#endif
3017 +MODULE_DEVICE_TABLE(of, ralink_eth_match);
3018 +
3019 +static int
3020 +ramips_eth_plat_probe(struct platform_device *plat)
3021 +{
3022 + struct raeth_priv *re;
3023 + struct resource *res;
3024 + struct clk *clk;
3025 + int err;
3026 + const struct of_device_id *match;
3027 + const struct ramips_soc_data *soc = NULL;
3028 +
3029 + match = of_match_device(ralink_eth_match, &plat->dev);
3030 + if (match)
3031 + soc = (const struct ramips_soc_data *) match->data;
3032 +
3033 + if (!soc) {
3034 + dev_err(&plat->dev, "no platform data specified\n");
3035 + return -EINVAL;
3036 + }
3037 +
3038 + res = platform_get_resource(plat, IORESOURCE_MEM, 0);
3039 + if (!res) {
3040 + dev_err(&plat->dev, "no memory resource found\n");
3041 + return -ENXIO;
3042 + }
3043 +
3044 + ramips_fe_base = ioremap_nocache(res->start, res->end - res->start + 1);
3045 + if (!ramips_fe_base)
3046 + return -ENOMEM;
3047 +
3048 + ramips_dev = alloc_etherdev(sizeof(struct raeth_priv));
3049 + if (!ramips_dev) {
3050 + dev_err(&plat->dev, "alloc_etherdev failed\n");
3051 + err = -ENOMEM;
3052 + goto err_unmap;
3053 + }
3054 +
3055 + strcpy(ramips_dev->name, "eth%d");
3056 + ramips_dev->irq = platform_get_irq(plat, 0);
3057 + if (ramips_dev->irq < 0) {
3058 + dev_err(&plat->dev, "no IRQ resource found\n");
3059 + err = -ENXIO;
3060 + goto err_free_dev;
3061 + }
3062 + ramips_dev->addr_len = ETH_ALEN;
3063 + ramips_dev->base_addr = (unsigned long)ramips_fe_base;
3064 + ramips_dev->netdev_ops = &ramips_eth_netdev_ops;
3065 +
3066 + re = netdev_priv(ramips_dev);
3067 +
3068 + clk = clk_get(&plat->dev, NULL);
3069 + if (IS_ERR(clk))
3070 + panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
3071 + re->sys_freq = clk_get_rate(clk);
3072 +
3073 + re->netdev = ramips_dev;
3074 + re->of_node = plat->dev.of_node;
3075 + re->parent = &plat->dev;
3076 + memcpy(re->mac, soc->mac, 6);
3077 + re->reset_fe = soc->reset_fe;
3078 + re->min_pkt_len = soc->min_pkt_len;
3079 +
3080 + err = register_netdev(ramips_dev);
3081 + if (err) {
3082 + dev_err(&plat->dev, "error bringing up device\n");
3083 + goto err_free_dev;
3084 + }
3085 +
3086 + netdev_info(ramips_dev, "done loading\n");
3087 + return 0;
3088 +
3089 + err_free_dev:
3090 + kfree(ramips_dev);
3091 + err_unmap:
3092 + iounmap(ramips_fe_base);
3093 + return err;
3094 +}
3095 +
3096 +static int
3097 +ramips_eth_plat_remove(struct platform_device *plat)
3098 +{
3099 + unregister_netdev(ramips_dev);
3100 + free_netdev(ramips_dev);
3101 + RADEBUG("ramips_eth: unloaded\n");
3102 + return 0;
3103 +}
3104 +
3105 +
3106 +
3107 +static struct platform_driver ramips_eth_driver = {
3108 + .probe = ramips_eth_plat_probe,
3109 + .remove = ramips_eth_plat_remove,
3110 + .driver = {
3111 + .name = "ramips_eth",
3112 + .owner = THIS_MODULE,
3113 + .of_match_table = ralink_eth_match
3114 + },
3115 +};
3116 +
3117 +static int __init
3118 +ramips_eth_init(void)
3119 +{
3120 + int ret;
3121 +
3122 + ret = raeth_debugfs_root_init();
3123 + if (ret)
3124 + goto err_out;
3125 +
3126 + ret = rt305x_esw_init();
3127 + if (ret)
3128 + goto err_debugfs_exit;
3129 +
3130 + ret = platform_driver_register(&ramips_eth_driver);
3131 + if (ret) {
3132 + printk(KERN_ERR
3133 + "ramips_eth: Error registering platfom driver!\n");
3134 + goto esw_cleanup;
3135 + }
3136 +
3137 + return 0;
3138 +
3139 +esw_cleanup:
3140 + rt305x_esw_exit();
3141 +err_debugfs_exit:
3142 + raeth_debugfs_root_exit();
3143 +err_out:
3144 + return ret;
3145 +}
3146 +
3147 +static void __exit
3148 +ramips_eth_cleanup(void)
3149 +{
3150 + platform_driver_unregister(&ramips_eth_driver);
3151 + rt305x_esw_exit();
3152 + raeth_debugfs_root_exit();
3153 +}
3154 +
3155 +module_init(ramips_eth_init);
3156 +module_exit(ramips_eth_cleanup);
3157 +
3158 +MODULE_LICENSE("GPL");
3159 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3160 +MODULE_DESCRIPTION("ethernet driver for ramips boards");
Staging tree of Christian Lamparter