1 From 007ab7fe49bfcaa220372260eedeb4eed51f1631 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 22 Jan 2013 18:24:34 +0100
4 Subject: [PATCH 130/137] GPIO: MIPS: ralink: adds ralink gpio support
6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/Kconfig | 1 +
12 arch/mips/include/asm/mach-ralink/gpio.h | 24 ++++
13 drivers/gpio/Kconfig | 6 +
14 drivers/gpio/Makefile | 1 +
15 drivers/gpio/gpio-ralink.c | 176 ++++++++++++++++++++++++++++++
16 5 files changed, 208 insertions(+)
17 create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
18 create mode 100644 drivers/gpio/gpio-ralink.c
20 --- a/arch/mips/Kconfig
21 +++ b/arch/mips/Kconfig
22 @@ -449,6 +449,7 @@ config RALINK
23 select SYS_HAS_EARLY_PRINTK
24 select HAVE_MACH_CLKDEV
26 + select ARCH_REQUIRE_GPIOLIB
29 bool "SGI IP22 (Indy/Indigo2)"
31 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
34 + * Ralink SoC GPIO API support
36 + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
37 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
39 + * This program is free software; you can redistribute it and/or modify it
40 + * under the terms of the GNU General Public License version 2 as published
41 + * by the Free Software Foundation.
45 +#ifndef __ASM_MACH_RALINK_GPIO_H
46 +#define __ASM_MACH_RALINK_GPIO_H
48 +#define ARCH_NR_GPIOS 128
49 +#include <asm-generic/gpio.h>
51 +#define gpio_get_value __gpio_get_value
52 +#define gpio_set_value __gpio_set_value
53 +#define gpio_cansleep __gpio_cansleep
54 +#define gpio_to_irq __gpio_to_irq
56 +#endif /* __ASM_MACH_RALINK_GPIO_H */
57 --- a/drivers/gpio/Kconfig
58 +++ b/drivers/gpio/Kconfig
59 @@ -201,6 +201,12 @@ config GPIO_PXA
61 Say yes here to support the PXA GPIO device
64 + bool "Ralink GPIO Support"
67 + Say yes here to support the Ralink SoC GPIO device
69 config GPIO_SPEAR_SPICS
70 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
72 --- a/drivers/gpio/Makefile
73 +++ b/drivers/gpio/Makefile
74 @@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf85
75 obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
76 obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
77 obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
78 +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
79 obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
80 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
81 obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
83 +++ b/drivers/gpio/gpio-ralink.c
86 + * This program is free software; you can redistribute it and/or modify it
87 + * under the terms of the GNU General Public License version 2 as published
88 + * by the Free Software Foundation.
90 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
91 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
94 +#include <linux/module.h>
95 +#include <linux/io.h>
96 +#include <linux/gpio.h>
97 +#include <linux/spinlock.h>
98 +#include <linux/platform_device.h>
100 +enum ralink_gpio_reg {
114 +struct ralink_gpio_chip {
115 + struct gpio_chip chip;
116 + u8 regs[GPIO_REG_MAX];
119 + void __iomem *membase;
122 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
124 + struct ralink_gpio_chip *rg;
126 + rg = container_of(chip, struct ralink_gpio_chip, chip);
130 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
132 + iowrite32(val, rg->membase + rg->regs[reg]);
135 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
137 + return ioread32(rg->membase + rg->regs[reg]);
140 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
142 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
144 + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
147 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
149 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
151 + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
154 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
156 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
157 + unsigned long flags;
160 + spin_lock_irqsave(&rg->lock, flags);
161 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
163 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
164 + spin_unlock_irqrestore(&rg->lock, flags);
169 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
170 + unsigned offset, int value)
172 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
173 + unsigned long flags;
176 + spin_lock_irqsave(&rg->lock, flags);
177 + ralink_gpio_set(chip, offset, value);
178 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
180 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
181 + spin_unlock_irqrestore(&rg->lock, flags);
186 +static int ralink_gpio_probe(struct platform_device *pdev)
188 + struct device_node *np = pdev->dev.of_node;
189 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
190 + struct ralink_gpio_chip *gc;
191 + const __be32 *ngpio;
192 + const __be32 *gpiobase;
195 + dev_err(&pdev->dev, "failed to find resource\n");
199 + gc = devm_kzalloc(&pdev->dev,
200 + sizeof(struct ralink_gpio_chip), GFP_KERNEL);
204 + gc->membase = devm_request_and_ioremap(&pdev->dev, res);
205 + if (!gc->membase) {
206 + dev_err(&pdev->dev, "cannot remap I/O memory region\n");
210 + if (of_property_read_u8_array(np, "ralink,register-map",
211 + gc->regs, GPIO_REG_MAX)) {
212 + dev_err(&pdev->dev, "failed to read register definition\n");
216 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
218 + dev_err(&pdev->dev, "failed to read number of pins\n");
222 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
224 + gc->chip.base = be32_to_cpu(*gpiobase);
226 + gc->chip.base = -1;
228 + gc->chip.label = dev_name(&pdev->dev);
229 + gc->chip.of_node = np;
230 + gc->chip.ngpio = be32_to_cpu(*ngpio);
231 + gc->chip.direction_input = ralink_gpio_direction_input;
232 + gc->chip.direction_output = ralink_gpio_direction_output;
233 + gc->chip.get = ralink_gpio_get;
234 + gc->chip.set = ralink_gpio_set;
236 + spin_lock_init(&gc->lock);
238 + /* set polarity to low for all lines */
239 + rt_gpio_w32(gc, GPIO_REG_POL, 0);
241 + dev_info(&pdev->dev, "registering %d gpios\n", gc->chip.ngpio);
243 + return gpiochip_add(&gc->chip);
246 +static const struct of_device_id ralink_gpio_match[] = {
247 + { .compatible = "ralink,rt2880-gpio" },
250 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
252 +static struct platform_driver ralink_gpio_driver = {
253 + .probe = ralink_gpio_probe,
255 + .name = "rt2880_gpio",
256 + .owner = THIS_MODULE,
257 + .of_match_table = ralink_gpio_match,
261 +static int __init ralink_gpio_init(void)
263 + return platform_driver_register(&ralink_gpio_driver);
266 +subsys_initcall(ralink_gpio_init);