1 From 32c1cff4c75925a0bbd305e85ed4adb30140cd42 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:16:18 +0200
4 Subject: [PATCH 131/137] SPI: ralink: add Ralink SoC spi driver
6 Add the driver needed to make SPI work on Ralink SoC.
8 Signed-off-by: John Crispin <blogic@openwrt.org>
10 drivers/spi/Kconfig | 6 +
11 drivers/spi/Makefile | 1 +
12 drivers/spi/spi-ralink.c | 472 ++++++++++++++++++++++++++++++++++++++++++++++
13 3 files changed, 479 insertions(+)
14 create mode 100644 drivers/spi/spi-ralink.c
16 --- a/drivers/spi/Kconfig
17 +++ b/drivers/spi/Kconfig
18 @@ -324,6 +324,12 @@ config SPI_RSPI
20 SPI driver for Renesas RSPI blocks.
23 + tristate "Ralink RT288x/RT305x/RT3662 SPI Controller"
24 + depends on (SOC_RT288X || SOC_RT305X || SOC_RT3883)
26 + This selects a driver for the Ralink RT288x/RT305x SPI Controller.
29 tristate "Samsung S3C24XX series SPI"
30 depends on ARCH_S3C24XX && EXPERIMENTAL
31 --- a/drivers/spi/Makefile
32 +++ b/drivers/spi/Makefile
33 @@ -51,6 +51,7 @@ obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.
34 obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o
35 obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
36 obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
37 +obj-$(CONFIG_SPI_RALINK) += spi-ralink.o
38 obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
39 spi-s3c24xx-hw-y := spi-s3c24xx.o
40 spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
42 +++ b/drivers/spi/spi-ralink.c
45 + * spi-ralink.c -- Ralink RT288x/RT305x SPI controller driver
47 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
48 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
50 + * Some parts are based on spi-orion.c:
51 + * Author: Shadi Ammouri <shadi@marvell.com>
52 + * Copyright (C) 2007-2008 Marvell Ltd.
54 + * This program is free software; you can redistribute it and/or modify
55 + * it under the terms of the GNU General Public License version 2 as
56 + * published by the Free Software Foundation.
59 +#include <linux/init.h>
60 +#include <linux/module.h>
61 +#include <linux/clk.h>
62 +#include <linux/err.h>
63 +#include <linux/delay.h>
64 +#include <linux/platform_device.h>
65 +#include <linux/io.h>
66 +#include <linux/spi/spi.h>
68 +#define DRIVER_NAME "spi-ralink"
69 +#define RALINK_NUM_CHIPSELECTS 1 /* only one slave is supported*/
70 +#define RALINK_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
72 +#define RAMIPS_SPI_STAT 0x00
73 +#define RAMIPS_SPI_CFG 0x10
74 +#define RAMIPS_SPI_CTL 0x14
75 +#define RAMIPS_SPI_DATA 0x20
77 +/* SPISTAT register bit field */
78 +#define SPISTAT_BUSY BIT(0)
80 +/* SPICFG register bit field */
81 +#define SPICFG_LSBFIRST 0
82 +#define SPICFG_MSBFIRST BIT(8)
83 +#define SPICFG_SPICLKPOL BIT(6)
84 +#define SPICFG_RXCLKEDGE_FALLING BIT(5)
85 +#define SPICFG_TXCLKEDGE_FALLING BIT(4)
86 +#define SPICFG_SPICLK_PRESCALE_MASK 0x7
87 +#define SPICFG_SPICLK_DIV2 0
88 +#define SPICFG_SPICLK_DIV4 1
89 +#define SPICFG_SPICLK_DIV8 2
90 +#define SPICFG_SPICLK_DIV16 3
91 +#define SPICFG_SPICLK_DIV32 4
92 +#define SPICFG_SPICLK_DIV64 5
93 +#define SPICFG_SPICLK_DIV128 6
94 +#define SPICFG_SPICLK_DISABLE 7
96 +/* SPICTL register bit field */
97 +#define SPICTL_HIZSDO BIT(3)
98 +#define SPICTL_STARTWR BIT(2)
99 +#define SPICTL_STARTRD BIT(1)
100 +#define SPICTL_SPIENA BIT(0)
103 +#define spi_debug(args...) printk(args)
105 +#define spi_debug(args...)
109 + struct spi_master *master;
110 + void __iomem *base;
111 + unsigned int sys_freq;
112 + unsigned int speed;
116 +static inline struct ralink_spi *spidev_to_ralink_spi(struct spi_device *spi)
118 + return spi_master_get_devdata(spi->master);
121 +static inline u32 ralink_spi_read(struct ralink_spi *rs, u32 reg)
123 + return ioread32(rs->base + reg);
126 +static inline void ralink_spi_write(struct ralink_spi *rs, u32 reg, u32 val)
128 + iowrite32(val, rs->base + reg);
131 +static inline void ralink_spi_setbits(struct ralink_spi *rs, u32 reg, u32 mask)
133 + void __iomem *addr = rs->base + reg;
136 + val = ioread32(addr);
138 + iowrite32(val, addr);
141 +static inline void ralink_spi_clrbits(struct ralink_spi *rs, u32 reg, u32 mask)
143 + void __iomem *addr = rs->base + reg;
146 + val = ioread32(addr);
148 + iowrite32(val, addr);
151 +static int ralink_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
153 + struct ralink_spi *rs = spidev_to_ralink_spi(spi);
158 + spi_debug("%s: speed:%u\n", __func__, speed);
161 + * the supported rates are: 2, 4, 8, ... 128
162 + * round up as we look for equal or less speed
164 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
165 + spi_debug("%s: rate-1:%u\n", __func__, rate);
166 + rate = roundup_pow_of_two(rate);
167 + spi_debug("%s: rate-2:%u\n", __func__, rate);
169 + /* check if requested speed is too small */
176 + /* Convert the rate to SPI clock divisor value. */
177 + prescale = ilog2(rate/2);
178 + spi_debug("%s: prescale:%u\n", __func__, prescale);
180 + reg = ralink_spi_read(rs, RAMIPS_SPI_CFG);
181 + reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
182 + ralink_spi_write(rs, RAMIPS_SPI_CFG, reg);
188 + * called only when no transfer is active on the bus
191 +ralink_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
193 + struct ralink_spi *rs = spidev_to_ralink_spi(spi);
194 + unsigned int speed = spi->max_speed_hz;
196 + unsigned int bits_per_word = 8;
198 + if ((t != NULL) && t->speed_hz)
199 + speed = t->speed_hz;
201 + if ((t != NULL) && t->bits_per_word)
202 + bits_per_word = t->bits_per_word;
204 + if (rs->speed != speed) {
205 + spi_debug("%s: speed_hz:%u\n", __func__, speed);
206 + rc = ralink_spi_baudrate_set(spi, speed);
211 + if (bits_per_word != 8) {
212 + spi_debug("%s: bad bits_per_word: %u\n", __func__,
220 +static void ralink_spi_set_cs(struct ralink_spi *rs, int enable)
223 + ralink_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
225 + ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
228 +static inline int ralink_spi_wait_till_ready(struct ralink_spi *rs)
232 + for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) {
235 + status = ralink_spi_read(rs, RAMIPS_SPI_STAT);
236 + if ((status & SPISTAT_BUSY) == 0)
246 +ralink_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
248 + struct ralink_spi *rs = spidev_to_ralink_spi(spi);
249 + unsigned count = 0;
250 + u8 *rx = xfer->rx_buf;
251 + const u8 *tx = xfer->tx_buf;
254 + spi_debug("%s(%d): %s %s\n", __func__, xfer->len,
255 + (tx != NULL) ? "tx" : " ",
256 + (rx != NULL) ? "rx" : " ");
259 + for (count = 0; count < xfer->len; count++) {
260 + ralink_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
261 + ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
262 + err = ralink_spi_wait_till_ready(rs);
264 + dev_err(&spi->dev, "TX failed, err=%d\n", err);
271 + for (count = 0; count < xfer->len; count++) {
272 + ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
273 + err = ralink_spi_wait_till_ready(rs);
275 + dev_err(&spi->dev, "RX failed, err=%d\n", err);
278 + rx[count] = (u8) ralink_spi_read(rs, RAMIPS_SPI_DATA);
286 +static int ralink_spi_transfer_one_message(struct spi_master *master,
287 + struct spi_message *m)
289 + struct ralink_spi *rs = spi_master_get_devdata(master);
290 + struct spi_device *spi = m->spi;
291 + struct spi_transfer *t = NULL;
292 + int par_override = 0;
296 + /* Load defaults */
297 + status = ralink_spi_setup_transfer(spi, NULL);
301 + list_for_each_entry(t, &m->transfers, transfer_list) {
302 + unsigned int bits_per_word = spi->bits_per_word;
304 + if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
306 + "message rejected: invalid transfer data buffers\n");
311 + if (t->bits_per_word)
312 + bits_per_word = t->bits_per_word;
314 + if (bits_per_word != 8) {
316 + "message rejected: invalid transfer bits_per_word (%d bits)\n",
322 + if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
324 + "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
325 + (rs->sys_freq / 128), t->speed_hz);
330 + if (par_override || t->speed_hz || t->bits_per_word) {
332 + status = ralink_spi_setup_transfer(spi, t);
335 + if (!t->speed_hz && !t->bits_per_word)
340 + ralink_spi_set_cs(rs, 1);
345 + m->actual_length += ralink_spi_write_read(spi, t);
347 + if (t->delay_usecs)
348 + udelay(t->delay_usecs);
350 + if (t->cs_change) {
351 + ralink_spi_set_cs(rs, 0);
358 + ralink_spi_set_cs(rs, 0);
360 + m->status = status;
361 + spi_finalize_current_message(master);
366 +static int ralink_spi_setup(struct spi_device *spi)
368 + struct ralink_spi *rs = spidev_to_ralink_spi(spi);
370 + if ((spi->max_speed_hz == 0) ||
371 + (spi->max_speed_hz > (rs->sys_freq / 2)))
372 + spi->max_speed_hz = (rs->sys_freq / 2);
374 + if (spi->max_speed_hz < (rs->sys_freq / 128)) {
375 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
376 + spi->max_speed_hz);
380 + if (spi->bits_per_word != 0 && spi->bits_per_word != 8) {
382 + "setup: requested bits per words - os wrong %d bpw\n",
383 + spi->bits_per_word);
387 + if (spi->bits_per_word == 0)
388 + spi->bits_per_word = 8;
391 + * baudrate & width will be set ralink_spi_setup_transfer
396 +static void ralink_spi_reset(struct ralink_spi *rs)
398 + ralink_spi_write(rs, RAMIPS_SPI_CFG,
399 + SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
400 + SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
401 + ralink_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
404 +static int ralink_spi_probe(struct platform_device *pdev)
406 + struct spi_master *master;
407 + struct ralink_spi *rs;
408 + struct resource *r;
411 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
412 + if (master == NULL) {
413 + dev_dbg(&pdev->dev, "master allocation failed\n");
417 + //if (pdev->id != -1)
418 + master->bus_num = 0;
420 + /* we support only mode 0, and no options */
421 + master->mode_bits = 0;
423 + master->setup = ralink_spi_setup;
424 + master->transfer_one_message = ralink_spi_transfer_one_message;
425 + master->num_chipselect = RALINK_NUM_CHIPSELECTS;
426 + master->dev.of_node = pdev->dev.of_node;
428 + dev_set_drvdata(&pdev->dev, master);
430 + rs = spi_master_get_devdata(master);
431 + rs->master = master;
433 + rs->clk = clk_get(&pdev->dev, NULL);
434 + if (IS_ERR(rs->clk)) {
435 + status = PTR_ERR(rs->clk);
436 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
438 + goto out_put_master;
441 + status = clk_enable(rs->clk);
445 + rs->sys_freq = clk_get_rate(rs->clk);
446 + spi_debug("%s: sys_freq: %u\n", __func__, rs->sys_freq);
448 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
451 + goto out_disable_clk;
454 + rs->base = devm_request_and_ioremap(&pdev->dev, r);
456 + status = -EADDRNOTAVAIL;
457 + goto out_disable_clk;
460 + ralink_spi_reset(rs);
462 + status = spi_register_master(master);
464 + goto out_disable_clk;
469 + clk_disable(rs->clk);
473 + spi_master_put(master);
477 +static int ralink_spi_remove(struct platform_device *pdev)
479 + struct spi_master *master;
480 + struct ralink_spi *rs;
482 + master = dev_get_drvdata(&pdev->dev);
483 + rs = spi_master_get_devdata(master);
485 + clk_disable(rs->clk);
487 + spi_unregister_master(master);
492 +MODULE_ALIAS("platform:" DRIVER_NAME);
494 +static const struct of_device_id ralink_spi_match[] = {
495 + { .compatible = "ralink,rt2880-spi" },
498 +MODULE_DEVICE_TABLE(of, ralink_spi_match);
500 +static struct platform_driver ralink_spi_driver = {
502 + .name = DRIVER_NAME,
503 + .owner = THIS_MODULE,
504 + .of_match_table = ralink_spi_match,
506 + .probe = ralink_spi_probe,
507 + .remove = ralink_spi_remove,
510 +module_platform_driver(ralink_spi_driver);
512 +MODULE_DESCRIPTION("Ralink SPI driver");
513 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
514 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
515 +MODULE_LICENSE("GPL");