target/linux/ramips/patches-3.8/0204-owrt-MIPS-ralink-add-usb-platform-support.patch

   1 From d7e679017ec92824145b275572f6ef83d461f076 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 19 Mar 2013 09:26:22 +0100
   4 Subject: [PATCH 204/208] owrt: MIPS: ralink: add usb platform support
   5
   6 Add code to load the platform ehci/ohci driver on Ralink SoC. For the usb core
   7 to work we need to populate the platform_data during boot, prior to the usb
   8 driver being loaded.
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 ---
  12  arch/mips/ralink/Makefile     |    4 +-
  13  arch/mips/ralink/common.h     |    1 +
  14  arch/mips/ralink/mt7620.c     |    5 ++
  15  arch/mips/ralink/of.c         |    1 +
  16  arch/mips/ralink/rt305x-usb.c |  120 +++++++++++++++++++++++++++++++++++++++++
  17  arch/mips/ralink/rt3883-usb.c |  118 ++++++++++++++++++++++++++++++++++++++++
  18  6 files changed, 247 insertions(+), 2 deletions(-)
  19  create mode 100644 arch/mips/ralink/rt305x-usb.c
  20  create mode 100644 arch/mips/ralink/rt3883-usb.c
  21
  22 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
  23 index cae7d88..8572538 100644
  24 --- a/arch/mips/ralink/Makefile
  25 +++ b/arch/mips/ralink/Makefile
  26 @@ -9,8 +9,8 @@
  27  obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
  28
  29  obj-$(CONFIG_SOC_RT288X) += rt288x.o
  30 -obj-$(CONFIG_SOC_RT305X) += rt305x.o
  31 -obj-$(CONFIG_SOC_RT3883) += rt3883.o
  32 +obj-$(CONFIG_SOC_RT305X) += rt305x.o rt305x-usb.o
  33 +obj-$(CONFIG_SOC_RT3883) += rt3883.o rt3883-usb.o
  34  obj-$(CONFIG_SOC_MT7620) += mt7620.o
  35
  36  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
  37 diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
  38 index ed99f23..14a101c 100644
  39 --- a/arch/mips/ralink/common.h
  40 +++ b/arch/mips/ralink/common.h
  41 @@ -43,5 +43,6 @@ extern void prom_soc_init(struct ralink_soc_info *soc_info);
  42  __iomem void *plat_of_remap_node(const char *node);
  43
  44  void ralink_pinmux(void);
  45 +void ralink_usb_platform(void);
  46
  47  #endif /* _RALINK_COMMON_H__ */
  48 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
  49 index 9d0dc8b..19b28c5 100644
  50 --- a/arch/mips/ralink/mt7620.c
  51 +++ b/arch/mips/ralink/mt7620.c
  52 @@ -146,6 +146,11 @@ struct ralink_pinmux rt_pinmux = {
  53  //     .wdt_reset = rt305x_wdt_reset,
  54  };
  55
  56 +void ralink_usb_platform(void)
  57 +{
  58 +
  59 +}
  60 +
  61  void __init ralink_clk_init(void)
  62  {
  63         unsigned long cpu_rate, sys_rate;
  64 diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
  65 index ecf1482..f438145 100644
  66 --- a/arch/mips/ralink/of.c
  67 +++ b/arch/mips/ralink/of.c
  68 @@ -102,6 +102,7 @@ static int __init plat_of_setup(void)
  69                 panic("failed to populate DT\n");
  70
  71         ralink_pinmux();
  72 +       ralink_usb_platform();
  73
  74         return 0;
  75  }
  76 diff --git a/arch/mips/ralink/rt305x-usb.c b/arch/mips/ralink/rt305x-usb.c
  77 new file mode 100644
  78 index 0000000..793fc82
  79 --- /dev/null
  80 +++ b/arch/mips/ralink/rt305x-usb.c
  81 @@ -0,0 +1,120 @@
  82 +/*
  83 + * This program is free software; you can redistribute it and/or modify it
  84 + * under the terms of the GNU General Public License version 2 as published
  85 + * by the Free Software Foundation.
  86 + *
  87 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  88 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  89 + */
  90 +
  91 +#include <linux/kernel.h>
  92 +#include <linux/init.h>
  93 +#include <linux/module.h>
  94 +
  95 +#include <linux/delay.h>
  96 +#include <linux/of_platform.h>
  97 +#include <linux/dma-mapping.h>
  98 +#include <linux/usb/ehci_pdriver.h>
  99 +#include <linux/usb/ohci_pdriver.h>
 100 +
 101 +#include <asm/mach-ralink/ralink_regs.h>
 102 +#include <asm/mach-ralink/rt305x.h>
 103 +
 104 +static atomic_t rt3352_usb_pwr_ref = ATOMIC_INIT(0);
 105 +
 106 +static int rt3352_usb_power_on(struct platform_device *pdev)
 107 +{
 108 +
 109 +       if (atomic_inc_return(&rt3352_usb_pwr_ref) == 1) {
 110 +               u32 t;
 111 +
 112 +               t = rt_sysc_r32(RT3352_SYSC_REG_USB_PS);
 113 +
 114 +               /* enable clock for port0's and port1's phys */
 115 +               t = rt_sysc_r32(RT3352_SYSC_REG_CLKCFG1);
 116 +               t |= RT3352_CLKCFG1_UPHY0_CLK_EN | RT3352_CLKCFG1_UPHY1_CLK_EN;
 117 +               rt_sysc_w32(t, RT3352_SYSC_REG_CLKCFG1);
 118 +               mdelay(500);
 119 +
 120 +               /* pull USBHOST and USBDEV out from reset */
 121 +               t = rt_sysc_r32(RT3352_SYSC_REG_RSTCTRL);
 122 +               t &= ~(RT3352_RSTCTRL_UHST | RT3352_RSTCTRL_UDEV);
 123 +               rt_sysc_w32(t, RT3352_SYSC_REG_RSTCTRL);
 124 +               mdelay(500);
 125 +
 126 +               /* enable host mode */
 127 +               t = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG1);
 128 +               t |= RT3352_SYSCFG1_USB0_HOST_MODE;
 129 +               rt_sysc_w32(t, RT3352_SYSC_REG_SYSCFG1);
 130 +
 131 +               t = rt_sysc_r32(RT3352_SYSC_REG_USB_PS);
 132 +       }
 133 +
 134 +       return 0;
 135 +}
 136 +
 137 +static void rt3352_usb_power_off(struct platform_device *pdev)
 138 +{
 139 +       if (atomic_dec_return(&rt3352_usb_pwr_ref) == 0) {
 140 +               u32 t;
 141 +
 142 +               /* put USBHOST and USBDEV into reset */
 143 +               t = rt_sysc_r32(RT3352_SYSC_REG_RSTCTRL);
 144 +               t |= RT3352_RSTCTRL_UHST | RT3352_RSTCTRL_UDEV;
 145 +               rt_sysc_w32(t, RT3352_SYSC_REG_RSTCTRL);
 146 +               udelay(10000);
 147 +
 148 +               /* disable clock for port0's and port1's phys*/
 149 +               t = rt_sysc_r32(RT3352_SYSC_REG_CLKCFG1);
 150 +               t &= ~(RT3352_CLKCFG1_UPHY0_CLK_EN | RT3352_CLKCFG1_UPHY1_CLK_EN);
 151 +               rt_sysc_w32(t, RT3352_SYSC_REG_CLKCFG1);
 152 +               udelay(10000);
 153 +       }
 154 +}
 155 +
 156 +static struct usb_ehci_pdata rt3352_ehci_data = {
 157 +       .power_on       = rt3352_usb_power_on,
 158 +       .power_off      = rt3352_usb_power_off,
 159 +};
 160 +
 161 +static struct usb_ohci_pdata rt3352_ohci_data = {
 162 +       .power_on       = rt3352_usb_power_on,
 163 +       .power_off      = rt3352_usb_power_off,
 164 +};
 165 +
 166 +static void ralink_add_usb(char *name, void *pdata, u64 *mask)
 167 +{
 168 +       struct device_node *node;
 169 +       struct platform_device *pdev;
 170 +
 171 +       node = of_find_compatible_node(NULL, NULL, name);
 172 +       if (!node)
 173 +               return;
 174 +
 175 +       pdev = of_find_device_by_node(node);
 176 +       if (!pdev)
 177 +               goto error_out;
 178 +
 179 +       if (pdata)
 180 +               pdev->dev.platform_data = pdata;
 181 +       if (mask) {
 182 +               pdev->dev.dma_mask = mask;
 183 +               pdev->dev.coherent_dma_mask = *mask;
 184 +       }
 185 +
 186 +error_out:
 187 +       of_node_put(node);
 188 +}
 189 +
 190 +static u64 rt3352_ohci_dmamask = DMA_BIT_MASK(32);
 191 +static u64 rt3352_ehci_dmamask = DMA_BIT_MASK(32);
 192 +
 193 +void ralink_usb_platform(void)
 194 +{
 195 +       if (soc_is_rt3352() || soc_is_rt5350()) {
 196 +               ralink_add_usb("ohci-platform",
 197 +                               &rt3352_ohci_data, &rt3352_ohci_dmamask);
 198 +               ralink_add_usb("ehci-platform",
 199 +                               &rt3352_ehci_data, &rt3352_ehci_dmamask);
 200 +       }
 201 +}
 202 diff --git a/arch/mips/ralink/rt3883-usb.c b/arch/mips/ralink/rt3883-usb.c
 203 new file mode 100644
 204 index 0000000..1d948a9
 205 --- /dev/null
 206 +++ b/arch/mips/ralink/rt3883-usb.c
 207 @@ -0,0 +1,118 @@
 208 +/*
 209 + * This program is free software; you can redistribute it and/or modify it
 210 + * under the terms of the GNU General Public License version 2 as published
 211 + * by the Free Software Foundation.
 212 + *
 213 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 214 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 215 + */
 216 +
 217 +#include <linux/kernel.h>
 218 +#include <linux/init.h>
 219 +#include <linux/module.h>
 220 +
 221 +#include <linux/delay.h>
 222 +#include <linux/of_platform.h>
 223 +#include <linux/dma-mapping.h>
 224 +#include <linux/usb/ehci_pdriver.h>
 225 +#include <linux/usb/ohci_pdriver.h>
 226 +
 227 +#include <asm/mach-ralink/ralink_regs.h>
 228 +#include <asm/mach-ralink/rt3883.h>
 229 +
 230 +static atomic_t rt3883_usb_pwr_ref = ATOMIC_INIT(0);
 231 +
 232 +static int rt3883_usb_power_on(struct platform_device *pdev)
 233 +{
 234 +       if (atomic_inc_return(&rt3883_usb_pwr_ref) == 1) {
 235 +               u32 t;
 236 +
 237 +               t = rt_sysc_r32(RT3883_SYSC_REG_USB_PS);
 238 +
 239 +               /* enable clock for port0's and port1's phys */
 240 +               t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 241 +               t |= RT3883_CLKCFG1_UPHY0_CLK_EN | RT3883_CLKCFG1_UPHY1_CLK_EN;
 242 +               rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
 243 +               mdelay(500);
 244 +
 245 +               /* pull USBHOST and USBDEV out from reset */
 246 +               t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 247 +               t &= ~(RT3883_RSTCTRL_UHST | RT3883_RSTCTRL_UDEV);
 248 +               rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 249 +               mdelay(500);
 250 +
 251 +               /* enable host mode */
 252 +               t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
 253 +               t |= RT3883_SYSCFG1_USB0_HOST_MODE;
 254 +               rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
 255 +
 256 +               t = rt_sysc_r32(RT3883_SYSC_REG_USB_PS);
 257 +       }
 258 +
 259 +       return 0;
 260 +}
 261 +
 262 +static void rt3883_usb_power_off(struct platform_device *pdev)
 263 +{
 264 +       if (atomic_dec_return(&rt3883_usb_pwr_ref) == 0) {
 265 +               u32 t;
 266 +
 267 +               /* put USBHOST and USBDEV into reset */
 268 +               t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 269 +               t |= RT3883_RSTCTRL_UHST | RT3883_RSTCTRL_UDEV;
 270 +               rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 271 +               udelay(10000);
 272 +
 273 +               /* disable clock for port0's and port1's phys*/
 274 +               t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 275 +               t &= ~(RT3883_CLKCFG1_UPHY0_CLK_EN |
 276 +               RT3883_CLKCFG1_UPHY1_CLK_EN);
 277 +               rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
 278 +               udelay(10000);
 279 +       }
 280 +}
 281 +
 282 +static struct usb_ohci_pdata rt3883_ohci_data = {
 283 +       .power_on       = rt3883_usb_power_on,
 284 +       .power_off      = rt3883_usb_power_off,
 285 +};
 286 +
 287 +static struct usb_ehci_pdata rt3883_ehci_data = {
 288 +       .power_on       = rt3883_usb_power_on,
 289 +       .power_off      = rt3883_usb_power_off,
 290 +};
 291 +
 292 +static void ralink_add_usb(char *name, void *pdata, u64 *mask)
 293 +{
 294 +       struct device_node *node;
 295 +       struct platform_device *pdev;
 296 +
 297 +       node = of_find_compatible_node(NULL, NULL, name);
 298 +       if (!node)
 299 +               return;
 300 +
 301 +       pdev = of_find_device_by_node(node);
 302 +       if (!pdev)
 303 +               goto error_out;
 304 +
 305 +       if (pdata)
 306 +               pdev->dev.platform_data = pdata;
 307 +       if (mask) {
 308 +               pdev->dev.dma_mask = mask;
 309 +               pdev->dev.coherent_dma_mask = *mask;
 310 +       }
 311 +
 312 +error_out:
 313 +       of_node_put(node);
 314 +}
 315 +
 316 +static u64 rt3883_ohci_dmamask = DMA_BIT_MASK(32);
 317 +static u64 rt3883_ehci_dmamask = DMA_BIT_MASK(32);
 318 +
 319 +void ralink_usb_platform(void)
 320 +{
 321 +       ralink_add_usb("ohci-platform",
 322 +                       &rt3883_ohci_data, &rt3883_ohci_dmamask);
 323 +       ralink_add_usb("ehci-platform",
 324 +                       &rt3883_ehci_data, &rt3883_ehci_dmamask);
 325 +}
 326 --
 327 1.7.10.4
 328