1 From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:49:07 +0100
4 Subject: [PATCH 43/53] spi: add mt7621 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 Note: This patch contains upstream mt7621-spi at 9c562d8411a54f6731cdc587c29968d9e8610c85
10 drivers/spi/Kconfig | 6 +
11 drivers/spi/Makefile | 1 +
12 drivers/spi/spi-mt7621.c | 480 ++++++++++++++++++++++++++++++++++++++++++++++
13 3 files changed, 487 insertions(+)
14 create mode 100644 drivers/spi/spi-mt7621.c
16 --- a/drivers/spi/Kconfig
17 +++ b/drivers/spi/Kconfig
18 @@ -569,6 +569,12 @@ config SPI_RT2880
20 This selects a driver for the Ralink RT288x/RT305x SPI Controller.
23 + tristate "MediaTek MT7621 SPI Controller"
26 + This selects a driver for the MediaTek MT7621 SPI Controller.
29 tristate "Samsung S3C24XX series SPI"
30 depends on ARCH_S3C24XX
31 --- a/drivers/spi/Makefile
32 +++ b/drivers/spi/Makefile
33 @@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
34 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
35 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
36 obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
37 +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
38 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
39 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
40 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
42 +++ b/drivers/spi/spi-mt7621.c
45 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
47 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
48 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
49 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
51 + * Some parts are based on spi-orion.c:
52 + * Author: Shadi Ammouri <shadi@marvell.com>
53 + * Copyright (C) 2007-2008 Marvell Ltd.
55 + * This program is free software; you can redistribute it and/or modify
56 + * it under the terms of the GNU General Public License version 2 as
57 + * published by the Free Software Foundation.
60 +#include <linux/init.h>
61 +#include <linux/module.h>
62 +#include <linux/clk.h>
63 +#include <linux/err.h>
64 +#include <linux/delay.h>
65 +#include <linux/io.h>
66 +#include <linux/reset.h>
67 +#include <linux/spi/spi.h>
68 +#include <linux/of_device.h>
69 +#include <linux/platform_device.h>
70 +#include <linux/swab.h>
72 +#include <ralink_regs.h>
74 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
76 +#define DRIVER_NAME "spi-mt7621"
78 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
80 +/* SPISTAT register bit field */
81 +#define SPISTAT_BUSY BIT(0)
83 +#define MT7621_SPI_TRANS 0x00
84 +#define SPITRANS_BUSY BIT(16)
86 +#define MT7621_SPI_OPCODE 0x04
87 +#define MT7621_SPI_DATA0 0x08
88 +#define MT7621_SPI_DATA4 0x18
89 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
90 +#define SPI_CTL_START BIT(8)
92 +#define MT7621_SPI_POLAR 0x38
93 +#define MT7621_SPI_MASTER 0x28
94 +#define MT7621_SPI_MOREBUF 0x2c
95 +#define MT7621_SPI_SPACE 0x3c
97 +#define MT7621_CPHA BIT(5)
98 +#define MT7621_CPOL BIT(4)
99 +#define MT7621_LSB_FIRST BIT(3)
101 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | \
102 + SPI_LSB_FIRST | SPI_CS_HIGH)
107 + struct spi_master *master;
108 + void __iomem *base;
109 + unsigned int sys_freq;
110 + unsigned int speed;
114 + struct mt7621_spi_ops *ops;
117 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
119 + return spi_master_get_devdata(spi->master);
122 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
124 + return ioread32(rs->base + reg);
127 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
129 + iowrite32(val, rs->base + reg);
132 +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
134 + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
141 + master &= ~(1 << 10);
143 + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
144 + rs->pending_write = 0;
147 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
149 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
150 + int cs = spi->chip_select;
153 + mt7621_spi_reset(rs, cs);
156 + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
159 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
161 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
165 + dev_dbg(&spi->dev, "speed:%u\n", speed);
167 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
168 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
176 + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
177 + reg &= ~(0xfff << 16);
178 + reg |= (rate - 2) << 16;
181 + reg &= ~MT7621_LSB_FIRST;
182 + if (spi->mode & SPI_LSB_FIRST)
183 + reg |= MT7621_LSB_FIRST;
185 + reg &= ~(MT7621_CPHA | MT7621_CPOL);
186 + switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
190 + reg |= MT7621_CPHA;
193 + reg |= MT7621_CPOL;
196 + reg |= MT7621_CPOL | MT7621_CPHA;
199 + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
204 +static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
208 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
211 + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
212 + if ((status & SPITRANS_BUSY) == 0)
221 +static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
222 + int rx_len, u8 *buf)
224 + /* Combine with any pending write, and perform one or
225 + * more half-duplex transactions reading 'len' bytes.
226 + * Data to be written is already in MT7621_SPI_DATA*
228 + int tx_len = rs->pending_write;
230 + rs->pending_write = 0;
232 + while (rx_len || tx_len) {
234 + u32 val = (min(tx_len, 4) * 8) << 24;
235 + int rx = min(rx_len, 32);
238 + val |= (tx_len - 4) * 8;
239 + val |= (rx * 8) << 12;
240 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
244 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
245 + val |= SPI_CTL_START;
246 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
248 + mt7621_spi_wait_till_ready(rs);
250 + for (i = 0; i < rx; i++) {
252 + val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
253 + *buf++ = val & 0xff;
260 +static inline void mt7621_spi_flush(struct mt7621_spi *rs)
262 + mt7621_spi_read_half_duplex(rs, 0, NULL);
265 +static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
266 + int tx_len, const u8 *buf)
269 + int len = rs->pending_write;
272 + val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
274 + val <<= (4 - len) * 8;
279 + while (tx_len > 0) {
281 + rs->pending_write = len;
282 + mt7621_spi_flush(rs);
286 + val |= *buf++ << (8 * (len & 3));
288 + if ((len & 3) == 0) {
290 + /* The byte-order of the opcode is weird! */
292 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
300 + val >>= (4 - len) * 8;
302 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
304 + rs->pending_write = len;
307 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
308 + struct spi_message *m)
310 + struct mt7621_spi *rs = spi_master_get_devdata(master);
311 + struct spi_device *spi = m->spi;
312 + unsigned int speed = spi->max_speed_hz;
313 + struct spi_transfer *t = NULL;
316 + mt7621_spi_wait_till_ready(rs);
318 + list_for_each_entry(t, &m->transfers, transfer_list)
319 + if (t->speed_hz < speed)
320 + speed = t->speed_hz;
322 + if (mt7621_spi_prepare(spi, speed)) {
327 + mt7621_spi_set_cs(spi, 1);
328 + m->actual_length = 0;
329 + list_for_each_entry(t, &m->transfers, transfer_list) {
331 + mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
332 + else if (t->tx_buf)
333 + mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
334 + m->actual_length += t->len;
336 + mt7621_spi_flush(rs);
338 + mt7621_spi_set_cs(spi, 0);
340 + m->status = status;
341 + spi_finalize_current_message(master);
346 +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
347 + struct spi_message *m)
349 + struct mt7621_spi *rs = spi_master_get_devdata(master);
350 + struct spi_device *spi = m->spi;
351 + unsigned int speed = spi->max_speed_hz;
352 + struct spi_transfer *t = NULL;
356 + u32 data[9] = { 0 };
359 + mt7621_spi_wait_till_ready(rs);
361 + list_for_each_entry(t, &m->transfers, transfer_list) {
362 + const u8 *buf = t->tx_buf;
370 + if (WARN_ON(len + t->len > 16)) {
375 + for (i = 0; i < t->len; i++, len++)
376 + data[len / 4] |= buf[i] << (8 * (len & 3));
377 + if (speed > t->speed_hz)
378 + speed = t->speed_hz;
381 + if (WARN_ON(rx_len > 16)) {
386 + if (mt7621_spi_prepare(spi, speed)) {
391 + for (i = 0; i < len; i += 4)
392 + mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
395 + val |= (rx_len * 8) << 12;
396 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
398 + mt7621_spi_set_cs(spi, 1);
400 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
401 + val |= SPI_CTL_START;
402 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
404 + mt7621_spi_wait_till_ready(rs);
406 + mt7621_spi_set_cs(spi, 0);
408 + for (i = 0; i < rx_len; i += 4)
409 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
411 + m->actual_length = rx_len;
414 + list_for_each_entry(t, &m->transfers, transfer_list) {
415 + u8 *buf = t->rx_buf;
420 + for (i = 0; i < t->len; i++, len++)
421 + buf[i] = data[len / 4] >> (8 * (len & 3));
425 + m->status = status;
426 + spi_finalize_current_message(master);
431 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
432 + struct spi_message *m)
434 + struct spi_device *spi = m->spi;
435 + int cs = spi->chip_select;
438 + return mt7621_spi_transfer_full_duplex(master, m);
439 + return mt7621_spi_transfer_half_duplex(master, m);
442 +static int mt7621_spi_setup(struct spi_device *spi)
444 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
446 + if ((spi->max_speed_hz == 0) ||
447 + (spi->max_speed_hz > (rs->sys_freq / 2)))
448 + spi->max_speed_hz = (rs->sys_freq / 2);
450 + if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
451 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
452 + spi->max_speed_hz);
459 +static const struct of_device_id mt7621_spi_match[] = {
460 + { .compatible = "ralink,mt7621-spi" },
463 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
465 +static int mt7621_spi_probe(struct platform_device *pdev)
467 + const struct of_device_id *match;
468 + struct spi_master *master;
469 + struct mt7621_spi *rs;
470 + void __iomem *base;
471 + struct resource *r;
474 + struct mt7621_spi_ops *ops;
476 + match = of_match_device(mt7621_spi_match, &pdev->dev);
479 + ops = (struct mt7621_spi_ops *)match->data;
481 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
482 + base = devm_ioremap_resource(&pdev->dev, r);
484 + return PTR_ERR(base);
486 + clk = devm_clk_get(&pdev->dev, NULL);
488 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
490 + return PTR_ERR(clk);
493 + status = clk_prepare_enable(clk);
497 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
498 + if (master == NULL) {
499 + dev_info(&pdev->dev, "master allocation failed\n");
503 + master->mode_bits = RT2880_SPI_MODE_BITS;
505 + master->setup = mt7621_spi_setup;
506 + master->transfer_one_message = mt7621_spi_transfer_one_message;
507 + master->bits_per_word_mask = SPI_BPW_MASK(8);
508 + master->dev.of_node = pdev->dev.of_node;
509 + master->num_chipselect = 2;
511 + dev_set_drvdata(&pdev->dev, master);
513 + rs = spi_master_get_devdata(master);
516 + rs->master = master;
517 + rs->sys_freq = clk_get_rate(rs->clk);
519 + rs->pending_write = 0;
520 + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
522 + device_reset(&pdev->dev);
524 + mt7621_spi_reset(rs, 0);
526 + return spi_register_master(master);
529 +static int mt7621_spi_remove(struct platform_device *pdev)
531 + struct spi_master *master;
532 + struct mt7621_spi *rs;
534 + master = dev_get_drvdata(&pdev->dev);
535 + rs = spi_master_get_devdata(master);
537 + clk_disable(rs->clk);
538 + spi_unregister_master(master);
543 +MODULE_ALIAS("platform:" DRIVER_NAME);
545 +static struct platform_driver mt7621_spi_driver = {
547 + .name = DRIVER_NAME,
548 + .of_match_table = mt7621_spi_match,
550 + .probe = mt7621_spi_probe,
551 + .remove = mt7621_spi_remove,
554 +module_platform_driver(mt7621_spi_driver);
556 +MODULE_DESCRIPTION("MT7621 SPI driver");
557 +MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
558 +MODULE_LICENSE("GPL");