1 From cbd66c626e16743b05af807ad48012c0a097b9fb Mon Sep 17 00:00:00 2001
2 From: Stefan Roese <sr@denx.de>
3 Date: Mon, 25 Mar 2019 09:29:25 +0100
4 Subject: [PATCH] spi: mt7621: Move SPI driver out of staging
6 This patch moves the MT7621 SPI driver, which is used on some Ralink /
7 MediaTek MT76xx MIPS SoC's, out of the staging directory. No changes to
8 the source code are done in this patch.
10 This driver version was tested successfully on an MT7688 based platform
11 with an SPI NOR on CS0 and an SPI NAND on CS1 without any issues (so
14 This patch also documents the devicetree bindings for the MT7621 SPI
17 Signed-off-by: Stefan Roese <sr@denx.de>
18 Cc: Rob Herring <robh@kernel.org>
19 Cc: Mark Brown <broonie@kernel.org>
20 Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
21 Cc: NeilBrown <neil@brown.name>
22 Cc: Sankalp Negi <sankalpnegi2310@gmail.com>
23 Cc: Chuanhong Guo <gch981213@gmail.com>
24 Cc: John Crispin <john@phrozen.org>
25 Cc: Armando Miraglia <arma2ff0@gmail.com>
26 Signed-off-by: Mark Brown <broonie@kernel.org>
28 .../devicetree/bindings/spi/spi-mt7621.txt | 26 ++++++
29 drivers/spi/Kconfig | 6 ++
30 drivers/spi/Makefile | 1 +
31 .../{staging/mt7621-spi => spi}/spi-mt7621.c | 83 +++++++++----------
32 drivers/staging/Kconfig | 2 -
33 drivers/staging/Makefile | 1 -
34 drivers/staging/mt7621-spi/Kconfig | 6 --
35 drivers/staging/mt7621-spi/Makefile | 1 -
36 drivers/staging/mt7621-spi/TODO | 5 --
37 9 files changed, 74 insertions(+), 57 deletions(-)
38 create mode 100644 Documentation/devicetree/bindings/spi/spi-mt7621.txt
39 rename drivers/{staging/mt7621-spi => spi}/spi-mt7621.c (88%)
40 delete mode 100644 drivers/staging/mt7621-spi/Kconfig
41 delete mode 100644 drivers/staging/mt7621-spi/Makefile
42 delete mode 100644 drivers/staging/mt7621-spi/TODO
44 --- a/drivers/spi/Kconfig
45 +++ b/drivers/spi/Kconfig
46 @@ -569,6 +569,12 @@ config SPI_RT2880
48 This selects a driver for the Ralink RT288x/RT305x SPI Controller.
51 + tristate "MediaTek MT7621 SPI Controller"
54 + This selects a driver for the MediaTek MT7621 SPI Controller.
57 tristate "Samsung S3C24XX series SPI"
58 depends on ARCH_S3C24XX
59 --- a/drivers/spi/Makefile
60 +++ b/drivers/spi/Makefile
61 @@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
62 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
63 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
64 obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
65 +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
66 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
67 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
68 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
70 +++ b/drivers/spi/spi-mt7621.c
72 +// SPDX-License-Identifier: GPL-2.0
74 +// spi-mt7621.c -- MediaTek MT7621 SPI controller driver
76 +// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
77 +// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
78 +// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
80 +// Some parts are based on spi-orion.c:
81 +// Author: Shadi Ammouri <shadi@marvell.com>
82 +// Copyright (C) 2007-2008 Marvell Ltd.
84 +#include <linux/clk.h>
85 +#include <linux/delay.h>
86 +#include <linux/io.h>
87 +#include <linux/module.h>
88 +#include <linux/of_device.h>
89 +#include <linux/reset.h>
90 +#include <linux/spi/spi.h>
92 +#define DRIVER_NAME "spi-mt7621"
95 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
97 +/* SPISTAT register bit field */
98 +#define SPISTAT_BUSY BIT(0)
100 +#define MT7621_SPI_TRANS 0x00
101 +#define SPITRANS_BUSY BIT(16)
103 +#define MT7621_SPI_OPCODE 0x04
104 +#define MT7621_SPI_DATA0 0x08
105 +#define MT7621_SPI_DATA4 0x18
106 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
107 +#define SPI_CTL_START BIT(8)
109 +#define MT7621_SPI_MASTER 0x28
110 +#define MASTER_MORE_BUFMODE BIT(2)
111 +#define MASTER_FULL_DUPLEX BIT(10)
112 +#define MASTER_RS_CLK_SEL GENMASK(27, 16)
113 +#define MASTER_RS_CLK_SEL_SHIFT 16
114 +#define MASTER_RS_SLAVE_SEL GENMASK(31, 29)
116 +#define MT7621_SPI_MOREBUF 0x2c
117 +#define MT7621_SPI_POLAR 0x38
118 +#define MT7621_SPI_SPACE 0x3c
120 +#define MT7621_CPHA BIT(5)
121 +#define MT7621_CPOL BIT(4)
122 +#define MT7621_LSB_FIRST BIT(3)
125 + struct spi_controller *master;
126 + void __iomem *base;
127 + unsigned int sys_freq;
128 + unsigned int speed;
133 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
135 + return spi_controller_get_devdata(spi->master);
138 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
140 + return ioread32(rs->base + reg);
143 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
145 + iowrite32(val, rs->base + reg);
148 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
150 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
151 + int cs = spi->chip_select;
156 + * Select SPI device 7, enable "more buffer mode" and disable
157 + * full-duplex (only half-duplex really works on this chip
160 + master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
161 + master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
162 + master &= ~MASTER_FULL_DUPLEX;
163 + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
165 + rs->pending_write = 0;
169 + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
172 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
174 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
178 + dev_dbg(&spi->dev, "speed:%u\n", speed);
180 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
181 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
189 + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
190 + reg &= ~MASTER_RS_CLK_SEL;
191 + reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
194 + reg &= ~MT7621_LSB_FIRST;
195 + if (spi->mode & SPI_LSB_FIRST)
196 + reg |= MT7621_LSB_FIRST;
199 + * This SPI controller seems to be tested on SPI flash only and some
200 + * bits are swizzled under other SPI modes probably due to incorrect
201 + * wiring inside the silicon. Only mode 0 works correctly.
203 + reg &= ~(MT7621_CPHA | MT7621_CPOL);
205 + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
210 +static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
214 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
217 + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
218 + if ((status & SPITRANS_BUSY) == 0)
227 +static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
228 + int rx_len, u8 *buf)
233 + * Combine with any pending write, and perform one or more half-duplex
234 + * transactions reading 'len' bytes. Data to be written is already in
237 + tx_len = rs->pending_write;
238 + rs->pending_write = 0;
240 + while (rx_len || tx_len) {
242 + u32 val = (min(tx_len, 4) * 8) << 24;
243 + int rx = min(rx_len, 32);
246 + val |= (tx_len - 4) * 8;
247 + val |= (rx * 8) << 12;
248 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
252 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
253 + val |= SPI_CTL_START;
254 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
256 + mt7621_spi_wait_till_ready(rs);
258 + for (i = 0; i < rx; i++) {
260 + val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
261 + *buf++ = val & 0xff;
269 +static inline void mt7621_spi_flush(struct mt7621_spi *rs)
271 + mt7621_spi_read_half_duplex(rs, 0, NULL);
274 +static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
275 + int tx_len, const u8 *buf)
277 + int len = rs->pending_write;
281 + val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
283 + val <<= (4 - len) * 8;
288 + while (tx_len > 0) {
290 + rs->pending_write = len;
291 + mt7621_spi_flush(rs);
295 + val |= *buf++ << (8 * (len & 3));
297 + if ((len & 3) == 0) {
299 + /* The byte-order of the opcode is weird! */
301 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
310 + val >>= (4 - len) * 8;
312 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
315 + rs->pending_write = len;
318 +static int mt7621_spi_transfer_one_message(struct spi_controller *master,
319 + struct spi_message *m)
321 + struct mt7621_spi *rs = spi_controller_get_devdata(master);
322 + struct spi_device *spi = m->spi;
323 + unsigned int speed = spi->max_speed_hz;
324 + struct spi_transfer *t = NULL;
327 + mt7621_spi_wait_till_ready(rs);
329 + list_for_each_entry(t, &m->transfers, transfer_list)
330 + if (t->speed_hz < speed)
331 + speed = t->speed_hz;
333 + if (mt7621_spi_prepare(spi, speed)) {
339 + mt7621_spi_set_cs(spi, 1);
341 + m->actual_length = 0;
342 + list_for_each_entry(t, &m->transfers, transfer_list) {
343 + if ((t->rx_buf) && (t->tx_buf)) {
345 + * This controller will shift some extra data out
346 + * of spi_opcode if (mosi_bit_cnt > 0) &&
347 + * (cmd_bit_cnt == 0). So the claimed full-duplex
348 + * support is broken since we have no way to read
349 + * the MISO value during that bit.
353 + } else if (t->rx_buf) {
354 + mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
355 + } else if (t->tx_buf) {
356 + mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
358 + m->actual_length += t->len;
361 + /* Flush data and deassert CS */
362 + mt7621_spi_flush(rs);
363 + mt7621_spi_set_cs(spi, 0);
366 + m->status = status;
367 + spi_finalize_current_message(master);
372 +static int mt7621_spi_setup(struct spi_device *spi)
374 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
376 + if ((spi->max_speed_hz == 0) ||
377 + (spi->max_speed_hz > (rs->sys_freq / 2)))
378 + spi->max_speed_hz = (rs->sys_freq / 2);
380 + if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
381 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
382 + spi->max_speed_hz);
389 +static const struct of_device_id mt7621_spi_match[] = {
390 + { .compatible = "ralink,mt7621-spi" },
393 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
395 +static int mt7621_spi_probe(struct platform_device *pdev)
397 + const struct of_device_id *match;
398 + struct spi_controller *master;
399 + struct mt7621_spi *rs;
400 + void __iomem *base;
401 + struct resource *r;
406 + match = of_match_device(mt7621_spi_match, &pdev->dev);
410 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
411 + base = devm_ioremap_resource(&pdev->dev, r);
413 + return PTR_ERR(base);
415 + clk = devm_clk_get(&pdev->dev, NULL);
417 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
419 + return PTR_ERR(clk);
422 + status = clk_prepare_enable(clk);
426 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
428 + dev_info(&pdev->dev, "master allocation failed\n");
432 + master->mode_bits = SPI_LSB_FIRST;
433 + master->flags = SPI_CONTROLLER_HALF_DUPLEX;
434 + master->setup = mt7621_spi_setup;
435 + master->transfer_one_message = mt7621_spi_transfer_one_message;
436 + master->bits_per_word_mask = SPI_BPW_MASK(8);
437 + master->dev.of_node = pdev->dev.of_node;
438 + master->num_chipselect = 2;
440 + dev_set_drvdata(&pdev->dev, master);
442 + rs = spi_controller_get_devdata(master);
445 + rs->master = master;
446 + rs->sys_freq = clk_get_rate(rs->clk);
447 + rs->pending_write = 0;
448 + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
450 + ret = device_reset(&pdev->dev);
452 + dev_err(&pdev->dev, "SPI reset failed!\n");
456 + return devm_spi_register_controller(&pdev->dev, master);
459 +static int mt7621_spi_remove(struct platform_device *pdev)
461 + struct spi_controller *master;
462 + struct mt7621_spi *rs;
464 + master = dev_get_drvdata(&pdev->dev);
465 + rs = spi_controller_get_devdata(master);
467 + clk_disable_unprepare(rs->clk);
472 +MODULE_ALIAS("platform:" DRIVER_NAME);
474 +static struct platform_driver mt7621_spi_driver = {
476 + .name = DRIVER_NAME,
477 + .of_match_table = mt7621_spi_match,
479 + .probe = mt7621_spi_probe,
480 + .remove = mt7621_spi_remove,
483 +module_platform_driver(mt7621_spi_driver);
485 +MODULE_DESCRIPTION("MT7621 SPI driver");
486 +MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
487 +MODULE_LICENSE("GPL");