1 From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:49:07 +0100
4 Subject: [PATCH 43/53] spi: add mt7621 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/spi/Kconfig | 6 +
9 drivers/spi/Makefile | 1 +
10 drivers/spi/spi-mt7621.c | 480 ++++++++++++++++++++++++++++++++++++++++++++++
11 3 files changed, 487 insertions(+)
12 create mode 100644 drivers/spi/spi-mt7621.c
14 --- a/drivers/spi/Kconfig
15 +++ b/drivers/spi/Kconfig
16 @@ -569,6 +569,12 @@ config SPI_RT2880
18 This selects a driver for the Ralink RT288x/RT305x SPI Controller.
21 + tristate "MediaTek MT7621 SPI Controller"
24 + This selects a driver for the MediaTek MT7621 SPI Controller.
27 tristate "Samsung S3C24XX series SPI"
28 depends on ARCH_S3C24XX
29 --- a/drivers/spi/Makefile
30 +++ b/drivers/spi/Makefile
31 @@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
32 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
33 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
34 obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
35 +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
36 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
37 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
38 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
40 +++ b/drivers/spi/spi-mt7621.c
43 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
45 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
46 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
47 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
49 + * Some parts are based on spi-orion.c:
50 + * Author: Shadi Ammouri <shadi@marvell.com>
51 + * Copyright (C) 2007-2008 Marvell Ltd.
53 + * This program is free software; you can redistribute it and/or modify
54 + * it under the terms of the GNU General Public License version 2 as
55 + * published by the Free Software Foundation.
58 +#include <linux/init.h>
59 +#include <linux/module.h>
60 +#include <linux/clk.h>
61 +#include <linux/err.h>
62 +#include <linux/delay.h>
63 +#include <linux/io.h>
64 +#include <linux/reset.h>
65 +#include <linux/spi/spi.h>
66 +#include <linux/of_device.h>
67 +#include <linux/platform_device.h>
68 +#include <linux/swab.h>
70 +#include <ralink_regs.h>
72 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
74 +#define DRIVER_NAME "spi-mt7621"
76 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
78 +/* SPISTAT register bit field */
79 +#define SPISTAT_BUSY BIT(0)
81 +#define MT7621_SPI_TRANS 0x00
82 +#define SPITRANS_BUSY BIT(16)
84 +#define MT7621_SPI_OPCODE 0x04
85 +#define MT7621_SPI_DATA0 0x08
86 +#define MT7621_SPI_DATA4 0x18
87 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
88 +#define SPI_CTL_START BIT(8)
90 +#define MT7621_SPI_POLAR 0x38
91 +#define MT7621_SPI_MASTER 0x28
92 +#define MT7621_SPI_MOREBUF 0x2c
93 +#define MT7621_SPI_SPACE 0x3c
95 +#define MT7621_CPHA BIT(5)
96 +#define MT7621_CPOL BIT(4)
97 +#define MT7621_LSB_FIRST BIT(3)
99 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
104 + struct spi_master *master;
105 + void __iomem *base;
106 + unsigned int sys_freq;
107 + unsigned int speed;
110 + struct mt7621_spi_ops *ops;
113 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
115 + return spi_master_get_devdata(spi->master);
118 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
120 + return ioread32(rs->base + reg);
123 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
125 + iowrite32(val, rs->base + reg);
128 +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
130 + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
134 +#ifdef CONFIG_SOC_MT7620
139 + master &= ~(1 << 10);
141 + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
144 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
146 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
147 + int cs = spi->chip_select;
150 + mt7621_spi_reset(rs, cs);
153 + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
156 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
158 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
162 + dev_dbg(&spi->dev, "speed:%u\n", speed);
164 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
165 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
173 + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
174 + reg &= ~(0xfff << 16);
175 + reg |= (rate - 2) << 16;
178 + reg &= ~MT7621_LSB_FIRST;
179 + if (spi->mode & SPI_LSB_FIRST)
180 + reg |= MT7621_LSB_FIRST;
182 + reg &= ~(MT7621_CPHA | MT7621_CPOL);
183 + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
187 + reg |= MT7621_CPHA;
190 + reg |= MT7621_CPOL;
193 + reg |= MT7621_CPOL | MT7621_CPHA;
196 + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
201 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
203 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
206 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
209 + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
210 + if ((status & SPITRANS_BUSY) == 0) {
220 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
221 + struct spi_message *m)
223 + struct mt7621_spi *rs = spi_master_get_devdata(master);
224 + struct spi_device *spi = m->spi;
225 + unsigned int speed = spi->max_speed_hz;
226 + struct spi_transfer *t = NULL;
230 + u32 data[9] = { 0 };
233 + mt7621_spi_wait_till_ready(spi);
235 + list_for_each_entry(t, &m->transfers, transfer_list) {
236 + const u8 *buf = t->tx_buf;
244 + if (t->speed_hz < speed)
245 + speed = t->speed_hz;
248 + * m25p80 might attempt to write more data than we can handle.
249 + * truncate the message to what we can fit into the registers
251 + if (len + t->len > 36)
254 + for (i = 0; i < t->len; i++, len++)
255 + data[len / 4] |= buf[i] << (8 * (len & 3));
258 + if (WARN_ON(rx_len > 32)) {
263 + if (mt7621_spi_prepare(spi, speed)) {
267 + data[0] = swab32(data[0]);
269 + data[0] >>= (4 - len) * 8;
271 + for (i = 0; i < len; i += 4)
272 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
274 + val = (min_t(int, len, 4) * 8) << 24;
276 + val |= (len - 4) * 8;
277 + val |= (rx_len * 8) << 12;
278 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
280 + mt7621_spi_set_cs(spi, 1);
282 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
283 + val |= SPI_CTL_START;
284 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
286 + mt7621_spi_wait_till_ready(spi);
288 + mt7621_spi_set_cs(spi, 0);
290 + for (i = 0; i < rx_len; i += 4)
291 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
293 + m->actual_length = len + rx_len;
296 + list_for_each_entry(t, &m->transfers, transfer_list) {
297 + u8 *buf = t->rx_buf;
302 + for (i = 0; i < t->len; i++, len++)
303 + buf[i] = data[len / 4] >> (8 * (len & 3));
307 + m->status = status;
308 + spi_finalize_current_message(master);
313 +#ifdef CONFIG_SOC_MT7620
314 +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
315 + struct spi_message *m)
317 + struct mt7621_spi *rs = spi_master_get_devdata(master);
318 + struct spi_device *spi = m->spi;
319 + unsigned int speed = spi->max_speed_hz;
320 + struct spi_transfer *t = NULL;
324 + u32 data[9] = { 0 };
327 + mt7621_spi_wait_till_ready(spi);
329 + list_for_each_entry(t, &m->transfers, transfer_list) {
330 + const u8 *buf = t->tx_buf;
338 + if (WARN_ON(len + t->len > 16)) {
343 + for (i = 0; i < t->len; i++, len++)
344 + data[len / 4] |= buf[i] << (8 * (len & 3));
345 + if (speed > t->speed_hz)
346 + speed = t->speed_hz;
349 + if (WARN_ON(rx_len > 16)) {
354 + if (mt7621_spi_prepare(spi, speed)) {
359 + for (i = 0; i < len; i += 4)
360 + mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
363 + val |= (rx_len * 8) << 12;
364 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
366 + mt7621_spi_set_cs(spi, 1);
368 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
369 + val |= SPI_CTL_START;
370 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
372 + mt7621_spi_wait_till_ready(spi);
374 + mt7621_spi_set_cs(spi, 0);
376 + for (i = 0; i < rx_len; i += 4)
377 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
379 + m->actual_length = rx_len;
382 + list_for_each_entry(t, &m->transfers, transfer_list) {
383 + u8 *buf = t->rx_buf;
388 + for (i = 0; i < t->len; i++, len++)
389 + buf[i] = data[len / 4] >> (8 * (len & 3));
393 + m->status = status;
394 + spi_finalize_current_message(master);
400 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
401 + struct spi_message *m)
403 + struct spi_device *spi = m->spi;
404 +#ifdef CONFIG_SOC_MT7620
405 + int cs = spi->chip_select;
408 + return mt7621_spi_transfer_full_duplex(master, m);
410 + return mt7621_spi_transfer_half_duplex(master, m);
413 +static int mt7621_spi_setup(struct spi_device *spi)
415 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
417 + if ((spi->max_speed_hz == 0) ||
418 + (spi->max_speed_hz > (rs->sys_freq / 2)))
419 + spi->max_speed_hz = (rs->sys_freq / 2);
421 + if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
422 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
423 + spi->max_speed_hz);
430 +static const struct of_device_id mt7621_spi_match[] = {
431 + { .compatible = "ralink,mt7621-spi" },
434 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
436 +static size_t mt7621_max_transfer_size(struct spi_device *spi)
441 +static int mt7621_spi_probe(struct platform_device *pdev)
443 + const struct of_device_id *match;
444 + struct spi_master *master;
445 + struct mt7621_spi *rs;
446 + void __iomem *base;
447 + struct resource *r;
450 + struct mt7621_spi_ops *ops;
452 + match = of_match_device(mt7621_spi_match, &pdev->dev);
455 + ops = (struct mt7621_spi_ops *)match->data;
457 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
458 + base = devm_ioremap_resource(&pdev->dev, r);
460 + return PTR_ERR(base);
462 + clk = devm_clk_get(&pdev->dev, NULL);
464 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
466 + return PTR_ERR(clk);
469 + status = clk_prepare_enable(clk);
473 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
474 + if (master == NULL) {
475 + dev_info(&pdev->dev, "master allocation failed\n");
479 + master->mode_bits = RT2880_SPI_MODE_BITS;
481 + master->setup = mt7621_spi_setup;
482 + master->transfer_one_message = mt7621_spi_transfer_one_message;
483 + master->bits_per_word_mask = SPI_BPW_MASK(8);
484 + master->dev.of_node = pdev->dev.of_node;
485 + master->num_chipselect = 2;
486 + master->max_transfer_size = mt7621_max_transfer_size;
488 + dev_set_drvdata(&pdev->dev, master);
490 + rs = spi_master_get_devdata(master);
493 + rs->master = master;
494 + rs->sys_freq = clk_get_rate(rs->clk);
496 + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
498 + device_reset(&pdev->dev);
500 + mt7621_spi_reset(rs, 0);
502 + return spi_register_master(master);
505 +static int mt7621_spi_remove(struct platform_device *pdev)
507 + struct spi_master *master;
508 + struct mt7621_spi *rs;
510 + master = dev_get_drvdata(&pdev->dev);
511 + rs = spi_master_get_devdata(master);
513 + clk_disable(rs->clk);
514 + spi_unregister_master(master);
519 +MODULE_ALIAS("platform:" DRIVER_NAME);
521 +static struct platform_driver mt7621_spi_driver = {
523 + .name = DRIVER_NAME,
524 + .owner = THIS_MODULE,
525 + .of_match_table = mt7621_spi_match,
527 + .probe = mt7621_spi_probe,
528 + .remove = mt7621_spi_remove,
531 +module_platform_driver(mt7621_spi_driver);
533 +MODULE_DESCRIPTION("MT7621 SPI driver");
534 +MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
535 +MODULE_LICENSE("GPL");