1 From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:49:07 +0100
4 Subject: [PATCH 43/53] spi: add mt7621 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/spi/Kconfig | 6 +
9 drivers/spi/Makefile | 1 +
10 drivers/spi/spi-mt7621.c | 480 ++++++++++++++++++++++++++++++++++++++++++++++
11 3 files changed, 487 insertions(+)
12 create mode 100644 drivers/spi/spi-mt7621.c
14 Index: linux-4.14.37/drivers/spi/Kconfig
15 ===================================================================
16 --- linux-4.14.37.orig/drivers/spi/Kconfig
17 +++ linux-4.14.37/drivers/spi/Kconfig
18 @@ -569,6 +569,12 @@ config SPI_RT2880
20 This selects a driver for the Ralink RT288x/RT305x SPI Controller.
23 + tristate "MediaTek MT7621 SPI Controller"
26 + This selects a driver for the MediaTek MT7621 SPI Controller.
29 tristate "Samsung S3C24XX series SPI"
30 depends on ARCH_S3C24XX
31 Index: linux-4.14.37/drivers/spi/Makefile
32 ===================================================================
33 --- linux-4.14.37.orig/drivers/spi/Makefile
34 +++ linux-4.14.37/drivers/spi/Makefile
35 @@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
36 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
37 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
38 obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
39 +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
40 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
41 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
42 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
43 Index: linux-4.14.37/drivers/spi/spi-mt7621.c
44 ===================================================================
46 +++ linux-4.14.37/drivers/spi/spi-mt7621.c
49 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
51 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
52 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
53 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
55 + * Some parts are based on spi-orion.c:
56 + * Author: Shadi Ammouri <shadi@marvell.com>
57 + * Copyright (C) 2007-2008 Marvell Ltd.
59 + * This program is free software; you can redistribute it and/or modify
60 + * it under the terms of the GNU General Public License version 2 as
61 + * published by the Free Software Foundation.
64 +#include <linux/init.h>
65 +#include <linux/module.h>
66 +#include <linux/clk.h>
67 +#include <linux/err.h>
68 +#include <linux/delay.h>
69 +#include <linux/io.h>
70 +#include <linux/reset.h>
71 +#include <linux/spi/spi.h>
72 +#include <linux/of_device.h>
73 +#include <linux/platform_device.h>
74 +#include <linux/swab.h>
76 +#include <ralink_regs.h>
78 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
80 +#define DRIVER_NAME "spi-mt7621"
82 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
84 +/* SPISTAT register bit field */
85 +#define SPISTAT_BUSY BIT(0)
87 +#define MT7621_SPI_TRANS 0x00
88 +#define SPITRANS_BUSY BIT(16)
90 +#define MT7621_SPI_OPCODE 0x04
91 +#define MT7621_SPI_DATA0 0x08
92 +#define MT7621_SPI_DATA4 0x18
93 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
94 +#define SPI_CTL_START BIT(8)
96 +#define MT7621_SPI_POLAR 0x38
97 +#define MT7621_SPI_MASTER 0x28
98 +#define MT7621_SPI_MOREBUF 0x2c
99 +#define MT7621_SPI_SPACE 0x3c
101 +#define MT7621_CPHA BIT(5)
102 +#define MT7621_CPOL BIT(4)
103 +#define MT7621_LSB_FIRST BIT(3)
105 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
110 + struct spi_master *master;
111 + void __iomem *base;
112 + unsigned int sys_freq;
113 + unsigned int speed;
116 + struct mt7621_spi_ops *ops;
119 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
121 + return spi_master_get_devdata(spi->master);
124 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
126 + return ioread32(rs->base + reg);
129 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
131 + iowrite32(val, rs->base + reg);
134 +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
136 + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
140 +#ifdef CONFIG_SOC_MT7620
145 + master &= ~(1 << 10);
147 + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
150 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
152 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
153 + int cs = spi->chip_select;
156 + mt7621_spi_reset(rs, cs);
159 + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
162 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
164 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
168 + dev_dbg(&spi->dev, "speed:%u\n", speed);
170 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
171 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
179 + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
180 + reg &= ~(0xfff << 16);
181 + reg |= (rate - 2) << 16;
184 + reg &= ~MT7621_LSB_FIRST;
185 + if (spi->mode & SPI_LSB_FIRST)
186 + reg |= MT7621_LSB_FIRST;
188 + reg &= ~(MT7621_CPHA | MT7621_CPOL);
189 + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
193 + reg |= MT7621_CPHA;
196 + reg |= MT7621_CPOL;
199 + reg |= MT7621_CPOL | MT7621_CPHA;
202 + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
207 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
209 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
212 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
215 + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
216 + if ((status & SPITRANS_BUSY) == 0) {
226 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
227 + struct spi_message *m)
229 + struct mt7621_spi *rs = spi_master_get_devdata(master);
230 + struct spi_device *spi = m->spi;
231 + unsigned int speed = spi->max_speed_hz;
232 + struct spi_transfer *t = NULL;
236 + u32 data[9] = { 0 };
239 + mt7621_spi_wait_till_ready(spi);
241 + list_for_each_entry(t, &m->transfers, transfer_list) {
242 + const u8 *buf = t->tx_buf;
250 + if (t->speed_hz < speed)
251 + speed = t->speed_hz;
254 + * m25p80 might attempt to write more data than we can handle.
255 + * truncate the message to what we can fit into the registers
257 + if (len + t->len > 36)
260 + for (i = 0; i < t->len; i++, len++)
261 + data[len / 4] |= buf[i] << (8 * (len & 3));
264 + if (WARN_ON(rx_len > 32)) {
269 + if (mt7621_spi_prepare(spi, speed)) {
273 + data[0] = swab32(data[0]);
275 + data[0] >>= (4 - len) * 8;
277 + for (i = 0; i < len; i += 4)
278 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
280 + val = (min_t(int, len, 4) * 8) << 24;
282 + val |= (len - 4) * 8;
283 + val |= (rx_len * 8) << 12;
284 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
286 + mt7621_spi_set_cs(spi, 1);
288 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
289 + val |= SPI_CTL_START;
290 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
292 + mt7621_spi_wait_till_ready(spi);
294 + mt7621_spi_set_cs(spi, 0);
296 + for (i = 0; i < rx_len; i += 4)
297 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
299 + m->actual_length = len + rx_len;
302 + list_for_each_entry(t, &m->transfers, transfer_list) {
303 + u8 *buf = t->rx_buf;
308 + for (i = 0; i < t->len; i++, len++)
309 + buf[i] = data[len / 4] >> (8 * (len & 3));
313 + m->status = status;
314 + spi_finalize_current_message(master);
319 +#ifdef CONFIG_SOC_MT7620
320 +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
321 + struct spi_message *m)
323 + struct mt7621_spi *rs = spi_master_get_devdata(master);
324 + struct spi_device *spi = m->spi;
325 + unsigned int speed = spi->max_speed_hz;
326 + struct spi_transfer *t = NULL;
330 + u32 data[9] = { 0 };
333 + mt7621_spi_wait_till_ready(spi);
335 + list_for_each_entry(t, &m->transfers, transfer_list) {
336 + const u8 *buf = t->tx_buf;
344 + if (WARN_ON(len + t->len > 16)) {
349 + for (i = 0; i < t->len; i++, len++)
350 + data[len / 4] |= buf[i] << (8 * (len & 3));
351 + if (speed > t->speed_hz)
352 + speed = t->speed_hz;
355 + if (WARN_ON(rx_len > 16)) {
360 + if (mt7621_spi_prepare(spi, speed)) {
365 + for (i = 0; i < len; i += 4)
366 + mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
369 + val |= (rx_len * 8) << 12;
370 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
372 + mt7621_spi_set_cs(spi, 1);
374 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
375 + val |= SPI_CTL_START;
376 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
378 + mt7621_spi_wait_till_ready(spi);
380 + mt7621_spi_set_cs(spi, 0);
382 + for (i = 0; i < rx_len; i += 4)
383 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
385 + m->actual_length = rx_len;
388 + list_for_each_entry(t, &m->transfers, transfer_list) {
389 + u8 *buf = t->rx_buf;
394 + for (i = 0; i < t->len; i++, len++)
395 + buf[i] = data[len / 4] >> (8 * (len & 3));
399 + m->status = status;
400 + spi_finalize_current_message(master);
406 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
407 + struct spi_message *m)
409 + struct spi_device *spi = m->spi;
410 +#ifdef CONFIG_SOC_MT7620
411 + int cs = spi->chip_select;
414 + return mt7621_spi_transfer_full_duplex(master, m);
416 + return mt7621_spi_transfer_half_duplex(master, m);
419 +static int mt7621_spi_setup(struct spi_device *spi)
421 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
423 + if ((spi->max_speed_hz == 0) ||
424 + (spi->max_speed_hz > (rs->sys_freq / 2)))
425 + spi->max_speed_hz = (rs->sys_freq / 2);
427 + if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
428 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
429 + spi->max_speed_hz);
436 +static const struct of_device_id mt7621_spi_match[] = {
437 + { .compatible = "ralink,mt7621-spi" },
440 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
442 +static size_t mt7621_max_transfer_size(struct spi_device *spi)
447 +static int mt7621_spi_probe(struct platform_device *pdev)
449 + const struct of_device_id *match;
450 + struct spi_master *master;
451 + struct mt7621_spi *rs;
452 + void __iomem *base;
453 + struct resource *r;
456 + struct mt7621_spi_ops *ops;
458 + match = of_match_device(mt7621_spi_match, &pdev->dev);
461 + ops = (struct mt7621_spi_ops *)match->data;
463 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
464 + base = devm_ioremap_resource(&pdev->dev, r);
466 + return PTR_ERR(base);
468 + clk = devm_clk_get(&pdev->dev, NULL);
470 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
472 + return PTR_ERR(clk);
475 + status = clk_prepare_enable(clk);
479 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
480 + if (master == NULL) {
481 + dev_info(&pdev->dev, "master allocation failed\n");
485 + master->mode_bits = RT2880_SPI_MODE_BITS;
487 + master->setup = mt7621_spi_setup;
488 + master->transfer_one_message = mt7621_spi_transfer_one_message;
489 + master->bits_per_word_mask = SPI_BPW_MASK(8);
490 + master->dev.of_node = pdev->dev.of_node;
491 + master->num_chipselect = 2;
492 + master->max_transfer_size = mt7621_max_transfer_size;
494 + dev_set_drvdata(&pdev->dev, master);
496 + rs = spi_master_get_devdata(master);
499 + rs->master = master;
500 + rs->sys_freq = clk_get_rate(rs->clk);
502 + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
504 + device_reset(&pdev->dev);
506 + mt7621_spi_reset(rs, 0);
508 + return spi_register_master(master);
511 +static int mt7621_spi_remove(struct platform_device *pdev)
513 + struct spi_master *master;
514 + struct mt7621_spi *rs;
516 + master = dev_get_drvdata(&pdev->dev);
517 + rs = spi_master_get_devdata(master);
519 + clk_disable(rs->clk);
520 + spi_unregister_master(master);
525 +MODULE_ALIAS("platform:" DRIVER_NAME);
527 +static struct platform_driver mt7621_spi_driver = {
529 + .name = DRIVER_NAME,
530 + .owner = THIS_MODULE,
531 + .of_match_table = mt7621_spi_match,
533 + .probe = mt7621_spi_probe,
534 + .remove = mt7621_spi_remove,
537 +module_platform_driver(mt7621_spi_driver);
539 +MODULE_DESCRIPTION("MT7621 SPI driver");
540 +MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
541 +MODULE_LICENSE("GPL");