1 --- a/arch/mips/ralink/mt7621.c
2 +++ b/arch/mips/ralink/mt7621.c
5 #include <linux/kernel.h>
6 #include <linux/init.h>
7 +#include <linux/jiffies.h>
9 #include <asm/mipsregs.h>
10 #include <asm/smp-ops.h>
12 #include <asm/mach-ralink/ralink_regs.h>
13 #include <asm/mach-ralink/mt7621.h>
14 #include <asm/mips-boards/launch.h>
15 +#include <asm/delay.h>
19 @@ -177,6 +178,58 @@ bool plat_cpu_core_present(int core)
25 +* Re-calibration lpj(loop-per-jiffy).
26 +* (derived from kernel/calibrate.c)
28 +static int udelay_recal(void)
30 + unsigned int i, lpj = 0;
31 + unsigned long ticks, loopbit;
32 + int lps_precision = LPS_PREC;
36 + while ((lpj <<= 1) != 0) {
37 + /* wait for "start of" clock tick */
39 + while (ticks == jiffies)
45 + ticks = jiffies - ticks;
51 + * Do a binary approximation to get lpj set to
52 + * equal one clock (up to lps_precision bits)
56 + while (lps_precision-- && (loopbit >>= 1)) {
59 + while (ticks == jiffies)
63 + if (jiffies != ticks) /* longer than 1 tick */
66 + printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
68 + for(i=0; i< NR_CPUS; i++)
69 + cpu_data[i].udelay_val = lpj;
73 +device_initcall(udelay_recal);
75 void prom_soc_init(struct ralink_soc_info *soc_info)
77 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
78 --- a/arch/mips/ralink/Kconfig
79 +++ b/arch/mips/ralink/Kconfig
80 @@ -58,6 +58,7 @@ choice
81 select CLKSRC_MIPS_GIC
83 select WEAK_REORDERING_BEYOND_LLSC
84 + select GENERIC_CLOCKEVENTS_BROADCAST
88 --- a/arch/mips/ralink/timer-gic.c
89 +++ b/arch/mips/ralink/timer-gic.c
92 #include <linux/clk-provider.h>
93 #include <linux/clocksource.h>
94 +#include <asm/time.h>
98 @@ -19,6 +20,8 @@ void __init plat_time_init(void)
102 + mips_hpt_frequency = 880000000 / 2;