target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch

   1 From 450b6e8257e22708173d0c1c86d34394fba0c5eb Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:08:31 +0100
   4 Subject: [PATCH 01/53] arch: mips: ralink: add mt7621 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-ralink/irq.h    |    9 +
   9  arch/mips/include/asm/mach-ralink/mt7621.h |   39 ++++
  10  arch/mips/kernel/mips-cm.c                 |    4 +-
  11  arch/mips/kernel/vmlinux.lds.S             |    1 +
  12  arch/mips/ralink/Kconfig                   |   18 ++
  13  arch/mips/ralink/Makefile                  |    7 +-
  14  arch/mips/ralink/Platform                  |    5 +
  15  arch/mips/ralink/irq-gic.c                 |  268 ++++++++++++++++++++++++++++
  16  arch/mips/ralink/malta-amon.c              |   81 +++++++++
  17  arch/mips/ralink/mt7621.c                  |  209 ++++++++++++++++++++++
  18  10 files changed, 638 insertions(+), 3 deletions(-)
  19  create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
  20  create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
  21  create mode 100644 arch/mips/ralink/irq-gic.c
  22  create mode 100644 arch/mips/ralink/malta-amon.c
  23  create mode 100644 arch/mips/ralink/mt7621.c
  24
  25 --- /dev/null
  26 +++ b/arch/mips/include/asm/mach-ralink/irq.h
  27 @@ -0,0 +1,9 @@
  28 +#ifndef __ASM_MACH_RALINK_IRQ_H
  29 +#define __ASM_MACH_RALINK_IRQ_H
  30 +
  31 +#define GIC_NUM_INTRS  64
  32 +#define NR_IRQS 256
  33 +
  34 +#include_next <irq.h>
  35 +
  36 +#endif
  37 --- /dev/null
  38 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
  39 @@ -0,0 +1,39 @@
  40 +/*
  41 + * This program is free software; you can redistribute it and/or modify it
  42 + * under the terms of the GNU General Public License version 2 as published
  43 + * by the Free Software Foundation.
  44 + *
  45 + * Parts of this file are based on Ralink's 2.6.21 BSP
  46 + *
  47 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  48 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  49 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  50 + */
  51 +
  52 +#ifndef _MT7621_REGS_H_
  53 +#define _MT7621_REGS_H_
  54 +
  55 +#define MT7621_SYSC_BASE               0x1E000000
  56 +
  57 +#define SYSC_REG_CHIP_NAME0            0x00
  58 +#define SYSC_REG_CHIP_NAME1            0x04
  59 +#define SYSC_REG_CHIP_REV              0x0c
  60 +#define SYSC_REG_SYSTEM_CONFIG0                0x10
  61 +#define SYSC_REG_SYSTEM_CONFIG1                0x14
  62 +
  63 +#define CHIP_REV_PKG_MASK              0x1
  64 +#define CHIP_REV_PKG_SHIFT             16
  65 +#define CHIP_REV_VER_MASK              0xf
  66 +#define CHIP_REV_VER_SHIFT             8
  67 +#define CHIP_REV_ECO_MASK              0xf
  68 +
  69 +#define MT7621_DRAM_BASE                0x0
  70 +#define MT7621_DDR2_SIZE_MIN           32
  71 +#define MT7621_DDR2_SIZE_MAX           256
  72 +
  73 +#define MT7621_CHIP_NAME0              0x3637544D
  74 +#define MT7621_CHIP_NAME1              0x20203132
  75 +
  76 +#define MIPS_GIC_IRQ_BASE           (MIPS_CPU_IRQ_BASE + 8)
  77 +
  78 +#endif
  79 --- a/arch/mips/kernel/mips-cm.c
  80 +++ b/arch/mips/kernel/mips-cm.c
  81 @@ -232,7 +232,7 @@ int mips_cm_probe(void)
  82         write_gcr_base(base_reg);
  83
  84         /* disable CM regions */
  85 -       write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
  86 +/*     write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
  87         write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
  88         write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
  89         write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
  90 @@ -240,7 +240,7 @@ int mips_cm_probe(void)
  91         write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
  92         write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
  93         write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
  94 -
  95 +*/
  96         /* probe for an L2-only sync region */
  97         mips_cm_probe_l2sync();
  98
  99 --- a/arch/mips/kernel/vmlinux.lds.S
 100 +++ b/arch/mips/kernel/vmlinux.lds.S
 101 @@ -51,6 +51,7 @@ SECTIONS
 102         /* read-only */
 103         _text = .;      /* Text and read-only data */
 104         .text : {
 105 +               /*. = . + 0x8000; */
 106                 TEXT_TEXT
 107                 SCHED_TEXT
 108                 LOCK_TEXT
 109 --- a/arch/mips/ralink/Kconfig
 110 +++ b/arch/mips/ralink/Kconfig
 111 @@ -12,6 +12,11 @@ config RALINK_ILL_ACC
 112         depends on SOC_RT305X
 113         default y
 114
 115 +config IRQ_INTC
 116 +       bool
 117 +       default y
 118 +       depends on !SOC_MT7621
 119 +
 120  choice
 121         prompt "Ralink SoC selection"
 122         default SOC_RT305X
 123 @@ -34,6 +39,14 @@ choice
 124         config SOC_MT7620
 125                 bool "MT7620/8"
 126
 127 +       config SOC_MT7621
 128 +               bool "MT7621"
 129 +               select MIPS_CPU_SCACHE
 130 +               select SYS_SUPPORTS_MULTITHREADING
 131 +               select SYS_SUPPORTS_SMP
 132 +               select SYS_SUPPORTS_MIPS_CPS
 133 +               select MIPS_GIC
 134 +               select HW_HAS_PCI
 135  endchoice
 136
 137  choice
 138 @@ -65,6 +78,10 @@ choice
 139                 depends on SOC_MT7620
 140                 select BUILTIN_DTB
 141
 142 +       config DTB_MT7621_EVAL
 143 +               bool "MT7621 eval kit"
 144 +               depends on SOC_MT7621
 145 +
 146  endchoice
 147
 148  endif
 149 --- a/arch/mips/ralink/Makefile
 150 +++ b/arch/mips/ralink/Makefile
 151 @@ -6,16 +6,20 @@
 152  # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 153  # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 154
 155 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
 156 +obj-y := prom.o of.o reset.o clk.o timer.o
 157
 158  obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
 159
 160  obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
 161
 162 +obj-$(CONFIG_IRQ_INTC) += irq.o
 163 +obj-$(CONFIG_MIPS_GIC) += irq-gic.o
 164 +
 165  obj-$(CONFIG_SOC_RT288X) += rt288x.o
 166  obj-$(CONFIG_SOC_RT305X) += rt305x.o
 167  obj-$(CONFIG_SOC_RT3883) += rt3883.o
 168  obj-$(CONFIG_SOC_MT7620) += mt7620.o
 169 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
 170
 171  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 172
 173 --- a/arch/mips/ralink/Platform
 174 +++ b/arch/mips/ralink/Platform
 175 @@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883)   += -I$(srctr
 176  #
 177  load-$(CONFIG_SOC_MT7620)      += 0xffffffff80000000
 178  cflags-$(CONFIG_SOC_MT7620)    += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
 179 +
 180 +# Ralink MT7621
 181 +#
 182 +load-$(CONFIG_SOC_MT7621)      += 0xffffffff80001000
 183 +cflags-$(CONFIG_SOC_MT7621)    += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
 184 --- /dev/null
 185 +++ b/arch/mips/ralink/irq-gic.c
 186 @@ -0,0 +1,18 @@
 187 +#include <linux/init.h>
 188 +
 189 +#include <linux/of.h>
 190 +#include <linux/irqchip.h>
 191 +
 192 +#include <linux/irqchip/mips-gic.h>
 193 +
 194 +unsigned int get_c0_compare_int(void)
 195 +{
 196 +       return gic_get_c0_compare_int();
 197 +}
 198 +
 199 +void __init
 200 +arch_init_irq(void)
 201 +{
 202 +       irqchip_init();
 203 +}
 204 +
 205 --- /dev/null
 206 +++ b/arch/mips/ralink/mt7621.c
 207 @@ -0,0 +1,213 @@
 208 +/*
 209 + * This program is free software; you can redistribute it and/or modify it
 210 + * under the terms of the GNU General Public License version 2 as published
 211 + * by the Free Software Foundation.
 212 + *
 213 + * Parts of this file are based on Ralink's 2.6.21 BSP
 214 + *
 215 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 216 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 217 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 218 + */
 219 +
 220 +#include <linux/kernel.h>
 221 +#include <linux/init.h>
 222 +#include <linux/module.h>
 223 +
 224 +#include <asm/mipsregs.h>
 225 +#include <asm/smp-ops.h>
 226 +#include <asm/mips-cm.h>
 227 +#include <asm/mips-cpc.h>
 228 +#include <asm/mach-ralink/ralink_regs.h>
 229 +#include <asm/mach-ralink/mt7621.h>
 230 +
 231 +#include <pinmux.h>
 232 +
 233 +#include "common.h"
 234 +
 235 +#define SYSC_REG_SYSCFG                0x10
 236 +#define SYSC_REG_CPLL_CLKCFG0  0x2c
 237 +#define SYSC_REG_CUR_CLK_STS   0x44
 238 +#define CPU_CLK_SEL            (BIT(30) | BIT(31))
 239 +
 240 +#define MT7621_GPIO_MODE_UART1         1
 241 +#define MT7621_GPIO_MODE_I2C           2
 242 +#define MT7621_GPIO_MODE_UART3_MASK    0x3
 243 +#define MT7621_GPIO_MODE_UART3_SHIFT   3
 244 +#define MT7621_GPIO_MODE_UART3_GPIO    1
 245 +#define MT7621_GPIO_MODE_UART2_MASK    0x3
 246 +#define MT7621_GPIO_MODE_UART2_SHIFT   5
 247 +#define MT7621_GPIO_MODE_UART2_GPIO    1
 248 +#define MT7621_GPIO_MODE_JTAG          7
 249 +#define MT7621_GPIO_MODE_WDT_MASK      0x3
 250 +#define MT7621_GPIO_MODE_WDT_SHIFT     8
 251 +#define MT7621_GPIO_MODE_WDT_GPIO      1
 252 +#define MT7621_GPIO_MODE_PCIE_RST      0
 253 +#define MT7621_GPIO_MODE_PCIE_REF      2
 254 +#define MT7621_GPIO_MODE_PCIE_MASK     0x3
 255 +#define MT7621_GPIO_MODE_PCIE_SHIFT    10
 256 +#define MT7621_GPIO_MODE_PCIE_GPIO     1
 257 +#define MT7621_GPIO_MODE_MDIO_MASK     0x3
 258 +#define MT7621_GPIO_MODE_MDIO_SHIFT    12
 259 +#define MT7621_GPIO_MODE_MDIO_GPIO     1
 260 +#define MT7621_GPIO_MODE_RGMII1                14
 261 +#define MT7621_GPIO_MODE_RGMII2                15
 262 +#define MT7621_GPIO_MODE_SPI_MASK      0x3
 263 +#define MT7621_GPIO_MODE_SPI_SHIFT     16
 264 +#define MT7621_GPIO_MODE_SPI_GPIO      1
 265 +#define MT7621_GPIO_MODE_SDHCI_MASK    0x3
 266 +#define MT7621_GPIO_MODE_SDHCI_SHIFT   18
 267 +#define MT7621_GPIO_MODE_SDHCI_GPIO    1
 268 +
 269 +static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };
 270 +static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
 271 +static struct rt2880_pmx_func uart3_grp[] = {
 272 +       FUNC("uart3", 0, 5, 4),
 273 +       FUNC("i2s", 2, 5, 4),
 274 +       FUNC("spdif3", 3, 5, 4),
 275 +};
 276 +static struct rt2880_pmx_func uart2_grp[] = {
 277 +       FUNC("uart2", 0, 9, 4),
 278 +       FUNC("pcm", 2, 9, 4),
 279 +       FUNC("spdif2", 3, 9, 4),
 280 +};
 281 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
 282 +static struct rt2880_pmx_func wdt_grp[] = {
 283 +       FUNC("wdt rst", 0, 18, 1),
 284 +       FUNC("wdt refclk", 2, 18, 1),
 285 +};
 286 +static struct rt2880_pmx_func pcie_rst_grp[] = {
 287 +       FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
 288 +       FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
 289 +};
 290 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
 291 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
 292 +static struct rt2880_pmx_func spi_grp[] = {
 293 +       FUNC("spi", 0, 34, 7),
 294 +       FUNC("nand1", 2, 34, 7),
 295 +};
 296 +static struct rt2880_pmx_func sdhci_grp[] = {
 297 +       FUNC("sdhci", 0, 41, 8),
 298 +       FUNC("nand2", 2, 41, 8),
 299 +};
 300 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
 301 +
 302 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
 303 +       GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
 304 +       GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
 305 +       GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
 306 +               MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
 307 +       GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
 308 +               MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
 309 +       GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
 310 +       GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
 311 +               MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
 312 +       GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
 313 +               MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
 314 +       GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
 315 +               MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
 316 +       GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
 317 +       GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
 318 +               MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
 319 +       GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
 320 +               MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
 321 +       GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
 322 +       { 0 }
 323 +};
 324 +
 325 +phys_addr_t mips_cpc_default_phys_base() {
 326 +       panic("Cannot detect cpc address");
 327 +}
 328 +
 329 +void __init ralink_clk_init(void)
 330 +{
 331 +       int cpu_fdiv = 0;
 332 +       int cpu_ffrac = 0;
 333 +       int fbdiv = 0;
 334 +       u32 clk_sts, syscfg;
 335 +       u8 clk_sel = 0, xtal_mode;
 336 +       u32 cpu_clk;
 337 +
 338 +       if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
 339 +               clk_sel = 1;
 340 +
 341 +       switch (clk_sel) {
 342 +       case 0:
 343 +               clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
 344 +               cpu_fdiv = ((clk_sts >> 8) & 0x1F);
 345 +               cpu_ffrac = (clk_sts & 0x1F);
 346 +               cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
 347 +               break;
 348 +
 349 +       case 1:
 350 +               fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
 351 +               syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
 352 +               xtal_mode = (syscfg >> 6) & 0x7;
 353 +               if(xtal_mode >= 6) { //25Mhz Xtal
 354 +                       cpu_clk = 25 * fbdiv * 1000 * 1000;
 355 +               } else if(xtal_mode >=3) { //40Mhz Xtal
 356 +                       cpu_clk = 40 * fbdiv * 1000 * 1000;
 357 +               } else { // 20Mhz Xtal
 358 +                       cpu_clk = 20 * fbdiv * 1000 * 1000;
 359 +               }
 360 +               break;
 361 +       }
 362 +       cpu_clk = 880000000;
 363 +       ralink_clk_add("cpu", cpu_clk);
 364 +       ralink_clk_add("1e000b00.spi", 50000000);
 365 +       ralink_clk_add("1e000c00.uartlite", 50000000);
 366 +       ralink_clk_add("1e000d00.uart", 50000000);
 367 +}
 368 +
 369 +void __init ralink_of_remap(void)
 370 +{
 371 +       rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
 372 +       rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
 373 +
 374 +       if (!rt_sysc_membase || !rt_memc_membase)
 375 +               panic("Failed to remap core resources");
 376 +}
 377 +
 378 +void prom_soc_init(struct ralink_soc_info *soc_info)
 379 +{
 380 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
 381 +       unsigned char *name = NULL;
 382 +       u32 n0;
 383 +       u32 n1;
 384 +       u32 rev;
 385 +
 386 +       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 387 +       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 388 +
 389 +       if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
 390 +               name = "MT7621";
 391 +               soc_info->compatible = "mtk,mt7621-soc";
 392 +       } else {
 393 +               panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 394 +       }
 395 +
 396 +       rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
 397 +
 398 +       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 399 +               "MediaTek %s ver:%u eco:%u",
 400 +               name,
 401 +               (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
 402 +               (rev & CHIP_REV_ECO_MASK));
 403 +
 404 +       soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
 405 +       soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
 406 +       soc_info->mem_base = MT7621_DRAM_BASE;
 407 +
 408 +       rt2880_pinmux_data = mt7621_pinmux_data;
 409 +
 410 +       /* Early detection of CMP support */
 411 +       mips_cm_probe();
 412 +       mips_cpc_probe();
 413 +
 414 +       if (!register_cps_smp_ops())
 415 +               return;
 416 +       if (!register_cmp_smp_ops())
 417 +               return;
 418 +       if (!register_vsmp_smp_ops())
 419 +               return;
 420 +}
 421 --- a/drivers/irqchip/irq-mips-gic.c
 422 +++ b/drivers/irqchip/irq-mips-gic.c
 423 @@ -862,7 +862,7 @@ void __init gic_init(unsigned long gic_b
 424         __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
 425  }
 426
 427 -static int __init gic_of_init(struct device_node *node,
 428 +int __init gic_of_init(struct device_node *node,
 429                               struct device_node *parent)
 430  {
 431         struct resource res;