target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch

   1 From 450b6e8257e22708173d0c1c86d34394fba0c5eb Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:08:31 +0100
   4 Subject: [PATCH 01/53] arch: mips: ralink: add mt7621 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-ralink/irq.h    |    9 +
   9  arch/mips/include/asm/mach-ralink/mt7621.h |   39 ++++
  10  arch/mips/kernel/mips-cm.c                 |    4 +-
  11  arch/mips/kernel/vmlinux.lds.S             |    1 +
  12  arch/mips/ralink/Kconfig                   |   18 ++
  13  arch/mips/ralink/Makefile                  |    7 +-
  14  arch/mips/ralink/Platform                  |    5 +
  15  arch/mips/ralink/irq-gic.c                 |  268 ++++++++++++++++++++++++++++
  16  arch/mips/ralink/malta-amon.c              |   81 +++++++++
  17  arch/mips/ralink/mt7621.c                  |  209 ++++++++++++++++++++++
  18  10 files changed, 638 insertions(+), 3 deletions(-)
  19  create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
  20  create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
  21  create mode 100644 arch/mips/ralink/irq-gic.c
  22  create mode 100644 arch/mips/ralink/malta-amon.c
  23  create mode 100644 arch/mips/ralink/mt7621.c
  24
  25 --- /dev/null
  26 +++ b/arch/mips/include/asm/mach-ralink/irq.h
  27 @@ -0,0 +1,9 @@
  28 +#ifndef __ASM_MACH_RALINK_IRQ_H
  29 +#define __ASM_MACH_RALINK_IRQ_H
  30 +
  31 +#define GIC_NUM_INTRS  64
  32 +#define NR_IRQS 256
  33 +
  34 +#include_next <irq.h>
  35 +
  36 +#endif
  37 --- /dev/null
  38 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
  39 @@ -0,0 +1,39 @@
  40 +/*
  41 + * This program is free software; you can redistribute it and/or modify it
  42 + * under the terms of the GNU General Public License version 2 as published
  43 + * by the Free Software Foundation.
  44 + *
  45 + * Parts of this file are based on Ralink's 2.6.21 BSP
  46 + *
  47 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  48 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  49 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  50 + */
  51 +
  52 +#ifndef _MT7621_REGS_H_
  53 +#define _MT7621_REGS_H_
  54 +
  55 +#define MT7621_SYSC_BASE               0x1E000000
  56 +
  57 +#define SYSC_REG_CHIP_NAME0            0x00
  58 +#define SYSC_REG_CHIP_NAME1            0x04
  59 +#define SYSC_REG_CHIP_REV              0x0c
  60 +#define SYSC_REG_SYSTEM_CONFIG0                0x10
  61 +#define SYSC_REG_SYSTEM_CONFIG1                0x14
  62 +
  63 +#define CHIP_REV_PKG_MASK              0x1
  64 +#define CHIP_REV_PKG_SHIFT             16
  65 +#define CHIP_REV_VER_MASK              0xf
  66 +#define CHIP_REV_VER_SHIFT             8
  67 +#define CHIP_REV_ECO_MASK              0xf
  68 +
  69 +#define MT7621_DRAM_BASE                0x0
  70 +#define MT7621_DDR2_SIZE_MIN           32
  71 +#define MT7621_DDR2_SIZE_MAX           256
  72 +
  73 +#define MT7621_CHIP_NAME0              0x3637544D
  74 +#define MT7621_CHIP_NAME1              0x20203132
  75 +
  76 +#define MIPS_GIC_IRQ_BASE           (MIPS_CPU_IRQ_BASE + 8)
  77 +
  78 +#endif
  79 --- a/arch/mips/kernel/mips-cm.c
  80 +++ b/arch/mips/kernel/mips-cm.c
  81 @@ -232,7 +232,7 @@ int mips_cm_probe(void)
  82         write_gcr_base(base_reg);
  83
  84         /* disable CM regions */
  85 -       write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
  86 +/*     write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
  87         write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
  88         write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
  89         write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
  90 @@ -240,7 +240,7 @@ int mips_cm_probe(void)
  91         write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
  92         write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
  93         write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
  94 -
  95 +*/
  96         /* probe for an L2-only sync region */
  97         mips_cm_probe_l2sync();
  98
  99 --- a/arch/mips/kernel/vmlinux.lds.S
 100 +++ b/arch/mips/kernel/vmlinux.lds.S
 101 @@ -51,6 +51,7 @@ SECTIONS
 102         /* read-only */
 103         _text = .;      /* Text and read-only data */
 104         .text : {
 105 +               /*. = . + 0x8000; */
 106                 TEXT_TEXT
 107                 SCHED_TEXT
 108                 LOCK_TEXT
 109 --- a/arch/mips/ralink/Kconfig
 110 +++ b/arch/mips/ralink/Kconfig
 111 @@ -12,6 +12,11 @@ config RALINK_ILL_ACC
 112         depends on SOC_RT305X
 113         default y
 114
 115 +config IRQ_INTC
 116 +       bool
 117 +       default y
 118 +       depends on !SOC_MT7621
 119 +
 120  choice
 121         prompt "Ralink SoC selection"
 122         default SOC_RT305X
 123 @@ -34,6 +39,15 @@ choice
 124         config SOC_MT7620
 125                 bool "MT7620/8"
 126
 127 +       config SOC_MT7621
 128 +               bool "MT7621"
 129 +               select MIPS_CPU_SCACHE
 130 +               select SYS_SUPPORTS_MULTITHREADING
 131 +               select SYS_SUPPORTS_SMP
 132 +               select SYS_SUPPORTS_MIPS_CMP
 133 +               select MIPS_GIC
 134 +               select IRQ_GIC
 135 +               select HW_HAS_PCI
 136  endchoice
 137
 138  choice
 139 @@ -65,6 +79,10 @@ choice
 140                 depends on SOC_MT7620
 141                 select BUILTIN_DTB
 142
 143 +       config DTB_MT7621_EVAL
 144 +               bool "MT7621 eval kit"
 145 +               depends on SOC_MT7621
 146 +
 147  endchoice
 148
 149  endif
 150 --- a/arch/mips/ralink/Makefile
 151 +++ b/arch/mips/ralink/Makefile
 152 @@ -6,16 +6,21 @@
 153  # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 154  # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 155
 156 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
 157 +obj-y := prom.o of.o reset.o clk.o timer.o
 158
 159  obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
 160
 161  obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
 162
 163 +obj-$(CONFIG_IRQ_INTC) += irq.o
 164 +obj-$(CONFIG_MIPS_GIC_IPI) += irq-gic.o
 165 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
 166 +
 167  obj-$(CONFIG_SOC_RT288X) += rt288x.o
 168  obj-$(CONFIG_SOC_RT305X) += rt305x.o
 169  obj-$(CONFIG_SOC_RT3883) += rt3883.o
 170  obj-$(CONFIG_SOC_MT7620) += mt7620.o
 171 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
 172
 173  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 174
 175 --- a/arch/mips/ralink/Platform
 176 +++ b/arch/mips/ralink/Platform
 177 @@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883)   += -I$(srctr
 178  #
 179  load-$(CONFIG_SOC_MT7620)      += 0xffffffff80000000
 180  cflags-$(CONFIG_SOC_MT7620)    += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
 181 +
 182 +# Ralink MT7621
 183 +#
 184 +load-$(CONFIG_SOC_MT7621)      += 0xffffffff80001000
 185 +cflags-$(CONFIG_SOC_MT7621)    += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
 186 --- /dev/null
 187 +++ b/arch/mips/ralink/irq-gic.c
 188 @@ -0,0 +1,42 @@
 189 +#include <linux/init.h>
 190 +#include <linux/sched.h>
 191 +#include <linux/slab.h>
 192 +#include <linux/interrupt.h>
 193 +#include <linux/kernel_stat.h>
 194 +#include <linux/hardirq.h>
 195 +#include <linux/preempt.h>
 196 +#include <linux/irqdomain.h>
 197 +#include <linux/of_platform.h>
 198 +#include <linux/of_address.h>
 199 +#include <linux/of_irq.h>
 200 +
 201 +#include <asm/irq_cpu.h>
 202 +#include <asm/mipsregs.h>
 203 +
 204 +#include <asm/irq.h>
 205 +#include <asm/setup.h>
 206 +
 207 +#include <asm/mips-cm.h>
 208 +#include <linux/irqchip/mips-gic.h>
 209 +
 210 +#include <asm/mach-ralink/mt7621.h>
 211 +
 212 +extern int __init gic_of_init(struct device_node *node,
 213 +                             struct device_node *parent);
 214 +
 215 +unsigned int get_c0_compare_int(void)
 216 +{
 217 +       return gic_get_c0_compare_int();
 218 +}
 219 +
 220 +static struct of_device_id __initdata of_irq_ids[] = {
 221 +       { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
 222 +       { .compatible = "mti,gic", .data = gic_of_init },
 223 +       {},
 224 +};
 225 +
 226 +void __init
 227 +arch_init_irq(void)
 228 +{
 229 +       of_irq_init(of_irq_ids);
 230 +}
 231 --- /dev/null
 232 +++ b/arch/mips/ralink/malta-amon.c
 233 @@ -0,0 +1,81 @@
 234 +/*
 235 + * Copyright (C) 2007  MIPS Technologies, Inc.
 236 + *     All rights reserved.
 237 +
 238 + *  This program is free software; you can distribute it and/or modify it
 239 + *  under the terms of the GNU General Public License (Version 2) as
 240 + *  published by the Free Software Foundation.
 241 + *
 242 + *  This program is distributed in the hope it will be useful, but WITHOUT
 243 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 244 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 245 + *  for more details.
 246 + *
 247 + *  You should have received a copy of the GNU General Public License along
 248 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 249 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 250 + *
 251 + * Arbitrary Monitor interface
 252 + */
 253 +
 254 +#include <linux/kernel.h>
 255 +#include <linux/init.h>
 256 +#include <linux/smp.h>
 257 +
 258 +#include <asm/addrspace.h>
 259 +#include <asm/mips-boards/launch.h>
 260 +#include <asm/mipsmtregs.h>
 261 +
 262 +int amon_cpu_avail(int cpu)
 263 +{
 264 +       struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
 265 +
 266 +       if (cpu < 0 || cpu >= NCPULAUNCH) {
 267 +               pr_debug("avail: cpu%d is out of range\n", cpu);
 268 +               return 0;
 269 +       }
 270 +
 271 +       launch += cpu;
 272 +       if (!(launch->flags & LAUNCH_FREADY)) {
 273 +               pr_debug("avail: cpu%d is not ready\n", cpu);
 274 +               return 0;
 275 +       }
 276 +       if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
 277 +               pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
 278 +               return 0;
 279 +       }
 280 +
 281 +       return 1;
 282 +}
 283 +
 284 +void amon_cpu_start(int cpu,
 285 +                   unsigned long pc, unsigned long sp,
 286 +                   unsigned long gp, unsigned long a0)
 287 +{
 288 +       volatile struct cpulaunch *launch =
 289 +               (struct cpulaunch  *)CKSEG0ADDR(CPULAUNCH);
 290 +
 291 +       if (!amon_cpu_avail(cpu))
 292 +               return;
 293 +       if (cpu == smp_processor_id()) {
 294 +               pr_debug("launch: I am cpu%d!\n", cpu);
 295 +               return;
 296 +       }
 297 +       launch += cpu;
 298 +
 299 +       pr_debug("launch: starting cpu%d\n", cpu);
 300 +
 301 +       launch->pc = pc;
 302 +       launch->gp = gp;
 303 +       launch->sp = sp;
 304 +       launch->a0 = a0;
 305 +
 306 +       smp_wmb();              /* Target must see parameters before go */
 307 +       launch->flags |= LAUNCH_FGO;
 308 +       smp_wmb();              /* Target must see go before we poll  */
 309 +
 310 +       while ((launch->flags & LAUNCH_FGONE) == 0)
 311 +               ;
 312 +       smp_rmb();      /* Target will be updating flags soon */
 313 +       pr_debug("launch: cpu%d gone!\n", cpu);
 314 +}
 315 --- /dev/null
 316 +++ b/arch/mips/ralink/mt7621.c
 317 @@ -0,0 +1,209 @@
 318 +/*
 319 + * This program is free software; you can redistribute it and/or modify it
 320 + * under the terms of the GNU General Public License version 2 as published
 321 + * by the Free Software Foundation.
 322 + *
 323 + * Parts of this file are based on Ralink's 2.6.21 BSP
 324 + *
 325 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 326 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 327 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 328 + */
 329 +
 330 +#include <linux/kernel.h>
 331 +#include <linux/init.h>
 332 +#include <linux/module.h>
 333 +
 334 +#include <asm/mipsregs.h>
 335 +#include <asm/smp-ops.h>
 336 +#include <asm/mips-cm.h>
 337 +#include <asm/mips-cpc.h>
 338 +#include <asm/mach-ralink/ralink_regs.h>
 339 +#include <asm/mach-ralink/mt7621.h>
 340 +
 341 +#include <pinmux.h>
 342 +
 343 +#include "common.h"
 344 +
 345 +#define SYSC_REG_SYSCFG                0x10
 346 +#define SYSC_REG_CPLL_CLKCFG0  0x2c
 347 +#define SYSC_REG_CUR_CLK_STS   0x44
 348 +#define CPU_CLK_SEL            (BIT(30) | BIT(31))
 349 +
 350 +#define MT7621_GPIO_MODE_UART1         1
 351 +#define MT7621_GPIO_MODE_I2C           2
 352 +#define MT7621_GPIO_MODE_UART3_MASK    0x3
 353 +#define MT7621_GPIO_MODE_UART3_SHIFT   3
 354 +#define MT7621_GPIO_MODE_UART3_GPIO    1
 355 +#define MT7621_GPIO_MODE_UART2_MASK    0x3
 356 +#define MT7621_GPIO_MODE_UART2_SHIFT   5
 357 +#define MT7621_GPIO_MODE_UART2_GPIO    1
 358 +#define MT7621_GPIO_MODE_JTAG          7
 359 +#define MT7621_GPIO_MODE_WDT_MASK      0x3
 360 +#define MT7621_GPIO_MODE_WDT_SHIFT     8
 361 +#define MT7621_GPIO_MODE_WDT_GPIO      1
 362 +#define MT7621_GPIO_MODE_PCIE_RST      0
 363 +#define MT7621_GPIO_MODE_PCIE_REF      2
 364 +#define MT7621_GPIO_MODE_PCIE_MASK     0x3
 365 +#define MT7621_GPIO_MODE_PCIE_SHIFT    10
 366 +#define MT7621_GPIO_MODE_PCIE_GPIO     1
 367 +#define MT7621_GPIO_MODE_MDIO_MASK     0x3
 368 +#define MT7621_GPIO_MODE_MDIO_SHIFT    12
 369 +#define MT7621_GPIO_MODE_MDIO_GPIO     1
 370 +#define MT7621_GPIO_MODE_RGMII1                14
 371 +#define MT7621_GPIO_MODE_RGMII2                15
 372 +#define MT7621_GPIO_MODE_SPI_MASK      0x3
 373 +#define MT7621_GPIO_MODE_SPI_SHIFT     16
 374 +#define MT7621_GPIO_MODE_SPI_GPIO      1
 375 +#define MT7621_GPIO_MODE_SDHCI_MASK    0x3
 376 +#define MT7621_GPIO_MODE_SDHCI_SHIFT   18
 377 +#define MT7621_GPIO_MODE_SDHCI_GPIO    1
 378 +
 379 +static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };
 380 +static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
 381 +static struct rt2880_pmx_func uart3_grp[] = {
 382 +       FUNC("uart3", 0, 5, 4),
 383 +       FUNC("i2s", 2, 5, 4),
 384 +       FUNC("spdif3", 3, 5, 4),
 385 +};
 386 +static struct rt2880_pmx_func uart2_grp[] = {
 387 +       FUNC("uart2", 0, 9, 4),
 388 +       FUNC("pcm", 2, 9, 4),
 389 +       FUNC("spdif2", 3, 9, 4),
 390 +};
 391 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
 392 +static struct rt2880_pmx_func wdt_grp[] = {
 393 +       FUNC("wdt rst", 0, 18, 1),
 394 +       FUNC("wdt refclk", 2, 18, 1),
 395 +};
 396 +static struct rt2880_pmx_func pcie_rst_grp[] = {
 397 +       FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
 398 +       FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
 399 +};
 400 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
 401 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
 402 +static struct rt2880_pmx_func spi_grp[] = {
 403 +       FUNC("spi", 0, 34, 7),
 404 +       FUNC("nand1", 2, 34, 7),
 405 +};
 406 +static struct rt2880_pmx_func sdhci_grp[] = {
 407 +       FUNC("sdhci", 0, 41, 8),
 408 +       FUNC("nand2", 2, 41, 8),
 409 +};
 410 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
 411 +
 412 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
 413 +       GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
 414 +       GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
 415 +       GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
 416 +               MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
 417 +       GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
 418 +               MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
 419 +       GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
 420 +       GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
 421 +               MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
 422 +       GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
 423 +               MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
 424 +       GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
 425 +               MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
 426 +       GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
 427 +       GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
 428 +               MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
 429 +       GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
 430 +               MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
 431 +       GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
 432 +       { 0 }
 433 +};
 434 +
 435 +void __init ralink_clk_init(void)
 436 +{
 437 +       int cpu_fdiv = 0;
 438 +       int cpu_ffrac = 0;
 439 +       int fbdiv = 0;
 440 +       u32 clk_sts, syscfg;
 441 +       u8 clk_sel = 0, xtal_mode;
 442 +       u32 cpu_clk;
 443 +
 444 +       if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
 445 +               clk_sel = 1;
 446 +
 447 +       switch (clk_sel) {
 448 +       case 0:
 449 +               clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
 450 +               cpu_fdiv = ((clk_sts >> 8) & 0x1F);
 451 +               cpu_ffrac = (clk_sts & 0x1F);
 452 +               cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
 453 +               break;
 454 +
 455 +       case 1:
 456 +               fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
 457 +               syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
 458 +               xtal_mode = (syscfg >> 6) & 0x7;
 459 +               if(xtal_mode >= 6) { //25Mhz Xtal
 460 +                       cpu_clk = 25 * fbdiv * 1000 * 1000;
 461 +               } else if(xtal_mode >=3) { //40Mhz Xtal
 462 +                       cpu_clk = 40 * fbdiv * 1000 * 1000;
 463 +               } else { // 20Mhz Xtal
 464 +                       cpu_clk = 20 * fbdiv * 1000 * 1000;
 465 +               }
 466 +               break;
 467 +       }
 468 +       cpu_clk = 880000000;
 469 +       ralink_clk_add("cpu", cpu_clk);
 470 +       ralink_clk_add("1e000b00.spi", 50000000);
 471 +       ralink_clk_add("1e000c00.uartlite", 50000000);
 472 +       ralink_clk_add("1e000d00.uart", 50000000);
 473 +}
 474 +
 475 +void __init ralink_of_remap(void)
 476 +{
 477 +       rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
 478 +       rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
 479 +
 480 +       if (!rt_sysc_membase || !rt_memc_membase)
 481 +               panic("Failed to remap core resources");
 482 +}
 483 +
 484 +void prom_soc_init(struct ralink_soc_info *soc_info)
 485 +{
 486 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
 487 +       unsigned char *name = NULL;
 488 +       u32 n0;
 489 +       u32 n1;
 490 +       u32 rev;
 491 +
 492 +       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 493 +       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 494 +
 495 +       if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
 496 +               name = "MT7621";
 497 +               soc_info->compatible = "mtk,mt7621-soc";
 498 +       } else {
 499 +               panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 500 +       }
 501 +
 502 +       rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
 503 +
 504 +       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 505 +               "MediaTek %s ver:%u eco:%u",
 506 +               name,
 507 +               (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
 508 +               (rev & CHIP_REV_ECO_MASK));
 509 +
 510 +       soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
 511 +       soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
 512 +       soc_info->mem_base = MT7621_DRAM_BASE;
 513 +
 514 +       rt2880_pinmux_data = mt7621_pinmux_data;
 515 +
 516 +       /* Early detection of CMP support */
 517 +       mips_cm_probe();
 518 +       mips_cpc_probe();
 519 +
 520 +       if (!register_cps_smp_ops())
 521 +               return;
 522 +       if (!register_cmp_smp_ops())
 523 +               return;
 524 +       if (!register_vsmp_smp_ops())
 525 +               return;
 526 +}
 527 --- a/drivers/irqchip/irq-mips-gic.c
 528 +++ b/drivers/irqchip/irq-mips-gic.c
 529 @@ -862,7 +862,7 @@ void __init gic_init(unsigned long gic_b
 530         __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
 531  }
 532
 533 -static int __init gic_of_init(struct device_node *node,
 534 +int __init gic_of_init(struct device_node *node,
 535                               struct device_node *parent)
 536  {
 537         struct resource res;