1 From a10fc0cb650be725157eca50e2ceb34efc281ac2 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH 29/53] phy: usb: add ralink phy
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/phy/Kconfig | 5 ++
9 drivers/phy/Makefile | 1 +
10 drivers/phy/phy-ralink-usb.c | 175 ++++++++++++++++++++++++++++++++++++++++++
11 3 files changed, 181 insertions(+)
12 create mode 100644 drivers/phy/phy-ralink-usb.c
14 diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
15 index 47da573..96ef184 100644
16 --- a/drivers/phy/Kconfig
17 +++ b/drivers/phy/Kconfig
18 @@ -331,6 +331,11 @@ config PHY_XGENE
20 This option enables support for APM X-Gene SoC multi-purpose PHY.
22 +config PHY_RALINK_USB
23 + tristate "Ralink USB PHY driver"
27 config PHY_STIH407_USB
28 tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family"
29 depends on RESET_CONTROLLER
30 diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
31 index a5b18c1..8dbf6cc 100644
32 --- a/drivers/phy/Makefile
33 +++ b/drivers/phy/Makefile
34 @@ -46,3 +46,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
35 obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
36 obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
37 obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
38 +obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
39 diff --git a/drivers/phy/phy-ralink-usb.c b/drivers/phy/phy-ralink-usb.c
41 index 0000000..6c74954
43 +++ b/drivers/phy/phy-ralink-usb.c
46 + * Allwinner ralink USB phy driver
48 + * Copyright (C) 2014 John Crispin <blogic@openwrt.org>
50 + * Based on code from
51 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
53 + * This program is free software; you can redistribute it and/or modify
54 + * it under the terms of the GNU General Public License as published by
55 + * the Free Software Foundation; either version 2 of the License, or
56 + * (at your option) any later version.
58 + * This program is distributed in the hope that it will be useful,
59 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
60 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
61 + * GNU General Public License for more details.
64 +#include <linux/delay.h>
65 +#include <linux/err.h>
66 +#include <linux/io.h>
67 +#include <linux/kernel.h>
68 +#include <linux/module.h>
69 +#include <linux/mutex.h>
70 +#include <linux/phy/phy.h>
71 +#include <linux/platform_device.h>
72 +#include <linux/reset.h>
73 +#include <linux/of_platform.h>
75 +#include <asm/mach-ralink/ralink_regs.h>
77 +#define RT_SYSC_REG_SYSCFG1 0x014
78 +#define RT_SYSC_REG_CLKCFG1 0x030
79 +#define RT_SYSC_REG_USB_PHY_CFG 0x05c
81 +#define RT_RSTCTRL_UDEV BIT(25)
82 +#define RT_RSTCTRL_UHST BIT(22)
83 +#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
85 +#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
86 +#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
87 +#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
88 +#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
90 +#define USB_PHY_UTMI_8B60M BIT(1)
91 +#define UDEV_WAKEUP BIT(0)
93 +static atomic_t usb_pwr_ref = ATOMIC_INIT(0);
94 +static struct reset_control *rstdev;
95 +static struct reset_control *rsthost;
97 +static struct phy *rt_phy;
99 +static void usb_phy_enable(int state)
102 + rt_sysc_m32(0, phy_clk, RT_SYSC_REG_CLKCFG1);
104 + rt_sysc_m32(phy_clk, 0, RT_SYSC_REG_CLKCFG1);
108 +static int ralink_usb_phy_init(struct phy *_phy)
113 +static int ralink_usb_phy_exit(struct phy *_phy)
118 +static int ralink_usb_phy_power_on(struct phy *_phy)
120 + if (atomic_inc_return(&usb_pwr_ref) == 1) {
127 + rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
128 + if (!IS_ERR(rsthost))
129 + reset_control_deassert(rsthost);
130 + if (!IS_ERR(rstdev))
131 + reset_control_deassert(rstdev);
133 + rt_sysc_m32(RT_SYSCFG1_USB0_HOST_MODE, 0, RT_SYSC_REG_SYSCFG1);
134 + if (!IS_ERR(rstdev))
135 + reset_control_deassert(rstdev);
139 + t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
140 + dev_info(&_phy->dev, "remote usb device wakeup %s\n",
141 + (t & UDEV_WAKEUP) ? ("enabbled") : ("disabled"));
142 + if (t & USB_PHY_UTMI_8B60M)
143 + dev_info(&_phy->dev, "UTMI 8bit 60MHz\n");
145 + dev_info(&_phy->dev, "UTMI 16bit 30MHz\n");
151 +static int ralink_usb_phy_power_off(struct phy *_phy)
153 + if (atomic_dec_return(&usb_pwr_ref) == 0) {
155 + if (!IS_ERR(rstdev))
156 + reset_control_assert(rstdev);
157 + if (!IS_ERR(rsthost))
158 + reset_control_assert(rsthost);
164 +static struct phy_ops ralink_usb_phy_ops = {
165 + .init = ralink_usb_phy_init,
166 + .exit = ralink_usb_phy_exit,
167 + .power_on = ralink_usb_phy_power_on,
168 + .power_off = ralink_usb_phy_power_off,
169 + .owner = THIS_MODULE,
172 +static struct phy *ralink_usb_phy_xlate(struct device *dev,
173 + struct of_phandle_args *args)
178 +static const struct of_device_id ralink_usb_phy_of_match[] = {
179 + { .compatible = "ralink,rt3xxx-usbphy", .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | RT_CLKCFG1_UPHY0_CLK_EN) },
180 + { .compatible = "ralink,mt7620a-usbphy", .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN | MT7620_CLKCFG1_UPHY0_CLK_EN) },
183 +MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
185 +static int ralink_usb_phy_probe(struct platform_device *pdev)
187 + struct device *dev = &pdev->dev;
188 + struct phy_provider *phy_provider;
189 + const struct of_device_id *match;
191 + match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
192 + phy_clk = (int) match->data;
194 + rsthost = devm_reset_control_get(&pdev->dev, "host");
195 + rstdev = devm_reset_control_get(&pdev->dev, "device");
197 + rt_phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
198 + if (IS_ERR(rt_phy)) {
199 + dev_err(dev, "failed to create PHY\n");
200 + return PTR_ERR(rt_phy);
203 + phy_provider = devm_of_phy_provider_register(dev, ralink_usb_phy_xlate);
205 + return PTR_ERR_OR_ZERO(phy_provider);
208 +static struct platform_driver ralink_usb_phy_driver = {
209 + .probe = ralink_usb_phy_probe,
211 + .of_match_table = ralink_usb_phy_of_match,
212 + .name = "ralink-usb-phy",
215 +module_platform_driver(ralink_usb_phy_driver);
217 +MODULE_DESCRIPTION("Ralink USB phy driver");
218 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
219 +MODULE_LICENSE("GPL v2");