17ff8d2bb231561b18cdbc184b851084c59050e3
[openwrt/staging/chunkeey.git] / target / linux / ramips / patches-4.3 / 0045-i2c-add-mt7621-driver.patch
1 From d5c54ff3d1db0a4348fa04d8e78f3bf6063e3afc Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 7 Dec 2015 17:21:27 +0100
4 Subject: [PATCH 45/53] i2c: add mt7621 driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/i2c/busses/Kconfig | 4 +
9 drivers/i2c/busses/Makefile | 1 +
10 drivers/i2c/busses/i2c-mt7621.c | 303 +++++++++++++++++++++++++++++++++++++++
11 3 files changed, 308 insertions(+)
12 create mode 100644 drivers/i2c/busses/i2c-mt7621.c
13
14 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
15 index 53d565b..073bfe3 100644
16 --- a/drivers/i2c/busses/Kconfig
17 +++ b/drivers/i2c/busses/Kconfig
18 @@ -807,6 +807,10 @@ config I2C_RALINK
19 tristate "Ralink I2C Controller"
20 select OF_I2C
21
22 +config I2C_MT7621
23 + tristate "MT7621 I2C Controller"
24 + select OF_I2C
25 +
26 config HAVE_S3C2410_I2C
27 bool
28 help
29 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
30 index 2edd32c..764e16e 100644
31 --- a/drivers/i2c/busses/Makefile
32 +++ b/drivers/i2c/busses/Makefile
33 @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
34 obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
35 obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
36 obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
37 +obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o
38 obj-$(CONFIG_I2C_QUP) += i2c-qup.o
39 obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
40 obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
41 diff --git a/drivers/i2c/busses/i2c-mt7621.c b/drivers/i2c/busses/i2c-mt7621.c
42 new file mode 100644
43 index 0000000..646ca40
44 --- /dev/null
45 +++ b/drivers/i2c/busses/i2c-mt7621.c
46 @@ -0,0 +1,303 @@
47 +/*
48 + * drivers/i2c/busses/i2c-mt7621.c
49 + *
50 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
51 + *
52 + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
53 + * (C) 2014 Sittisak <sittisaks@hotmail.com>
54 + *
55 + * This software is licensed under the terms of the GNU General Public
56 + * License version 2, as published by the Free Software Foundation, and
57 + * may be copied, distributed, and modified under those terms.
58 + *
59 + * This program is distributed in the hope that it will be useful,
60 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
61 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
62 + * GNU General Public License for more details.
63 + *
64 + */
65 +
66 +#include <linux/interrupt.h>
67 +#include <linux/kernel.h>
68 +#include <linux/module.h>
69 +#include <linux/reset.h>
70 +#include <linux/delay.h>
71 +#include <linux/slab.h>
72 +#include <linux/init.h>
73 +#include <linux/errno.h>
74 +#include <linux/platform_device.h>
75 +#include <linux/i2c.h>
76 +#include <linux/io.h>
77 +#include <linux/err.h>
78 +
79 +#include <asm/mach-ralink/ralink_regs.h>
80 +
81 +#define REG_CONFIG_REG 0x00
82 +#define REG_CLKDIV_REG 0x04
83 +#define REG_DEVADDR_REG 0x08
84 +#define REG_ADDR_REG 0x0C
85 +#define REG_DATAOUT_REG 0x10
86 +#define REG_DATAIN_REG 0x14
87 +#define REG_STATUS_REG 0x18
88 +#define REG_STARTXFR_REG 0x1C
89 +#define REG_BYTECNT_REG 0x20
90 +#define REG_SM0_IS_AUTOMODE 0x28
91 +#define REG_SM0CTL0 0x40
92 +
93 +
94 +#define I2C_STARTERR 0x10
95 +#define I2C_ACKERR 0x08
96 +#define I2C_DATARDY 0x04
97 +#define I2C_SDOEMPTY 0x02
98 +#define I2C_BUSY 0x01
99 +
100 +/* I2C_CFG register bit field */
101 +#define I2C_CFG_ADDRLEN_8 (7<<5) /* 8 bits */
102 +#define I2C_CFG_DEVADLEN_7 (6<<2)
103 +#define I2C_CFG_ADDRDIS BIT(1)
104 +#define I2C_CFG_DEVADDIS BIT(0)
105 +
106 +#define I2C_CFG_DEFAULT (I2C_CFG_ADDRLEN_8 | \
107 + I2C_CFG_DEVADLEN_7 | \
108 + I2C_CFG_ADDRDIS)
109 +
110 +#define I2C_RETRY 0x1000
111 +
112 +#define CLKDIV_VALUE 333
113 +#define i2c_busy_loop (CLKDIV_VALUE*30)
114 +
115 +#define READ_CMD 0x01
116 +#define WRITE_CMD 0x00
117 +#define READ_BLOCK 16
118 +
119 +#define SM0_ODRAIN BIT(31)
120 +#define SM0_VSYNC_MODE BIT(28)
121 +#define SM0_CLK_DIV (CLKDIV_VALUE << 16)
122 +#define SM0_WAIT_LEVEL BIT(6)
123 +#define SM0_EN BIT(1)
124 +
125 +#define SM0_CFG_DEFUALT (SM0_ODRAIN | SM0_VSYNC_MODE | \
126 + SM0_CLK_DIV | SM0_WAIT_LEVEL | \
127 + SM0_EN)
128 +/***********************************************************/
129 +
130 +static void __iomem *membase;
131 +static struct i2c_adapter *adapter;
132 +
133 +static void rt_i2c_w32(u32 val, unsigned reg)
134 +{
135 + iowrite32(val, membase + reg);
136 +}
137 +
138 +static u32 rt_i2c_r32(unsigned reg)
139 +{
140 + return ioread32(membase + reg);
141 +}
142 +
143 +static void mt7621_i2c_reset(struct i2c_adapter *a)
144 +{
145 + device_reset(a->dev.parent);
146 +}
147 +static void mt7621_i2c_enable(struct i2c_msg *msg)
148 +{
149 + rt_i2c_w32(msg->addr,REG_DEVADDR_REG);
150 + rt_i2c_w32(0,REG_ADDR_REG);
151 +}
152 +
153 +static void i2c_master_init(struct i2c_adapter *a)
154 +{
155 + mt7621_i2c_reset(a);
156 + rt_i2c_w32(I2C_CFG_DEFAULT,REG_CONFIG_REG);
157 + rt_i2c_w32(SM0_CFG_DEFUALT,REG_SM0CTL0);
158 + rt_i2c_w32(1,REG_SM0_IS_AUTOMODE);//auto mode
159 +}
160 +
161 +
162 +static inline int rt_i2c_wait_rx_done(void)
163 +{
164 + int i=0;
165 + while((!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY)) && (i<i2c_busy_loop))
166 + i++;
167 + if(i>=i2c_busy_loop){
168 + pr_err("err,wait for idle timeout");
169 + return -ETIMEDOUT;
170 + }
171 + return 0;
172 +}
173 +
174 +static inline int rt_i2c_wait_idle(void)
175 +{
176 + int i=0;
177 + while((rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY) && (i<i2c_busy_loop))
178 + i++;
179 + if(i>=i2c_busy_loop){
180 + pr_err("err,wait for idle timeout");
181 + return -ETIMEDOUT;
182 + }
183 + return 0;
184 +}
185 +
186 +static inline int rt_i2c_wait_tx_done(void)
187 +{
188 + int i=0;
189 + while((!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY)) && (i<i2c_busy_loop))
190 + i++;
191 + if(i>=i2c_busy_loop){
192 + pr_err("err,wait for idle timeout");
193 + return -ETIMEDOUT;
194 + }
195 + return 0;
196 +}
197 +
198 +static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
199 +{
200 + int i = 0, j = 0, pos = 0;
201 + int nblock = msg->len / READ_BLOCK;
202 + int rem = msg->len % READ_BLOCK;
203 +
204 + if (msg->flags & I2C_M_TEN) {
205 + printk("10 bits addr not supported\n");
206 + return -EINVAL;
207 + }
208 +
209 + if (msg->flags & I2C_M_RD) {
210 + for (i = 0; i < nblock; i++) {
211 + if (rt_i2c_wait_idle())
212 + goto err_timeout;
213 + rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
214 + rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
215 + for (j = 0; j < READ_BLOCK; j++) {
216 + if (rt_i2c_wait_rx_done())
217 + goto err_timeout;
218 + msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
219 + }
220 + }
221 +
222 + if (rt_i2c_wait_idle())
223 + goto err_timeout;
224 + rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
225 + rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
226 +
227 + for (i = 0; i < rem; i++) {
228 + if (rt_i2c_wait_rx_done())
229 + goto err_timeout;
230 + msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
231 + }
232 + } else {
233 + if (rt_i2c_wait_idle())
234 + goto err_timeout;
235 + rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
236 + for (i = 0; i < msg->len; i++) {
237 + rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
238 + if(i == 0)
239 + rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
240 +
241 + if (rt_i2c_wait_tx_done())
242 + goto err_timeout;
243 + }
244 + }
245 +
246 + return 0;
247 +err_timeout:
248 + return -ETIMEDOUT;
249 +}
250 +
251 +static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
252 +{
253 + int i = 0;
254 + int ret = 0;
255 + i2c_master_init(a);
256 + mt7621_i2c_enable(m);
257 +
258 + for (i = 0; i != n && ret==0; i++) {
259 + ret = rt_i2c_handle_msg(a, &m[i]);
260 + if (ret)
261 + return ret;
262 + }
263 + return i;
264 +}
265 +
266 +static u32 rt_i2c_func(struct i2c_adapter *a)
267 +{
268 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
269 +}
270 +
271 +static const struct i2c_algorithm rt_i2c_algo = {
272 + .master_xfer = rt_i2c_master_xfer,
273 + .functionality = rt_i2c_func,
274 +};
275 +
276 +static int rt_i2c_probe(struct platform_device *pdev)
277 +{
278 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
279 + int ret;
280 +
281 + adapter = devm_kzalloc(&pdev->dev,sizeof(struct i2c_adapter), GFP_KERNEL);
282 + if (!adapter) {
283 + dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
284 + return -ENOMEM;
285 + }
286 + membase = devm_ioremap_resource(&pdev->dev, res);
287 + if (IS_ERR(membase))
288 + return PTR_ERR(membase);
289 +
290 + strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
291 +
292 + adapter->owner = THIS_MODULE;
293 + adapter->nr = pdev->id;
294 + adapter->timeout = HZ;
295 + adapter->algo = &rt_i2c_algo;
296 + adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
297 + adapter->dev.parent = &pdev->dev;
298 + adapter->dev.of_node = pdev->dev.of_node;
299 +
300 + platform_set_drvdata(pdev, adapter);
301 +
302 + ret = i2c_add_numbered_adapter(adapter);
303 + if (ret)
304 + return ret;
305 +
306 + dev_info(&pdev->dev,"loaded");
307 +
308 + return 0;
309 +}
310 +
311 +static int rt_i2c_remove(struct platform_device *pdev)
312 +{
313 + platform_set_drvdata(pdev, NULL);
314 + return 0;
315 +}
316 +
317 +static const struct of_device_id i2c_rt_dt_ids[] = {
318 + { .compatible = "ralink,i2c-mt7621", },
319 + { /* sentinel */ }
320 +};
321 +
322 +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
323 +
324 +static struct platform_driver rt_i2c_driver = {
325 + .probe = rt_i2c_probe,
326 + .remove = rt_i2c_remove,
327 + .driver = {
328 + .owner = THIS_MODULE,
329 + .name = "i2c-mt7621",
330 + .of_match_table = i2c_rt_dt_ids,
331 + },
332 +};
333 +
334 +static int __init i2c_rt_init (void)
335 +{
336 + return platform_driver_register(&rt_i2c_driver);
337 +}
338 +
339 +static void __exit i2c_rt_exit (void)
340 +{
341 + platform_driver_unregister(&rt_i2c_driver);
342 +}
343 +module_init (i2c_rt_init);
344 +module_exit (i2c_rt_exit);
345 +
346 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
347 +MODULE_DESCRIPTION("MT7621 I2c host driver");
348 +MODULE_LICENSE("GPL");
349 +MODULE_ALIAS("platform:MT7621-I2C");
350 --
351 1.7.10.4
352