1 From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 13 Nov 2014 19:08:40 +0100
4 Subject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/mmc/host/Kconfig | 2 +
9 drivers/mmc/host/Makefile | 1 +
10 drivers/mmc/host/mtk-mmc/Kconfig | 16 +
11 drivers/mmc/host/mtk-mmc/Makefile | 42 +
12 drivers/mmc/host/mtk-mmc/board.h | 137 ++
13 drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++
14 drivers/mmc/host/mtk-mmc/dbg.h | 156 ++
15 drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
16 drivers/mmc/host/mtk-mmc/sd.c | 3060 ++++++++++++++++++++++++++++++++++
17 9 files changed, 4762 insertions(+)
18 create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
19 create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
20 create mode 100644 drivers/mmc/host/mtk-mmc/board.h
21 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
22 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
23 create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
24 create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
26 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
27 index 8a1e349..47833d1 100644
28 --- a/drivers/mmc/host/Kconfig
29 +++ b/drivers/mmc/host/Kconfig
30 @@ -793,3 +793,5 @@ config MMC_MTK
31 If you have a machine with a integrated SD/MMC card reader, say Y or M here.
32 This is needed if support for any SD/SDIO/MMC devices is required.
35 +source "drivers/mmc/host/mtk-mmc/Kconfig"
36 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
37 index 4f3452a..69dd05f 100644
38 --- a/drivers/mmc/host/Makefile
39 +++ b/drivers/mmc/host/Makefile
41 # Makefile for MMC/SD host controller drivers
44 +obj-$(CONFIG_MTK_MMC) += mtk-mmc/
45 obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
46 obj-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
47 obj-$(CONFIG_MMC_PXA) += pxamci.o
48 diff --git a/drivers/mmc/host/mtk-mmc/Kconfig b/drivers/mmc/host/mtk-mmc/Kconfig
50 index 0000000..a58b0f3
52 +++ b/drivers/mmc/host/mtk-mmc/Kconfig
55 + tristate "MTK SD/MMC"
56 + depends on !MTD_NAND_RALINK
59 + bool "MTK AEE KDUMP"
62 +config MTK_MMC_CD_POLL
63 + bool "Card Detect with Polling"
66 +config MTK_MMC_EMMC_8BIT
67 + bool "eMMC 8-bit support"
68 + depends on MTK_MMC && RALINK_MT7628
70 diff --git a/drivers/mmc/host/mtk-mmc/Makefile b/drivers/mmc/host/mtk-mmc/Makefile
72 index 0000000..caead0b
74 +++ b/drivers/mmc/host/mtk-mmc/Makefile
76 +# Copyright Statement:
78 +# This software/firmware and related documentation ("MediaTek Software") are
79 +# protected under relevant copyright laws. The information contained herein
80 +# is confidential and proprietary to MediaTek Inc. and/or its licensors.
81 +# Without the prior written permission of MediaTek inc. and/or its licensors,
82 +# any reproduction, modification, use or disclosure of MediaTek Software,
83 +# and information contained herein, in whole or in part, shall be strictly prohibited.
85 +# MediaTek Inc. (C) 2010. All rights reserved.
87 +# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
88 +# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
89 +# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
90 +# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
91 +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
92 +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
93 +# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
94 +# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
95 +# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
96 +# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
97 +# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
98 +# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
99 +# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
100 +# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
101 +# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
102 +# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
103 +# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
104 +# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
106 +# The following software/firmware and/or related documentation ("MediaTek Software")
107 +# have been modified by MediaTek Inc. All revisions are subject to any receiver's
108 +# applicable license agreements with MediaTek Inc.
110 +obj-$(CONFIG_MTK_MMC) += mtk_sd.o
111 +mtk_sd-objs := sd.o dbg.o
112 +ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
113 +EXTRA_CFLAGS += -DMT6575_SD_DEBUG
117 + @rm -f *.o modules.order .*.cmd
118 diff --git a/drivers/mmc/host/mtk-mmc/board.h b/drivers/mmc/host/mtk-mmc/board.h
120 index 0000000..33bfc7b
122 +++ b/drivers/mmc/host/mtk-mmc/board.h
124 +/* Copyright Statement:
126 + * This software/firmware and related documentation ("MediaTek Software") are
127 + * protected under relevant copyright laws. The information contained herein
128 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
129 + * Without the prior written permission of MediaTek inc. and/or its licensors,
130 + * any reproduction, modification, use or disclosure of MediaTek Software,
131 + * and information contained herein, in whole or in part, shall be strictly prohibited.
133 +/* MediaTek Inc. (C) 2010. All rights reserved.
135 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
136 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
137 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
138 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
139 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
140 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
141 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
142 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
143 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
144 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
145 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
146 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
147 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
148 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
149 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
150 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
151 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
152 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
154 + * The following software/firmware and/or related documentation ("MediaTek Software")
155 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
156 + * applicable license agreements with MediaTek Inc.
159 +#ifndef __ARCH_ARM_MACH_BOARD_H
160 +#define __ARCH_ARM_MACH_BOARD_H
162 +#include <generated/autoconf.h>
163 +#include <linux/pm.h>
165 +// #include <mach/mt6575.h>
166 +// #include <board-custom.h>
169 +typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
170 +typedef void (*pm_callback_t)(pm_message_t state, void *data);
172 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
173 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
174 +#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
175 +#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
176 +#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
177 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
178 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
179 +#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
180 +#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
181 +#define MSDC_DDR (1 << 9) /* ddr mode support */
184 +#define MSDC_SMPL_RISING (0)
185 +#define MSDC_SMPL_FALLING (1)
187 +#define MSDC_CMD_PIN (0)
188 +#define MSDC_DAT_PIN (1)
189 +#define MSDC_CD_PIN (2)
190 +#define MSDC_WP_PIN (3)
191 +#define MSDC_RST_PIN (4)
194 + MSDC_CLKSRC_48MHZ = 0,
195 +// MSDC_CLKSRC_26MHZ = 0,
196 +// MSDC_CLKSRC_197MHZ = 1,
197 +// MSDC_CLKSRC_208MHZ = 2
201 + unsigned char clk_src; /* host clock source */
202 + unsigned char cmd_edge; /* command latch edge */
203 + unsigned char data_edge; /* data latch edge */
204 + unsigned char clk_drv; /* clock pad driving */
205 + unsigned char cmd_drv; /* command pad driving */
206 + unsigned char dat_drv; /* data pad driving */
207 + unsigned long flags; /* hardware capability flags */
208 + unsigned long data_pins; /* data pins */
209 + unsigned long data_offset; /* data address offset */
211 + /* config gpio pull mode */
212 + void (*config_gpio_pin)(int type, int pull);
214 + /* external power control for card */
215 + void (*ext_power_on)(void);
216 + void (*ext_power_off)(void);
218 + /* external sdio irq operations */
219 + void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
220 + void (*enable_sdio_eirq)(void);
221 + void (*disable_sdio_eirq)(void);
223 + /* external cd irq operations */
224 + void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
225 + void (*enable_cd_eirq)(void);
226 + void (*disable_cd_eirq)(void);
227 + int (*get_cd_status)(void);
229 + /* power management callback for external module */
230 + void (*register_pm)(pm_callback_t pm_cb, void *data);
233 +extern struct msdc_hw msdc0_hw;
234 +extern struct msdc_hw msdc1_hw;
235 +extern struct msdc_hw msdc2_hw;
236 +extern struct msdc_hw msdc3_hw;
239 +#define GPS_FLAG_FORCE_OFF 0x0001
240 +struct mt3326_gps_hardware {
241 + int (*ext_power_on)(int);
242 + int (*ext_power_off)(int);
244 +extern struct mt3326_gps_hardware mt3326_gps_hw;
247 +struct mt6575_nand_host_hw {
248 + unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
249 + unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
250 + unsigned int nfi_cs_num; /* NFI_CS_NUM */
251 + unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
252 + unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
253 + unsigned int nand_ecc_size;
254 + unsigned int nand_ecc_bytes;
255 + unsigned int nand_ecc_mode;
257 +extern struct mt6575_nand_host_hw mt6575_nand_hw;
259 +#endif /* __ARCH_ARM_MACH_BOARD_H */
261 diff --git a/drivers/mmc/host/mtk-mmc/dbg.c b/drivers/mmc/host/mtk-mmc/dbg.c
263 index 0000000..4dc115b
265 +++ b/drivers/mmc/host/mtk-mmc/dbg.c
267 +/* Copyright Statement:
269 + * This software/firmware and related documentation ("MediaTek Software") are
270 + * protected under relevant copyright laws. The information contained herein
271 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
272 + * Without the prior written permission of MediaTek inc. and/or its licensors,
273 + * any reproduction, modification, use or disclosure of MediaTek Software,
274 + * and information contained herein, in whole or in part, shall be strictly prohibited.
276 + * MediaTek Inc. (C) 2010. All rights reserved.
278 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
279 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
280 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
281 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
282 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
283 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
284 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
285 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
286 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
287 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
288 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
289 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
290 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
291 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
292 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
293 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
294 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
295 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
297 + * The following software/firmware and/or related documentation ("MediaTek Software")
298 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
299 + * applicable license agreements with MediaTek Inc.
302 +#include <linux/version.h>
303 +#include <linux/kernel.h>
304 +#include <linux/sched.h>
305 +#include <linux/kthread.h>
306 +#include <linux/delay.h>
307 +#include <linux/module.h>
308 +#include <linux/init.h>
309 +#include <linux/proc_fs.h>
310 +#include <linux/string.h>
311 +#include <linux/uaccess.h>
312 +// #include <mach/mt6575_gpt.h> /* --- by chhung */
314 +#include "mt6575_sd.h"
315 +#include <linux/seq_file.h>
317 +static char cmd_buf[256];
319 +/* for debug zone */
320 +unsigned int sd_debug_zone[4]={
334 +msdc_mode drv_mode[4]={
335 + MODE_SIZE_DEP, /* using DMA or not depend on the size */
341 +#if defined (MT6575_SD_DEBUG)
342 +/* for driver profile */
343 +#define TICKS_ONE_MS (13000)
345 +u32 sdio_pro_enable = 0; /* make sure gpt is enabled */
346 +u32 sdio_pro_time = 0; /* no more than 30s */
347 +struct sdio_profile sdio_perfomance = {0};
349 +#if 0 /* --- chhung */
350 +void msdc_init_gpt(void)
355 + config.mode = GPT_FREE_RUN;
356 + config.clkSrc = GPT_CLK_SRC_SYS;
357 + config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
359 + if (GPT_Config(config) == FALSE )
364 +#endif /* end of --- */
366 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
370 + if (new_H32 == old_H32) {
371 + ret = new_L32 - old_L32;
372 + } else if(new_H32 == (old_H32 + 1)) {
373 + if (new_L32 > old_L32) {
374 + printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
376 + ret = (0xffffffff - old_L32);
379 + printk("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);
385 +void msdc_sdio_profile(struct sdio_profile* result)
387 + struct cmd_profile* cmd;
390 + printk("sdio === performance dump ===\n");
391 + printk("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n",
392 + result->total_tc, result->total_tc / TICKS_ONE_MS,
393 + result->total_tx_bytes, result->total_rx_bytes);
396 + cmd = &result->cmd52_rx;
397 + printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
398 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
399 + cmd = &result->cmd52_tx;
400 + printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
401 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
403 + /* CMD53 Rx bytes + block mode */
404 + for (i=0; i<512; i++) {
405 + cmd = &result->cmd53_rx_byte[i];
407 + printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
408 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
409 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
412 + for (i=0; i<100; i++) {
413 + cmd = &result->cmd53_rx_blk[i];
415 + printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
416 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
417 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
421 + /* CMD53 Tx bytes + block mode */
422 + for (i=0; i<512; i++) {
423 + cmd = &result->cmd53_tx_byte[i];
425 + printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
426 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
427 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
430 + for (i=0; i<100; i++) {
431 + cmd = &result->cmd53_tx_blk[i];
433 + printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
434 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
435 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
439 + printk("sdio === performance dump done ===\n");
442 +//========= sdio command table ===========
443 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
445 + struct sdio_profile* result = &sdio_perfomance;
446 + struct cmd_profile* cmd;
449 + if (sdio_pro_enable == 0) {
453 + if (opcode == 52) {
454 + cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
455 + } else if (opcode == 53) {
457 + cmd = bRx ? &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];
459 + block = sizes / 512;
461 + printk("cmd53 error blocks\n");
464 + cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
470 + /* update the members */
471 + if (ticks > cmd->max_tc){
472 + cmd->max_tc = ticks;
474 + if (cmd->min_tc == 0 || ticks < cmd->min_tc) {
475 + cmd->min_tc = ticks;
477 + cmd->tot_tc += ticks;
478 + cmd->tot_bytes += sizes;
482 + result->total_rx_bytes += sizes;
484 + result->total_tx_bytes += sizes;
486 + result->total_tc += ticks;
488 + /* dump when total_tc > 30s */
489 + if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
490 + msdc_sdio_profile(result);
491 + memset(result, 0 , sizeof(struct sdio_profile));
495 +//========== driver proc interface ===========
496 +static int msdc_debug_proc_read(struct seq_file *s, void *p)
498 + seq_printf(s, "\n=========================================\n");
499 + seq_printf(s, "Index<0> + Id + Zone\n");
500 + seq_printf(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
501 + seq_printf(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
502 + seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
503 + seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
504 + seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
505 + seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
507 + seq_printf(s, "Index<1> + ID:4|Mode:4 + DMA_SIZE\n");
508 + seq_printf(s, "-> 0)PIO 1)DMA 2)SIZE\n");
509 + seq_printf(s, "-> echo 1 22 0x200 >msdc_bebug -> host[2] size mode, dma when >= 512\n");
510 + seq_printf(s, "-> MSDC[0] mode<%d> size<%d>\n", drv_mode[0], dma_size[0]);
511 + seq_printf(s, "-> MSDC[1] mode<%d> size<%d>\n", drv_mode[1], dma_size[1]);
512 + seq_printf(s, "-> MSDC[2] mode<%d> size<%d>\n", drv_mode[2], dma_size[2]);
513 + seq_printf(s, "-> MSDC[3] mode<%d> size<%d>\n", drv_mode[3], dma_size[3]);
515 + seq_printf(s, "Index<3> + SDIO_PROFILE + TIME\n");
516 + seq_printf(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
517 + seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
518 + seq_printf(s, "=========================================\n\n");
523 +static ssize_t msdc_debug_proc_write(struct file *file,
524 + const char __user *buf, size_t count, loff_t *data)
532 + if (count == 0)return -1;
533 + if(count > 255)count = 255;
535 + ret = copy_from_user(cmd_buf, buf, count);
536 + if (ret < 0)return -1;
538 + cmd_buf[count] = '\0';
539 + printk("msdc Write %s\n", cmd_buf);
541 + sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
543 + if(cmd == SD_TOOL_ZONE) {
544 + id = p1; zone = p2; zone &= 0x3ff;
545 + printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
546 + if(id >=0 && id<=3){
547 + sd_debug_zone[id] = zone;
550 + sd_debug_zone[0] = sd_debug_zone[1] = zone;
551 + sd_debug_zone[2] = sd_debug_zone[3] = zone;
554 + printk("msdc host_id error when set debug zone\n");
556 + } else if (cmd == SD_TOOL_DMA_SIZE) {
557 + id = p1>>4; mode = (p1&0xf); size = p2;
558 + if(id >=0 && id<=3){
559 + drv_mode[id] = mode;
563 + drv_mode[0] = drv_mode[1] = mode;
564 + drv_mode[2] = drv_mode[3] = mode;
565 + dma_size[0] = dma_size[1] = p2;
566 + dma_size[2] = dma_size[3] = p2;
569 + printk("msdc host_id error when select mode\n");
571 + } else if (cmd == SD_TOOL_SDIO_PROFILE) {
572 + if (p1 == 1) { /* enable profile */
573 + if (gpt_enable == 0) {
574 + // msdc_init_gpt(); /* --- by chhung */
577 + sdio_pro_enable = 1;
578 + if (p2 == 0) p2 = 1; if (p2 >= 30) p2 = 30;
579 + sdio_pro_time = p2 ;
580 + } else if (p1 == 0) {
582 + sdio_pro_enable = 0;
589 +static int msdc_debug_show(struct inode *inode, struct file *file)
591 + return single_open(file, msdc_debug_proc_read, NULL);
594 +static const struct file_operations msdc_debug_fops = {
595 + .owner = THIS_MODULE,
596 + .open = msdc_debug_show,
598 + .write = msdc_debug_proc_write,
599 + .llseek = seq_lseek,
600 + .release = single_release,
603 +int msdc_debug_proc_init(void)
605 + struct proc_dir_entry *de = proc_create("msdc_debug", 0667, NULL, &msdc_debug_fops);
607 + if (!de || IS_ERR(de))
608 + printk("!! Create MSDC debug PROC fail !!\n");
612 +EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
614 diff --git a/drivers/mmc/host/mtk-mmc/dbg.h b/drivers/mmc/host/mtk-mmc/dbg.h
616 index 0000000..e58c431
618 +++ b/drivers/mmc/host/mtk-mmc/dbg.h
620 +/* Copyright Statement:
622 + * This software/firmware and related documentation ("MediaTek Software") are
623 + * protected under relevant copyright laws. The information contained herein
624 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
625 + * Without the prior written permission of MediaTek inc. and/or its licensors,
626 + * any reproduction, modification, use or disclosure of MediaTek Software,
627 + * and information contained herein, in whole or in part, shall be strictly prohibited.
629 + * MediaTek Inc. (C) 2010. All rights reserved.
631 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
632 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
633 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
634 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
635 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
636 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
637 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
638 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
639 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
640 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
641 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
642 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
643 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
644 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
645 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
646 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
647 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
648 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
650 + * The following software/firmware and/or related documentation ("MediaTek Software")
651 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
652 + * applicable license agreements with MediaTek Inc.
654 +#ifndef __MT_MSDC_DEUBG__
655 +#define __MT_MSDC_DEUBG__
657 +//==========================
658 +extern u32 sdio_pro_enable;
659 +/* for a type command, e.g. CMD53, 2 blocks */
660 +struct cmd_profile {
661 + u32 max_tc; /* Max tick count */
663 + u32 tot_tc; /* total tick count */
665 + u32 count; /* the counts of the command */
668 +/* dump when total_tc and total_bytes */
669 +struct sdio_profile {
670 + u32 total_tc; /* total tick count of CMD52 and CMD53 */
671 + u32 total_tx_bytes; /* total bytes of CMD53 Tx */
672 + u32 total_rx_bytes; /* total bytes of CMD53 Rx */
675 + struct cmd_profile cmd52_tx;
676 + struct cmd_profile cmd52_rx;
678 + /*CMD53 in byte unit */
679 + struct cmd_profile cmd53_tx_byte[512];
680 + struct cmd_profile cmd53_rx_byte[512];
682 + /*CMD53 in block unit */
683 + struct cmd_profile cmd53_tx_blk[100];
684 + struct cmd_profile cmd53_rx_blk[100];
687 +//==========================
690 + SD_TOOL_DMA_SIZE = 1,
691 + SD_TOOL_PM_ENABLE = 2,
692 + SD_TOOL_SDIO_PROFILE = 3,
700 +extern msdc_mode drv_mode[4];
701 +extern u32 dma_size[4];
703 +/* Debug message event */
704 +#define DBG_EVT_NONE (0) /* No event */
705 +#define DBG_EVT_DMA (1 << 0) /* DMA related event */
706 +#define DBG_EVT_CMD (1 << 1) /* MSDC CMD related event */
707 +#define DBG_EVT_RSP (1 << 2) /* MSDC CMD RSP related event */
708 +#define DBG_EVT_INT (1 << 3) /* MSDC INT event */
709 +#define DBG_EVT_CFG (1 << 4) /* MSDC CFG event */
710 +#define DBG_EVT_FUC (1 << 5) /* Function event */
711 +#define DBG_EVT_OPS (1 << 6) /* Read/Write operation event */
712 +#define DBG_EVT_FIO (1 << 7) /* FIFO operation event */
713 +#define DBG_EVT_WRN (1 << 8) /* Warning event */
714 +#define DBG_EVT_PWR (1 << 9) /* Power event */
715 +#define DBG_EVT_ALL (0xffffffff)
717 +#define DBG_EVT_MASK (DBG_EVT_ALL)
719 +extern unsigned int sd_debug_zone[4];
721 +#if 0 /* +++ chhung */
725 + printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
729 +#endif /* end of +++ */
731 +#define N_MSG(evt, fmt, args...)
734 + if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
735 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
736 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
741 +#define ERR_MSG(fmt, args...) \
743 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
744 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
748 +//defined CONFIG_MTK_MMC_CD_POLL
749 +#define INIT_MSG(fmt, args...)
750 +#define IRQ_MSG(fmt, args...)
752 +#define INIT_MSG(fmt, args...) \
754 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
755 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
758 +/* PID in ISR in not corrent */
759 +#define IRQ_MSG(fmt, args...) \
761 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
762 + host->id, ##args , __FUNCTION__, __LINE__); \
766 +int msdc_debug_proc_init(void);
768 +#if 0 /* --- chhung */
769 +void msdc_init_gpt(void);
770 +extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
771 +#endif /* end of --- */
772 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
773 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);
776 diff --git a/drivers/mmc/host/mtk-mmc/mt6575_sd.h b/drivers/mmc/host/mtk-mmc/mt6575_sd.h
778 index 0000000..e90c4f1
780 +++ b/drivers/mmc/host/mtk-mmc/mt6575_sd.h
782 +/* Copyright Statement:
784 + * This software/firmware and related documentation ("MediaTek Software") are
785 + * protected under relevant copyright laws. The information contained herein
786 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
787 + * Without the prior written permission of MediaTek inc. and/or its licensors,
788 + * any reproduction, modification, use or disclosure of MediaTek Software,
789 + * and information contained herein, in whole or in part, shall be strictly prohibited.
791 +/* MediaTek Inc. (C) 2010. All rights reserved.
793 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
794 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
795 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
796 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
797 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
798 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
799 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
800 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
801 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
802 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
803 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
804 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
805 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
806 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
807 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
808 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
809 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
810 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
812 + * The following software/firmware and/or related documentation ("MediaTek Software")
813 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
814 + * applicable license agreements with MediaTek Inc.
820 +#include <linux/bitops.h>
821 +#include <linux/mmc/host.h>
823 +// #include <mach/mt6575_reg_base.h> /* --- by chhung */
825 +/*--------------------------------------------------------------------------*/
827 +/*--------------------------------------------------------------------------*/
828 +#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
830 +/*--------------------------------------------------------------------------*/
831 +/* Common Definition */
832 +/*--------------------------------------------------------------------------*/
833 +#define MSDC_FIFO_SZ (128)
834 +#define MSDC_FIFO_THD (64) // (128)
835 +#define MSDC_NUM (4)
838 +#define MSDC_SDMMC (1)
840 +#define MSDC_MODE_UNKNOWN (0)
841 +#define MSDC_MODE_PIO (1)
842 +#define MSDC_MODE_DMA_BASIC (2)
843 +#define MSDC_MODE_DMA_DESC (3)
844 +#define MSDC_MODE_DMA_ENHANCED (4)
845 +#define MSDC_MODE_MMC_STREAM (5)
847 +#define MSDC_BUS_1BITS (0)
848 +#define MSDC_BUS_4BITS (1)
849 +#define MSDC_BUS_8BITS (2)
851 +#define MSDC_BRUST_8B (3)
852 +#define MSDC_BRUST_16B (4)
853 +#define MSDC_BRUST_32B (5)
854 +#define MSDC_BRUST_64B (6)
856 +#define MSDC_PIN_PULL_NONE (0)
857 +#define MSDC_PIN_PULL_DOWN (1)
858 +#define MSDC_PIN_PULL_UP (2)
859 +#define MSDC_PIN_KEEP (3)
861 +#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
862 +#define MSDC_MIN_SCLK (260000)
864 +#define MSDC_AUTOCMD12 (0x0001)
865 +#define MSDC_AUTOCMD23 (0x0002)
866 +#define MSDC_AUTOCMD19 (0x0003)
868 +#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
869 +#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
883 +/*--------------------------------------------------------------------------*/
884 +/* Register Offset */
885 +/*--------------------------------------------------------------------------*/
886 +#define OFFSET_MSDC_CFG (0x0)
887 +#define OFFSET_MSDC_IOCON (0x04)
888 +#define OFFSET_MSDC_PS (0x08)
889 +#define OFFSET_MSDC_INT (0x0c)
890 +#define OFFSET_MSDC_INTEN (0x10)
891 +#define OFFSET_MSDC_FIFOCS (0x14)
892 +#define OFFSET_MSDC_TXDATA (0x18)
893 +#define OFFSET_MSDC_RXDATA (0x1c)
894 +#define OFFSET_SDC_CFG (0x30)
895 +#define OFFSET_SDC_CMD (0x34)
896 +#define OFFSET_SDC_ARG (0x38)
897 +#define OFFSET_SDC_STS (0x3c)
898 +#define OFFSET_SDC_RESP0 (0x40)
899 +#define OFFSET_SDC_RESP1 (0x44)
900 +#define OFFSET_SDC_RESP2 (0x48)
901 +#define OFFSET_SDC_RESP3 (0x4c)
902 +#define OFFSET_SDC_BLK_NUM (0x50)
903 +#define OFFSET_SDC_CSTS (0x58)
904 +#define OFFSET_SDC_CSTS_EN (0x5c)
905 +#define OFFSET_SDC_DCRC_STS (0x60)
906 +#define OFFSET_EMMC_CFG0 (0x70)
907 +#define OFFSET_EMMC_CFG1 (0x74)
908 +#define OFFSET_EMMC_STS (0x78)
909 +#define OFFSET_EMMC_IOCON (0x7c)
910 +#define OFFSET_SDC_ACMD_RESP (0x80)
911 +#define OFFSET_SDC_ACMD19_TRG (0x84)
912 +#define OFFSET_SDC_ACMD19_STS (0x88)
913 +#define OFFSET_MSDC_DMA_SA (0x90)
914 +#define OFFSET_MSDC_DMA_CA (0x94)
915 +#define OFFSET_MSDC_DMA_CTRL (0x98)
916 +#define OFFSET_MSDC_DMA_CFG (0x9c)
917 +#define OFFSET_MSDC_DBG_SEL (0xa0)
918 +#define OFFSET_MSDC_DBG_OUT (0xa4)
919 +#define OFFSET_MSDC_PATCH_BIT (0xb0)
920 +#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
921 +#define OFFSET_MSDC_PAD_CTL0 (0xe0)
922 +#define OFFSET_MSDC_PAD_CTL1 (0xe4)
923 +#define OFFSET_MSDC_PAD_CTL2 (0xe8)
924 +#define OFFSET_MSDC_PAD_TUNE (0xec)
925 +#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
926 +#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
927 +#define OFFSET_MSDC_HW_DBG (0xf8)
928 +#define OFFSET_MSDC_VERSION (0x100)
929 +#define OFFSET_MSDC_ECO_VER (0x104)
931 +/*--------------------------------------------------------------------------*/
932 +/* Register Address */
933 +/*--------------------------------------------------------------------------*/
935 +/* common register */
936 +#define MSDC_CFG REG_ADDR(MSDC_CFG)
937 +#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
938 +#define MSDC_PS REG_ADDR(MSDC_PS)
939 +#define MSDC_INT REG_ADDR(MSDC_INT)
940 +#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
941 +#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
942 +#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
943 +#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
944 +#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
946 +/* sdmmc register */
947 +#define SDC_CFG REG_ADDR(SDC_CFG)
948 +#define SDC_CMD REG_ADDR(SDC_CMD)
949 +#define SDC_ARG REG_ADDR(SDC_ARG)
950 +#define SDC_STS REG_ADDR(SDC_STS)
951 +#define SDC_RESP0 REG_ADDR(SDC_RESP0)
952 +#define SDC_RESP1 REG_ADDR(SDC_RESP1)
953 +#define SDC_RESP2 REG_ADDR(SDC_RESP2)
954 +#define SDC_RESP3 REG_ADDR(SDC_RESP3)
955 +#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
956 +#define SDC_CSTS REG_ADDR(SDC_CSTS)
957 +#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
958 +#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
961 +#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
962 +#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
963 +#define EMMC_STS REG_ADDR(EMMC_STS)
964 +#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
966 +/* auto command register */
967 +#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
968 +#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
969 +#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
972 +#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
973 +#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
974 +#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
975 +#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
977 +/* pad ctrl register */
978 +#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
979 +#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
980 +#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
982 +/* data read delay */
983 +#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
984 +#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
986 +/* debug register */
987 +#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
988 +#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
991 +#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
992 +#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
993 +#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
994 +#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
995 +#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
996 +#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
998 +/*--------------------------------------------------------------------------*/
1000 +/*--------------------------------------------------------------------------*/
1002 +/* MSDC_CFG mask */
1003 +#define MSDC_CFG_MODE (0x1 << 0) /* RW */
1004 +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
1005 +#define MSDC_CFG_RST (0x1 << 2) /* RW */
1006 +#define MSDC_CFG_PIO (0x1 << 3) /* RW */
1007 +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
1008 +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
1009 +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
1010 +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
1011 +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
1012 +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
1014 +/* MSDC_IOCON mask */
1015 +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
1016 +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
1017 +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
1018 +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
1019 +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
1020 +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
1021 +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
1022 +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
1023 +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
1024 +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
1025 +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
1026 +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
1027 +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
1028 +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
1029 +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
1032 +#define MSDC_PS_CDEN (0x1 << 0) /* RW */
1033 +#define MSDC_PS_CDSTS (0x1 << 1) /* R */
1034 +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
1035 +#define MSDC_PS_DAT (0xff << 16) /* R */
1036 +#define MSDC_PS_CMD (0x1 << 24) /* R */
1037 +#define MSDC_PS_WP (0x1UL<< 31) /* R */
1039 +/* MSDC_INT mask */
1040 +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
1041 +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
1042 +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
1043 +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
1044 +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
1045 +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
1046 +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
1047 +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
1048 +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
1049 +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
1050 +#define MSDC_INT_CSTA (0x1 << 11) /* R */
1051 +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
1052 +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
1053 +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
1054 +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
1055 +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
1057 +/* MSDC_INTEN mask */
1058 +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
1059 +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
1060 +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
1061 +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
1062 +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
1063 +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
1064 +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
1065 +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
1066 +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
1067 +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
1068 +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
1069 +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
1070 +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
1071 +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
1072 +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
1073 +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
1075 +/* MSDC_FIFOCS mask */
1076 +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
1077 +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
1078 +#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
1081 +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
1082 +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
1083 +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
1084 +#define SDC_CFG_SDIO (0x1 << 19) /* RW */
1085 +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
1086 +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
1087 +#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
1090 +#define SDC_CMD_OPC (0x3f << 0) /* RW */
1091 +#define SDC_CMD_BRK (0x1 << 6) /* RW */
1092 +#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
1093 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1094 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1095 +#define SDC_CMD_RW (0x1 << 13) /* RW */
1096 +#define SDC_CMD_STOP (0x1 << 14) /* RW */
1097 +#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
1098 +#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
1099 +#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
1100 +#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
1103 +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
1104 +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
1105 +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
1107 +/* SDC_DCRC_STS mask */
1108 +#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
1109 +#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
1111 +/* EMMC_CFG0 mask */
1112 +#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
1113 +#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
1114 +#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
1115 +#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
1116 +#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
1117 +#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
1119 +/* EMMC_CFG1 mask */
1120 +#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
1121 +#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
1123 +/* EMMC_STS mask */
1124 +#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
1125 +#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
1126 +#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
1127 +#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
1128 +#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
1129 +#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
1130 +#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
1132 +/* EMMC_IOCON mask */
1133 +#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
1135 +/* SDC_ACMD19_TRG mask */
1136 +#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
1138 +/* MSDC_DMA_CTRL mask */
1139 +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
1140 +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
1141 +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
1142 +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
1143 +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
1144 +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
1145 +#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
1147 +/* MSDC_DMA_CFG mask */
1148 +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
1149 +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
1150 +#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
1151 +#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
1153 +/* MSDC_PATCH_BIT mask */
1154 +#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
1155 +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
1156 +#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
1157 +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
1158 +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
1159 +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
1160 +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
1161 +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
1162 +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
1163 +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
1164 +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
1165 +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
1167 +/* MSDC_PATCH_BIT1 mask */
1168 +#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
1169 +#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
1171 +/* MSDC_PAD_CTL0 mask */
1172 +#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
1173 +#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
1174 +#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
1175 +#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
1176 +#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
1177 +#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
1178 +#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
1179 +#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
1180 +#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
1182 +/* MSDC_PAD_CTL1 mask */
1183 +#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
1184 +#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
1185 +#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
1186 +#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
1187 +#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
1188 +#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
1189 +#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
1190 +#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
1191 +#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
1193 +/* MSDC_PAD_CTL2 mask */
1194 +#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
1195 +#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
1196 +#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
1197 +#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
1198 +#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
1199 +#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
1200 +#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
1201 +#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
1202 +#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
1204 +/* MSDC_PAD_TUNE mask */
1205 +#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
1206 +#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
1207 +#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
1208 +#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
1209 +#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
1211 +/* MSDC_DAT_RDDLY0/1 mask */
1212 +#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
1213 +#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
1214 +#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
1215 +#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
1217 +#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
1218 +#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
1219 +#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
1220 +#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
1222 +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
1223 +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
1224 +#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
1225 +#define CARD_READY_FOR_DATA (1<<8)
1226 +#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
1228 +/*--------------------------------------------------------------------------*/
1229 +/* Descriptor Structure */
1230 +/*--------------------------------------------------------------------------*/
1232 + u32 hwo:1; /* could be changed by hw */
1262 +/*--------------------------------------------------------------------------*/
1263 +/* Register Debugging Structure */
1264 +/*--------------------------------------------------------------------------*/
1280 + u32 sdr104cksel:1;
1325 + u32 atocmd19done:1;
1345 + u32 atocmd19done:1;
1421 +} sdc_datcrcsts_reg;
1432 + u32 bootcrctmc:16;
1434 + u32 bootacktmc:12;
1441 + u32 bootupstate:1;
1452 +} msdc_acmd_resp_reg;
1456 +} msdc_acmd19_trg_reg;
1459 +} msdc_acmd19_sts_reg;
1478 +} msdc_dma_ctrl_reg;
1486 +} msdc_dma_cfg_reg;
1490 +} msdc_dbg_sel_reg;
1493 +} msdc_dbg_out_reg;
1507 +} msdc_pad_ctl0_reg;
1521 +} msdc_pad_ctl1_reg;
1535 +} msdc_pad_ctl2_reg;
1541 +} msdc_pad_tune_reg;
1573 +} msdc_version_reg;
1576 +} msdc_eco_ver_reg;
1579 + msdc_cfg_reg msdc_cfg; /* base+0x00h */
1580 + msdc_iocon_reg msdc_iocon; /* base+0x04h */
1581 + msdc_ps_reg msdc_ps; /* base+0x08h */
1582 + msdc_int_reg msdc_int; /* base+0x0ch */
1583 + msdc_inten_reg msdc_inten; /* base+0x10h */
1584 + msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
1585 + msdc_txdat_reg msdc_txdat; /* base+0x18h */
1586 + msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
1588 + sdc_cfg_reg sdc_cfg; /* base+0x30h */
1589 + sdc_cmd_reg sdc_cmd; /* base+0x34h */
1590 + sdc_arg_reg sdc_arg; /* base+0x38h */
1591 + sdc_sts_reg sdc_sts; /* base+0x3ch */
1592 + sdc_resp0_reg sdc_resp0; /* base+0x40h */
1593 + sdc_resp1_reg sdc_resp1; /* base+0x44h */
1594 + sdc_resp2_reg sdc_resp2; /* base+0x48h */
1595 + sdc_resp3_reg sdc_resp3; /* base+0x4ch */
1596 + sdc_blknum_reg sdc_blknum; /* base+0x50h */
1598 + sdc_csts_reg sdc_csts; /* base+0x58h */
1599 + sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
1600 + sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
1602 + emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
1603 + emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
1604 + emmc_sts_reg emmc_sts; /* base+0x78h */
1605 + emmc_iocon_reg emmc_iocon; /* base+0x7ch */
1606 + msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
1607 + msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
1608 + msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
1610 + msdc_dma_sa_reg dma_sa; /* base+0x90h */
1611 + msdc_dma_ca_reg dma_ca; /* base+0x94h */
1612 + msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
1613 + msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
1614 + msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
1615 + msdc_dbg_out_reg dbg_out; /* base+0xa4h */
1617 + u32 patch0; /* base+0xb0h */
1618 + u32 patch1; /* base+0xb4h */
1620 + msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
1621 + msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
1622 + msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
1623 + msdc_pad_tune_reg pad_tune; /* base+0xech */
1624 + msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
1625 + msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
1626 + msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
1628 + msdc_version_reg version; /* base+0x100h */
1629 + msdc_eco_ver_reg eco_ver; /* base+0x104h */
1632 +struct scatterlist_ex {
1636 + struct scatterlist *sg;
1639 +#define DMA_FLAG_NONE (0x00000000)
1640 +#define DMA_FLAG_EN_CHKSUM (0x00000001)
1641 +#define DMA_FLAG_PAD_BLOCK (0x00000002)
1642 +#define DMA_FLAG_PAD_DWORD (0x00000004)
1645 + u32 flags; /* flags */
1646 + u32 xfersz; /* xfer size in bytes */
1647 + u32 sglen; /* size of scatter list */
1648 + u32 blklen; /* block size */
1649 + struct scatterlist *sg; /* I/O scatter list */
1650 + struct scatterlist_ex *esg; /* extended I/O scatter list */
1651 + u8 mode; /* dma mode */
1652 + u8 burstsz; /* burst size */
1653 + u8 intr; /* dma done interrupt */
1654 + u8 padding; /* padding */
1655 + u32 cmd; /* enhanced mode command */
1656 + u32 arg; /* enhanced mode arg */
1657 + u32 rsp; /* enhanced mode command response */
1658 + u32 autorsp; /* auto command response */
1660 + gpd_t *gpd; /* pointer to gpd array */
1661 + bd_t *bd; /* pointer to bd array */
1662 + dma_addr_t gpd_addr; /* the physical address of gpd array */
1663 + dma_addr_t bd_addr; /* the physical address of bd array */
1664 + u32 used_gpd; /* the number of used gpd elements */
1665 + u32 used_bd; /* the number of used bd elements */
1670 + struct msdc_hw *hw;
1672 + struct mmc_host *mmc; /* mmc structure */
1673 + struct mmc_command *cmd;
1674 + struct mmc_data *data;
1675 + struct mmc_request *mrq;
1681 + spinlock_t lock; /* mutex */
1682 + struct semaphore sem;
1684 + u32 blksz; /* host block size */
1685 + u32 base; /* host base address */
1686 + int id; /* host id */
1687 + int pwr_ref; /* core power reference count */
1689 + u32 xfer_size; /* total transferred size */
1691 + struct msdc_dma dma; /* dma channel */
1692 + u32 dma_addr; /* dma transfer address */
1693 + u32 dma_left_size; /* dma transfer left size */
1694 + u32 dma_xfer_size; /* dma transfer size in bytes */
1695 + int dma_xfer; /* dma transfer mode */
1697 + u32 timeout_ns; /* data timeout ns */
1698 + u32 timeout_clks; /* data timeout clks */
1700 + atomic_t abort; /* abort transfer */
1702 + int irq; /* host interrupt */
1704 + struct tasklet_struct card_tasklet;
1706 + struct work_struct card_workqueue;
1708 + struct delayed_work card_delaywork;
1711 + struct completion cmd_done;
1712 + struct completion xfer_done;
1713 + struct pm_message pm_state;
1715 + u32 mclk; /* mmc subsystem clock */
1716 + u32 hclk; /* host clock speed */
1717 + u32 sclk; /* SD/MS clock speed */
1718 + u8 core_clkon; /* Host core clock on ? */
1719 + u8 card_clkon; /* Card clock on ? */
1720 + u8 core_power; /* core power */
1721 + u8 power_mode; /* host power mode */
1722 + u8 card_inserted; /* card inserted ? */
1723 + u8 suspend; /* host suspended ? */
1725 + u8 app_cmd; /* for app command */
1730 +static inline unsigned int uffs(unsigned int x)
1732 + unsigned int r = 1;
1736 + if (!(x & 0xffff)) {
1740 + if (!(x & 0xff)) {
1758 +#define sdr_read8(reg) __raw_readb(reg)
1759 +#define sdr_read16(reg) __raw_readw(reg)
1760 +#define sdr_read32(reg) __raw_readl(reg)
1761 +#define sdr_write8(reg,val) __raw_writeb(val,reg)
1762 +#define sdr_write16(reg,val) __raw_writew(val,reg)
1763 +#define sdr_write32(reg,val) __raw_writel(val,reg)
1765 +#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
1766 +#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
1768 +#define sdr_set_field(reg,field,val) \
1770 + volatile unsigned int tv = sdr_read32(reg); \
1772 + tv |= ((val) << (uffs((unsigned int)field) - 1)); \
1773 + sdr_write32(reg,tv); \
1775 +#define sdr_get_field(reg,field,val) \
1777 + volatile unsigned int tv = sdr_read32(reg); \
1778 + val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
1783 diff --git a/drivers/mmc/host/mtk-mmc/sd.c b/drivers/mmc/host/mtk-mmc/sd.c
1784 new file mode 100644
1785 index 0000000..d240b46
1787 +++ b/drivers/mmc/host/mtk-mmc/sd.c
1789 +/* Copyright Statement:
1791 + * This software/firmware and related documentation ("MediaTek Software") are
1792 + * protected under relevant copyright laws. The information contained herein
1793 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
1794 + * Without the prior written permission of MediaTek inc. and/or its licensors,
1795 + * any reproduction, modification, use or disclosure of MediaTek Software,
1796 + * and information contained herein, in whole or in part, shall be strictly prohibited.
1798 + * MediaTek Inc. (C) 2010. All rights reserved.
1800 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1801 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1802 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
1803 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1804 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1805 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1806 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1807 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1808 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
1809 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
1810 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
1811 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
1812 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
1813 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
1814 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1815 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1816 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
1817 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1819 + * The following software/firmware and/or related documentation ("MediaTek Software")
1820 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
1821 + * applicable license agreements with MediaTek Inc.
1824 +#include <linux/module.h>
1825 +#include <linux/moduleparam.h>
1826 +#include <linux/init.h>
1827 +#include <linux/spinlock.h>
1828 +#include <linux/timer.h>
1829 +#include <linux/ioport.h>
1830 +#include <linux/device.h>
1831 +#include <linux/platform_device.h>
1832 +#include <linux/interrupt.h>
1833 +#include <linux/delay.h>
1834 +#include <linux/blkdev.h>
1835 +#include <linux/slab.h>
1836 +#include <linux/mmc/host.h>
1837 +#include <linux/mmc/card.h>
1838 +#include <linux/mmc/core.h>
1839 +#include <linux/mmc/mmc.h>
1840 +#include <linux/mmc/sd.h>
1841 +#include <linux/mmc/sdio.h>
1842 +#include <linux/dma-mapping.h>
1844 +/* +++ by chhung */
1845 +#include <linux/types.h>
1846 +#include <linux/kernel.h>
1847 +#include <linux/version.h>
1848 +#include <linux/pm.h>
1849 +#include <linux/of.h>
1851 +#define MSDC_SMPL_FALLING (1)
1852 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
1853 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
1854 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
1855 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
1856 +#define MSDC_HIGHSPEED (1 << 7)
1858 +//#define IRQ_SDC 14 //MT7620 /*FIXME*/
1859 +#ifdef CONFIG_SOC_MT7621
1860 +#define RALINK_SYSCTL_BASE 0xbe000000
1861 +#define RALINK_MSDC_BASE 0xbe130000
1863 +#define RALINK_SYSCTL_BASE 0xb0000000
1864 +#define RALINK_MSDC_BASE 0xb0130000
1866 +#define IRQ_SDC 22 /*FIXME*/
1868 +#include <asm/dma.h>
1872 +#include <asm/mach-ralink/ralink_regs.h>
1874 +#if 0 /* --- by chhung */
1875 +#include <mach/board.h>
1876 +#include <mach/mt6575_devs.h>
1877 +#include <mach/mt6575_typedefs.h>
1878 +#include <mach/mt6575_clock_manager.h>
1879 +#include <mach/mt6575_pm_ldo.h>
1880 +//#include <mach/mt6575_pll.h>
1881 +//#include <mach/mt6575_gpio.h>
1882 +//#include <mach/mt6575_gpt_sw.h>
1883 +#include <asm/tcm.h>
1884 +// #include <mach/mt6575_gpt.h>
1885 +#endif /* end of --- */
1887 +#include "mt6575_sd.h"
1890 +/* +++ by chhung */
1894 +#if 0 /* --- by chhung */
1895 +#define isb() __asm__ __volatile__ ("" : : : "memory")
1896 +#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
1897 + : : "r" (0) : "memory")
1898 +#define dmb() __asm__ __volatile__ ("" : : : "memory")
1899 +#endif /* end of --- */
1901 +#define DRV_NAME "mtk-sd"
1903 +#define HOST_MAX_NUM (1) /* +/- by chhung */
1905 +#if defined (CONFIG_SOC_MT7620)
1906 +#define HOST_MAX_MCLK (48000000) /* +/- by chhung */
1907 +#elif defined (CONFIG_SOC_MT7621)
1908 +#define HOST_MAX_MCLK (50000000) /* +/- by chhung */
1910 +#define HOST_MIN_MCLK (260000)
1912 +#define HOST_MAX_BLKSZ (2048)
1914 +#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
1916 +#define GPIO_PULL_DOWN (0)
1917 +#define GPIO_PULL_UP (1)
1919 +#if 0 /* --- by chhung */
1920 +#define MSDC_CLKSRC_REG (0xf100000C)
1921 +#define PDN_REG (0xF1000010)
1922 +#endif /* end of --- */
1924 +#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
1925 +#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
1927 +#define CMD_TIMEOUT (HZ/10) /* 100ms */
1928 +#define DAT_TIMEOUT (HZ/2 * 5) /* 500ms x5 */
1930 +#define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
1932 +#define MAX_GPD_NUM (1 + 1) /* one null gpd */
1933 +#define MAX_BD_NUM (1024)
1934 +#define MAX_BD_PER_GPD (MAX_BD_NUM)
1936 +#define MAX_HW_SGMTS (MAX_BD_NUM)
1937 +#define MAX_PHY_SGMTS (MAX_BD_NUM)
1938 +#define MAX_SGMT_SZ (MAX_DMA_CNT)
1939 +#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
1941 +#ifdef MT6575_SD_DEBUG
1942 +static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
1945 +static int mtk_sw_poll;
1947 +static int cd_active_low = 1;
1949 +//=================================
1950 +#define PERI_MSDC0_PDN (15)
1951 +//#define PERI_MSDC1_PDN (16)
1952 +//#define PERI_MSDC2_PDN (17)
1953 +//#define PERI_MSDC3_PDN (18)
1955 +struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
1956 +#if 0 /* --- by chhung */
1957 +/* gate means clock power down */
1958 +static int g_clk_gate = 0;
1959 +#define msdc_gate_clock(id) \
1961 + g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
1963 +/* not like power down register. 1 means clock on. */
1964 +#define msdc_ungate_clock(id) \
1966 + g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
1969 +// do we need sync object or not
1970 +void msdc_clk_status(int * status)
1972 + *status = g_clk_gate;
1974 +#endif /* end of --- */
1976 +/* +++ by chhung */
1977 +struct msdc_hw msdc0_hw = {
1979 + .cmd_edge = MSDC_SMPL_FALLING,
1980 + .data_edge = MSDC_SMPL_FALLING,
1986 + .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
1987 +// .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
1990 +static struct resource mtk_sd_resources[] = {
1992 + .start = RALINK_MSDC_BASE,
1993 + .end = RALINK_MSDC_BASE+0x3fff,
1994 + .flags = IORESOURCE_MEM,
1997 + .start = IRQ_SDC, /*FIXME*/
1998 + .end = IRQ_SDC, /*FIXME*/
1999 + .flags = IORESOURCE_IRQ,
2003 +static struct platform_device mtk_sd_device = {
2006 + .num_resources = ARRAY_SIZE(mtk_sd_resources),
2007 + .resource = mtk_sd_resources,
2011 +static int msdc_rsp[] = {
2012 + 0, /* RESP_NONE */
2023 +/* For Inhanced DMA */
2024 +#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
2026 + ((gpd_t*)gpd)->extlen = extlen; \
2027 + ((gpd_t*)gpd)->cmd = cmd; \
2028 + ((gpd_t*)gpd)->arg = arg; \
2029 + ((gpd_t*)gpd)->blknum = blknum; \
2032 +#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
2034 + BUG_ON(dlen > 0xFFFFUL); \
2035 + ((bd_t*)bd)->blkpad = blkpad; \
2036 + ((bd_t*)bd)->dwpad = dwpad; \
2037 + ((bd_t*)bd)->ptr = (void*)dptr; \
2038 + ((bd_t*)bd)->buflen = dlen; \
2041 +#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
2042 +#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
2043 +#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
2044 +#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
2045 +#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
2046 +#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
2049 +#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
2050 +#define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
2052 +#define msdc_retry(expr,retry,cnt) \
2054 + int backup = cnt; \
2056 + if (!(expr)) break; \
2057 + if (cnt-- == 0) { \
2058 + retry--; mdelay(1); cnt = backup; \
2061 + WARN_ON(retry == 0); \
2064 +#if 0 /* --- by chhung */
2065 +#define msdc_reset() \
2067 + int retry = 3, cnt = 1000; \
2068 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2070 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2073 +#define msdc_reset() \
2075 + int retry = 3, cnt = 1000; \
2076 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2077 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2079 +#endif /* end of +/- */
2081 +#define msdc_clr_int() \
2083 + volatile u32 val = sdr_read32(MSDC_INT); \
2084 + sdr_write32(MSDC_INT, val); \
2087 +#define msdc_clr_fifo() \
2089 + int retry = 3, cnt = 1000; \
2090 + sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
2091 + msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
2094 +#define msdc_irq_save(val) \
2096 + val = sdr_read32(MSDC_INTEN); \
2097 + sdr_clr_bits(MSDC_INTEN, val); \
2100 +#define msdc_irq_restore(val) \
2102 + sdr_set_bits(MSDC_INTEN, val); \
2105 +/* clock source for host: global */
2106 +#if defined (CONFIG_SOC_MT7620)
2107 +static u32 hclks[] = {48000000}; /* +/- by chhung */
2108 +#elif defined (CONFIG_SOC_MT7621)
2109 +static u32 hclks[] = {50000000}; /* +/- by chhung */
2112 +//============================================
2113 +// the power for msdc host controller: global
2114 +// always keep the VMC on.
2115 +//============================================
2116 +#define msdc_vcore_on(host) \
2118 + INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
2119 + (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
2121 +#define msdc_vcore_off(host) \
2123 + INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
2124 + (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
2127 +//====================================
2128 +// the vdd output for card: global
2129 +// always keep the VMCH on.
2130 +//====================================
2131 +#define msdc_vdd_on(host) \
2133 + (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
2135 +#define msdc_vdd_off(host) \
2137 + (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
2140 +#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
2141 +#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
2143 +#define sdc_send_cmd(cmd,arg) \
2145 + sdr_write32(SDC_ARG, (arg)); \
2146 + sdr_write32(SDC_CMD, (cmd)); \
2149 +// can modify to read h/w register.
2150 +//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
2151 +#define is_card_present(h) (((struct msdc_host*)(h))->card_inserted)
2153 +/* +++ by chhung */
2154 +#ifndef __ASSEMBLY__
2155 +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
2157 +#define PHYSADDR(a) ((a) & 0x1fffffff)
2160 +static unsigned int msdc_do_command(struct msdc_host *host,
2161 + struct mmc_command *cmd,
2163 + unsigned long timeout);
2165 +static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
2167 +#ifdef MT6575_SD_DEBUG
2168 +static void msdc_dump_card_status(struct msdc_host *host, u32 status)
2170 + static char *state[] = {
2180 + "Reserved", /* 9 */
2181 + "Reserved", /* 10 */
2182 + "Reserved", /* 11 */
2183 + "Reserved", /* 12 */
2184 + "Reserved", /* 13 */
2185 + "Reserved", /* 14 */
2186 + "I/O mode", /* 15 */
2188 + if (status & R1_OUT_OF_RANGE)
2189 + N_MSG(RSP, "[CARD_STATUS] Out of Range");
2190 + if (status & R1_ADDRESS_ERROR)
2191 + N_MSG(RSP, "[CARD_STATUS] Address Error");
2192 + if (status & R1_BLOCK_LEN_ERROR)
2193 + N_MSG(RSP, "[CARD_STATUS] Block Len Error");
2194 + if (status & R1_ERASE_SEQ_ERROR)
2195 + N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
2196 + if (status & R1_ERASE_PARAM)
2197 + N_MSG(RSP, "[CARD_STATUS] Erase Param");
2198 + if (status & R1_WP_VIOLATION)
2199 + N_MSG(RSP, "[CARD_STATUS] WP Violation");
2200 + if (status & R1_CARD_IS_LOCKED)
2201 + N_MSG(RSP, "[CARD_STATUS] Card is Locked");
2202 + if (status & R1_LOCK_UNLOCK_FAILED)
2203 + N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
2204 + if (status & R1_COM_CRC_ERROR)
2205 + N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
2206 + if (status & R1_ILLEGAL_COMMAND)
2207 + N_MSG(RSP, "[CARD_STATUS] Illegal Command");
2208 + if (status & R1_CARD_ECC_FAILED)
2209 + N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
2210 + if (status & R1_CC_ERROR)
2211 + N_MSG(RSP, "[CARD_STATUS] CC Error");
2212 + if (status & R1_ERROR)
2213 + N_MSG(RSP, "[CARD_STATUS] Error");
2214 + if (status & R1_UNDERRUN)
2215 + N_MSG(RSP, "[CARD_STATUS] Underrun");
2216 + if (status & R1_OVERRUN)
2217 + N_MSG(RSP, "[CARD_STATUS] Overrun");
2218 + if (status & R1_CID_CSD_OVERWRITE)
2219 + N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
2220 + if (status & R1_WP_ERASE_SKIP)
2221 + N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
2222 + if (status & R1_CARD_ECC_DISABLED)
2223 + N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
2224 + if (status & R1_ERASE_RESET)
2225 + N_MSG(RSP, "[CARD_STATUS] Erase Reset");
2226 + if (status & R1_READY_FOR_DATA)
2227 + N_MSG(RSP, "[CARD_STATUS] Ready for Data");
2228 + if (status & R1_SWITCH_ERROR)
2229 + N_MSG(RSP, "[CARD_STATUS] Switch error");
2230 + if (status & R1_APP_CMD)
2231 + N_MSG(RSP, "[CARD_STATUS] App Command");
2233 + N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
2236 +static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
2238 + if (resp & (1 << 7))
2239 + N_MSG(RSP, "[OCR] Low Voltage Range");
2240 + if (resp & (1 << 15))
2241 + N_MSG(RSP, "[OCR] 2.7-2.8 volt");
2242 + if (resp & (1 << 16))
2243 + N_MSG(RSP, "[OCR] 2.8-2.9 volt");
2244 + if (resp & (1 << 17))
2245 + N_MSG(RSP, "[OCR] 2.9-3.0 volt");
2246 + if (resp & (1 << 18))
2247 + N_MSG(RSP, "[OCR] 3.0-3.1 volt");
2248 + if (resp & (1 << 19))
2249 + N_MSG(RSP, "[OCR] 3.1-3.2 volt");
2250 + if (resp & (1 << 20))
2251 + N_MSG(RSP, "[OCR] 3.2-3.3 volt");
2252 + if (resp & (1 << 21))
2253 + N_MSG(RSP, "[OCR] 3.3-3.4 volt");
2254 + if (resp & (1 << 22))
2255 + N_MSG(RSP, "[OCR] 3.4-3.5 volt");
2256 + if (resp & (1 << 23))
2257 + N_MSG(RSP, "[OCR] 3.5-3.6 volt");
2258 + if (resp & (1 << 24))
2259 + N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
2260 + if (resp & (1 << 30))
2261 + N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
2262 + if (resp & (1 << 31))
2263 + N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
2265 + N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
2268 +static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
2270 + u32 status = (((resp >> 15) & 0x1) << 23) |
2271 + (((resp >> 14) & 0x1) << 22) |
2272 + (((resp >> 13) & 0x1) << 19) |
2275 + N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
2276 + msdc_dump_card_status(host, status);
2279 +static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
2281 + u32 flags = (resp >> 8) & 0xFF;
2282 + char *state[] = {"DIS", "CMD", "TRN", "RFU"};
2284 + if (flags & (1 << 7))
2285 + N_MSG(RSP, "[IO] COM_CRC_ERR");
2286 + if (flags & (1 << 6))
2287 + N_MSG(RSP, "[IO] Illgal command");
2288 + if (flags & (1 << 3))
2289 + N_MSG(RSP, "[IO] Error");
2290 + if (flags & (1 << 2))
2291 + N_MSG(RSP, "[IO] RFU");
2292 + if (flags & (1 << 1))
2293 + N_MSG(RSP, "[IO] Function number error");
2294 + if (flags & (1 << 0))
2295 + N_MSG(RSP, "[IO] Out of range");
2297 + N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
2301 +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
2303 + u32 base = host->base;
2304 + u32 timeout, clk_ns;
2306 + host->timeout_ns = ns;
2307 + host->timeout_clks = clks;
2309 + clk_ns = 1000000000UL / host->sclk;
2310 + timeout = ns / clk_ns + clks;
2311 + timeout = timeout >> 16; /* in 65536 sclk cycle unit */
2312 + timeout = timeout > 1 ? timeout - 1 : 0;
2313 + timeout = timeout > 255 ? 255 : timeout;
2315 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
2317 + N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
2318 + ns, clks, timeout + 1);
2321 +/* msdc_eirq_sdio() will be called when EIRQ(for WIFI) */
2322 +static void msdc_eirq_sdio(void *data)
2324 + struct msdc_host *host = (struct msdc_host *)data;
2326 + N_MSG(INT, "SDIO EINT");
2328 + mmc_signal_sdio_irq(host->mmc);
2331 +/* msdc_eirq_cd will not be used! We not using EINT for card detection. */
2332 +static void msdc_eirq_cd(void *data)
2334 + struct msdc_host *host = (struct msdc_host *)data;
2336 + N_MSG(INT, "CD EINT");
2339 + tasklet_hi_schedule(&host->card_tasklet);
2341 + schedule_delayed_work(&host->card_delaywork, HZ);
2346 +static void msdc_tasklet_card(unsigned long arg)
2348 + struct msdc_host *host = (struct msdc_host *)arg;
2350 +static void msdc_tasklet_card(struct work_struct *work)
2352 + struct msdc_host *host = (struct msdc_host *)container_of(work,
2353 + struct msdc_host, card_delaywork.work);
2355 + struct msdc_hw *hw = host->hw;
2356 + u32 base = host->base;
2361 + spin_lock(&host->lock);
2363 + if (hw->get_cd_status) { // NULL
2364 + inserted = hw->get_cd_status();
2366 + status = sdr_read32(MSDC_PS);
2367 + if (cd_active_low)
2368 + inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
2370 + inserted = (status & MSDC_PS_CDSTS) ? 1 : 0;
2374 + change = host->card_inserted ^ inserted;
2375 + host->card_inserted = inserted;
2377 + if (change && !host->suspend) {
2379 + host->mmc->f_max = HOST_MAX_MCLK; // work around
2381 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2383 +#else /* Make sure: handle the last interrupt */
2384 + host->card_inserted = inserted;
2386 + if (!host->suspend) {
2387 + host->mmc->f_max = HOST_MAX_MCLK;
2388 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2391 + IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
2394 + spin_unlock(&host->lock);
2397 +#if 0 /* --- by chhung */
2399 +static u8 clk_src_bit[4] = {
2403 +static void msdc_select_clksrc(struct msdc_host* host, unsigned char clksrc)
2406 + u32 base = host->base;
2408 + BUG_ON(clksrc > 3);
2409 + INIT_MSG("set clock source to <%d>", clksrc);
2411 + val = sdr_read32(MSDC_CLKSRC_REG);
2412 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2413 + val &= ~(0x3 << clk_src_bit[host->id]);
2414 + val |= clksrc << clk_src_bit[host->id];
2416 + val &= ~0x3; val |= clksrc;
2418 + sdr_write32(MSDC_CLKSRC_REG, val);
2420 + host->hclk = hclks[clksrc];
2421 + host->hw->clk_src = clksrc;
2423 +#endif /* end of --- */
2425 +static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
2427 + //struct msdc_hw *hw = host->hw;
2428 + u32 base = host->base;
2433 + u32 hclk = host->hclk;
2434 + //u8 clksrc = hw->clk_src;
2436 + if (!hz) { // set mmc system clock to 0 ?
2437 + //ERR_MSG("set mclk to 0!!!");
2442 + msdc_irq_save(flags);
2444 +#if defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7628_FPGA)
2445 + mode = 0x0; /* use divisor */
2446 + if (hz >= (hclk >> 1)) {
2447 + div = 0; /* mean div = 1/2 */
2448 + sclk = hclk >> 1; /* sclk = clk / 2 */
2450 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2451 + sclk = (hclk >> 2) / div;
2455 + mode = 0x2; /* ddr mode and use divisor */
2456 + if (hz >= (hclk >> 2)) {
2457 + div = 1; /* mean div = 1/4 */
2458 + sclk = hclk >> 2; /* sclk = clk / 4 */
2460 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2461 + sclk = (hclk >> 2) / div;
2463 + } else if (hz >= hclk) { /* bug fix */
2464 + mode = 0x1; /* no divisor and divisor is ignored */
2468 + mode = 0x0; /* use divisor */
2469 + if (hz >= (hclk >> 1)) {
2470 + div = 0; /* mean div = 1/2 */
2471 + sclk = hclk >> 1; /* sclk = clk / 2 */
2473 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2474 + sclk = (hclk >> 2) / div;
2478 + /* set clock mode and divisor */
2479 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
2480 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
2482 + /* wait clock stable */
2483 + while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
2485 + host->sclk = sclk;
2487 + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
2489 + INIT_MSG("================");
2490 + INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz/1000, hclk/1000, sclk/1000);
2491 + INIT_MSG("================");
2493 + msdc_irq_restore(flags);
2496 +/* Fix me. when need to abort */
2497 +static void msdc_abort_data(struct msdc_host *host)
2499 + u32 base = host->base;
2500 + struct mmc_command *stop = host->mrq->stop;
2502 + ERR_MSG("Need to Abort. dma<%d>", host->dma_xfer);
2508 + // need to check FIFO count 0 ?
2510 + if (stop) { /* try to stop, but may not success */
2511 + ERR_MSG("stop when abort CMD<%d>", stop->opcode);
2512 + (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
2515 + //if (host->mclk >= 25000000) {
2516 + // msdc_set_mclk(host, 0, host->mclk >> 1);
2520 +#if 0 /* --- by chhung */
2521 +static void msdc_pin_config(struct msdc_host *host, int mode)
2523 + struct msdc_hw *hw = host->hw;
2524 + u32 base = host->base;
2525 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2527 + /* Config WP pin */
2528 + if (hw->flags & MSDC_WP_PIN_EN) {
2529 + if (hw->config_gpio_pin) /* NULL */
2530 + hw->config_gpio_pin(MSDC_WP_PIN, pull);
2534 + case MSDC_PIN_PULL_UP:
2535 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
2536 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2537 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
2538 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2539 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
2540 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2542 + case MSDC_PIN_PULL_DOWN:
2543 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2544 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
2545 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2546 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
2547 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2548 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
2550 + case MSDC_PIN_PULL_NONE:
2552 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2553 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2554 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2555 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2556 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2557 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2561 + N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
2562 + mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
2565 +void msdc_pin_reset(struct msdc_host *host, int mode)
2567 + struct msdc_hw *hw = (struct msdc_hw *)host->hw;
2568 + u32 base = host->base;
2569 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2571 + /* Config reset pin */
2572 + if (hw->flags & MSDC_RST_PIN_EN) {
2573 + if (hw->config_gpio_pin) /* NULL */
2574 + hw->config_gpio_pin(MSDC_RST_PIN, pull);
2576 + if (mode == MSDC_PIN_PULL_UP) {
2577 + sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2579 + sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2584 +static void msdc_core_power(struct msdc_host *host, int on)
2586 + N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
2587 + on ? "on" : "off", "core", host->core_power, on);
2589 + if (on && host->core_power == 0) {
2590 + msdc_vcore_on(host);
2591 + host->core_power = 1;
2593 + } else if (!on && host->core_power == 1) {
2594 + msdc_vcore_off(host);
2595 + host->core_power = 0;
2600 +static void msdc_host_power(struct msdc_host *host, int on)
2602 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
2605 + //msdc_core_power(host, 1); // need do card detection.
2606 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
2608 + msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
2609 + //msdc_core_power(host, 0);
2613 +static void msdc_card_power(struct msdc_host *host, int on)
2615 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
2618 + msdc_pin_config(host, MSDC_PIN_PULL_UP);
2619 + if (host->hw->ext_power_on) {
2620 + host->hw->ext_power_on();
2622 + //msdc_vdd_on(host); // need todo card detection.
2626 + if (host->hw->ext_power_off) {
2627 + host->hw->ext_power_off();
2629 + //msdc_vdd_off(host);
2631 + msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
2636 +static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
2638 + N_MSG(CFG, "Set power mode(%d)", mode);
2640 + if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
2641 + msdc_host_power(host, 1);
2642 + msdc_card_power(host, 1);
2643 + } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
2644 + msdc_card_power(host, 0);
2645 + msdc_host_power(host, 0);
2647 + host->power_mode = mode;
2649 +#endif /* end of --- */
2653 + register as callback function of WIFI(combo_sdio_register_pm) .
2654 + can called by msdc_drv_suspend/resume too.
2656 +static void msdc_pm(pm_message_t state, void *data)
2658 + struct msdc_host *host = (struct msdc_host *)data;
2659 + int evt = state.event;
2661 + if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
2662 + INIT_MSG("USR_%s: suspend<%d> power<%d>",
2663 + evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
2664 + host->suspend, host->power_mode);
2667 + if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
2668 + if (host->suspend) /* already suspend */ /* default 0*/
2671 + /* for memory card. already power off by mmc */
2672 + if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
2675 + host->suspend = 1;
2676 + host->pm_state = state; /* default PMSG_RESUME */
2678 + INIT_MSG("%s Suspend", evt == PM_EVENT_SUSPEND ? "PM" : "USR");
2679 + if(host->hw->flags & MSDC_SYS_SUSPEND) /* set for card */
2680 + (void)mmc_suspend_host(host->mmc);
2682 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* just for double confirm */ /* --- by chhung */
2683 + mmc_remove_host(host->mmc);
2685 + } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
2686 + if (!host->suspend){
2687 + //ERR_MSG("warning: already resume");
2691 + /* No PM resume when USR suspend */
2692 + if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
2693 + ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
2697 + host->suspend = 0;
2698 + host->pm_state = state;
2700 + INIT_MSG("%s Resume", evt == PM_EVENT_RESUME ? "PM" : "USR");
2701 + if(host->hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
2702 + (void)mmc_resume_host(host->mmc);
2705 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* --- by chhung */
2706 + mmc_add_host(host->mmc);
2712 +/*--------------------------------------------------------------------------*/
2713 +/* mmc_host_ops members */
2714 +/*--------------------------------------------------------------------------*/
2715 +static unsigned int msdc_command_start(struct msdc_host *host,
2716 + struct mmc_command *cmd,
2717 + int tune, /* not used */
2718 + unsigned long timeout)
2720 + u32 base = host->base;
2721 + u32 opcode = cmd->opcode;
2723 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2724 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2725 + MSDC_INT_ACMD19_DONE;
2728 + unsigned long tmo;
2730 + /* Protocol layer does not provide response type, but our hardware needs
2731 + * to know exact type, not just size!
2733 + if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
2735 + else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
2736 + resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
2737 + else if (opcode == MMC_FAST_IO)
2739 + else if (opcode == MMC_GO_IRQ_STATE)
2741 + else if (opcode == MMC_SELECT_CARD)
2742 + resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
2743 + else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
2744 + resp = RESP_R1; /* SDIO workaround. */
2745 + else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
2748 + switch (mmc_resp_type(cmd)) {
2761 + case MMC_RSP_NONE:
2770 + * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
2771 + * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
2773 + rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
2775 + if (opcode == MMC_READ_MULTIPLE_BLOCK) {
2776 + rawcmd |= (2 << 11);
2777 + } else if (opcode == MMC_READ_SINGLE_BLOCK) {
2778 + rawcmd |= (1 << 11);
2779 + } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
2780 + rawcmd |= ((2 << 11) | (1 << 13));
2781 + } else if (opcode == MMC_WRITE_BLOCK) {
2782 + rawcmd |= ((1 << 11) | (1 << 13));
2783 + } else if (opcode == SD_IO_RW_EXTENDED) {
2784 + if (cmd->data->flags & MMC_DATA_WRITE)
2785 + rawcmd |= (1 << 13);
2786 + if (cmd->data->blocks > 1)
2787 + rawcmd |= (2 << 11);
2789 + rawcmd |= (1 << 11);
2790 + } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
2791 + rawcmd |= (1 << 14);
2792 + } else if ((opcode == SD_APP_SEND_SCR) ||
2793 + (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
2794 + (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2795 + (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2796 + (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
2797 + rawcmd |= (1 << 11);
2798 + } else if (opcode == MMC_STOP_TRANSMISSION) {
2799 + rawcmd |= (1 << 14);
2800 + rawcmd &= ~(0x0FFF << 16);
2803 + N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode , rawcmd, cmd->arg);
2805 + tmo = jiffies + timeout;
2807 + if (opcode == MMC_SEND_STATUS) {
2809 + if (!sdc_is_cmd_busy())
2812 + if (time_after(jiffies, tmo)) {
2813 + ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
2814 + cmd->error = (unsigned int)-ETIMEDOUT;
2821 + if (!sdc_is_busy())
2823 + if (time_after(jiffies, tmo)) {
2824 + ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
2825 + cmd->error = (unsigned int)-ETIMEDOUT;
2832 + //BUG_ON(in_interrupt());
2834 + host->cmd_rsp = resp;
2836 + init_completion(&host->cmd_done);
2838 + sdr_set_bits(MSDC_INTEN, wints);
2839 + sdc_send_cmd(rawcmd, cmd->arg);
2842 + return cmd->error;
2845 +static unsigned int msdc_command_resp(struct msdc_host *host,
2846 + struct mmc_command *cmd,
2848 + unsigned long timeout)
2850 + u32 base = host->base;
2851 + u32 opcode = cmd->opcode;
2854 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2855 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2856 + MSDC_INT_ACMD19_DONE;
2858 + resp = host->cmd_rsp;
2860 + BUG_ON(in_interrupt());
2861 + //init_completion(&host->cmd_done);
2862 + //sdr_set_bits(MSDC_INTEN, wints);
2864 + spin_unlock(&host->lock);
2865 + if(!wait_for_completion_timeout(&host->cmd_done, 10*timeout)){
2866 + ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
2867 + cmd->error = (unsigned int)-ETIMEDOUT;
2870 + spin_lock(&host->lock);
2872 + sdr_clr_bits(MSDC_INTEN, wints);
2876 +#ifdef MT6575_SD_DEBUG
2879 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
2882 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
2883 + opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
2884 + cmd->resp[2], cmd->resp[3]);
2886 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
2887 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
2888 + opcode, cmd->error, resp, cmd->resp[0]);
2889 + if (cmd->error == 0) {
2893 + msdc_dump_card_status(host, cmd->resp[0]);
2896 + msdc_dump_ocr_reg(host, cmd->resp[0]);
2899 + msdc_dump_io_resp(host, cmd->resp[0]);
2902 + msdc_dump_rca_resp(host, cmd->resp[0]);
2910 + /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
2913 + return cmd->error;
2916 + /* memory card CRC */
2917 + if(host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
2918 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
2919 + msdc_abort_data(host);
2921 + /* do basic: reset*/
2926 + cmd->error = msdc_tune_cmdrsp(host,cmd);
2930 + /* if (resp == RESP_R1B) {
2931 + while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);
2933 + /* CMD12 Error Handle */
2935 + return cmd->error;
2938 +static unsigned int msdc_do_command(struct msdc_host *host,
2939 + struct mmc_command *cmd,
2941 + unsigned long timeout)
2943 + if (msdc_command_start(host, cmd, tune, timeout))
2946 + if (msdc_command_resp(host, cmd, tune, timeout))
2951 + N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
2952 + return cmd->error;
2955 +/* The abort condition when PIO read/write
2958 +static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
2961 + u32 base = host->base;
2963 + if (atomic_read(&host->abort)) {
2967 + if (time_after(jiffies, tmo)) {
2968 + data->error = (unsigned int)-ETIMEDOUT;
2969 + ERR_MSG("XXX PIO Data Timeout: CMD<%d>", host->mrq->cmd->opcode);
2977 + ERR_MSG("msdc pio find abort");
2983 + Need to add a timeout, or WDT timeout, system reboot.
2985 +// pio mode data read/write
2986 +static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
2988 + struct scatterlist *sg = data->sg;
2989 + u32 base = host->base;
2990 + u32 num = data->sg_len;
2994 + u32 count, size = 0;
2995 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
2996 + unsigned long tmo = jiffies + DAT_TIMEOUT;
2998 + sdr_set_bits(MSDC_INTEN, wints);
3000 + left = sg_dma_len(sg);
3001 + ptr = sg_virt(sg);
3003 + if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
3004 + count = MSDC_FIFO_THD >> 2;
3006 + *ptr++ = msdc_fifo_read32();
3007 + } while (--count);
3008 + left -= MSDC_FIFO_THD;
3009 + } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
3010 + while (left > 3) {
3011 + *ptr++ = msdc_fifo_read32();
3015 + u8ptr = (u8 *)ptr;
3017 + * u8ptr++ = msdc_fifo_read8();
3022 + if (msdc_pio_abort(host, data, tmo)) {
3026 + size += sg_dma_len(sg);
3027 + sg = sg_next(sg); num--;
3030 + data->bytes_xfered += size;
3031 + N_MSG(FIO, " PIO Read<%d>bytes", size);
3033 + sdr_clr_bits(MSDC_INTEN, wints);
3034 + if(data->error) ERR_MSG("read pio data->error<%d> left<%d> size<%d>", data->error, left, size);
3035 + return data->error;
3038 +/* please make sure won't using PIO when size >= 512
3039 + which means, memory card block read/write won't using pio
3040 + then don't need to handle the CMD12 when data error.
3042 +static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
3044 + u32 base = host->base;
3045 + struct scatterlist *sg = data->sg;
3046 + u32 num = data->sg_len;
3050 + u32 count, size = 0;
3051 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3052 + unsigned long tmo = jiffies + DAT_TIMEOUT;
3054 + sdr_set_bits(MSDC_INTEN, wints);
3056 + left = sg_dma_len(sg);
3057 + ptr = sg_virt(sg);
3060 + if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3061 + count = MSDC_FIFO_SZ >> 2;
3063 + msdc_fifo_write32(*ptr); ptr++;
3064 + } while (--count);
3065 + left -= MSDC_FIFO_SZ;
3066 + } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3067 + while (left > 3) {
3068 + msdc_fifo_write32(*ptr); ptr++;
3074 + msdc_fifo_write8(*u8ptr); u8ptr++;
3079 + if (msdc_pio_abort(host, data, tmo)) {
3083 + size += sg_dma_len(sg);
3084 + sg = sg_next(sg); num--;
3087 + data->bytes_xfered += size;
3088 + N_MSG(FIO, " PIO Write<%d>bytes", size);
3089 + if(data->error) ERR_MSG("write pio data->error<%d>", data->error);
3091 + sdr_clr_bits(MSDC_INTEN, wints);
3092 + return data->error;
3095 +#if 0 /* --- by chhung */
3096 +// DMA resume / start / stop
3097 +static void msdc_dma_resume(struct msdc_host *host)
3099 + u32 base = host->base;
3101 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
3103 + N_MSG(DMA, "DMA resume");
3105 +#endif /* end of --- */
3107 +static void msdc_dma_start(struct msdc_host *host)
3109 + u32 base = host->base;
3110 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3112 + sdr_set_bits(MSDC_INTEN, wints);
3113 + //dsb(); /* --- by chhung */
3114 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
3116 + N_MSG(DMA, "DMA start");
3119 +static void msdc_dma_stop(struct msdc_host *host)
3121 + u32 base = host->base;
3122 + //u32 retries=500;
3123 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3125 + N_MSG(DMA, "DMA status: 0x%.8x",sdr_read32(MSDC_DMA_CFG));
3126 + //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3128 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
3129 + while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3131 + //dsb(); /* --- by chhung */
3132 + sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
3134 + N_MSG(DMA, "DMA stop");
3137 +#if 0 /* --- by chhung */
3138 +/* dump a gpd list */
3139 +static void msdc_dma_dump(struct msdc_host *host, struct msdc_dma *dma)
3141 + gpd_t *gpd = dma->gpd;
3142 + bd_t *bd = dma->bd;
3147 + if (dma->mode != MSDC_MODE_DMA_DESC) {
3151 + ERR_MSG("try to dump gpd and bd");
3154 + ERR_MSG(".gpd<0x%.8x> gpd_phy<0x%.8x>", (int)gpd, (int)dma->gpd_addr);
3155 + ERR_MSG("...hwo <%d>", gpd->hwo );
3156 + ERR_MSG("...bdp <%d>", gpd->bdp );
3157 + ERR_MSG("...chksum<0x%.8x>", gpd->chksum );
3158 + //ERR_MSG("...intr <0x%.8x>", gpd->intr );
3159 + ERR_MSG("...next <0x%.8x>", (int)gpd->next );
3160 + ERR_MSG("...ptr <0x%.8x>", (int)gpd->ptr );
3161 + ERR_MSG("...buflen<0x%.8x>", gpd->buflen );
3162 + //ERR_MSG("...extlen<0x%.8x>", gpd->extlen );
3163 + //ERR_MSG("...arg <0x%.8x>", gpd->arg );
3164 + //ERR_MSG("...blknum<0x%.8x>", gpd->blknum );
3165 + //ERR_MSG("...cmd <0x%.8x>", gpd->cmd );
3168 + ERR_MSG(".bd<0x%.8x> bd_phy<0x%.8x> gpd_ptr<0x%.8x>", (int)bd, (int)dma->bd_addr, (int)gpd->ptr);
3170 + p_to_v = ((u32)bd - (u32)dma->bd_addr);
3172 + ERR_MSG(".bd[%d]", i); i++;
3173 + ERR_MSG("...eol <%d>", ptr->eol );
3174 + ERR_MSG("...chksum<0x%.8x>", ptr->chksum );
3175 + //ERR_MSG("...blkpad<0x%.8x>", ptr->blkpad );
3176 + //ERR_MSG("...dwpad <0x%.8x>", ptr->dwpad );
3177 + ERR_MSG("...next <0x%.8x>", (int)ptr->next );
3178 + ERR_MSG("...ptr <0x%.8x>", (int)ptr->ptr );
3179 + ERR_MSG("...buflen<0x%.8x>", (int)ptr->buflen );
3181 + if (ptr->eol == 1) {
3185 + /* find the next bd, virtual address of ptr->next */
3186 + /* don't need to enable when use malloc */
3187 + //BUG_ON( (ptr->next + p_to_v)!=(ptr+1) );
3188 + //ERR_MSG(".next bd<0x%.8x><0x%.8x>", (ptr->next + p_to_v), (ptr+1));
3192 + ERR_MSG("dump gpd and bd finished");
3194 +#endif /* end of --- */
3196 +/* calc checksum */
3197 +static u8 msdc_dma_calcs(u8 *buf, u32 len)
3200 + for (i = 0; i < len; i++) {
3203 + return 0xFF - (u8)sum;
3206 +/* gpd bd setup + dma registers */
3207 +static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
3209 + u32 base = host->base;
3210 + u32 sglen = dma->sglen;
3211 + //u32 i, j, num, bdlen, arg, xfersz;
3212 + u32 j, num, bdlen;
3213 + u8 blkpad, dwpad, chksum;
3214 + struct scatterlist *sg = dma->sg;
3218 + switch (dma->mode) {
3219 + case MSDC_MODE_DMA_BASIC:
3220 + BUG_ON(dma->xfersz > 65535);
3221 + BUG_ON(dma->sglen != 1);
3222 + sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
3223 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
3224 +//#if defined (CONFIG_RALINK_MT7620)
3225 + if (ralink_soc == MT762X_SOC_MT7620A)
3226 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
3227 +//#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3229 + sdr_write32((volatile u32*)(RALINK_MSDC_BASE+0xa8), sg_dma_len(sg));
3231 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3232 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
3234 + case MSDC_MODE_DMA_DESC:
3235 + blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
3236 + dwpad = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
3237 + chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
3239 + /* calculate the required number of gpd */
3240 + num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
3249 + gpd->hwo = 1; /* hw will clear it */
3251 + gpd->chksum = 0; /* need to clear first. */
3252 + gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
3255 + for (j = 0; j < bdlen; j++) {
3256 + msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
3257 + if(j == bdlen - 1) {
3258 + bd[j].eol = 1; /* the last bd */
3262 + bd[j].chksum = 0; /* checksume need to clear first */
3263 + bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
3267 + dma->used_gpd += 2;
3268 + dma->used_bd += bdlen;
3270 + sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
3271 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3272 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
3274 + sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
3281 + N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3282 + N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3283 + N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3288 +static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
3289 + struct scatterlist *sg, unsigned int sglen)
3291 + BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
3294 + dma->flags = DMA_FLAG_EN_CHKSUM;
3295 + //dma->flags = DMA_FLAG_NONE; /* CHECKME */
3296 + dma->sglen = sglen;
3297 + dma->xfersz = host->xfer_size;
3298 + dma->burstsz = MSDC_BRUST_64B;
3300 + if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
3301 + dma->mode = MSDC_MODE_DMA_BASIC;
3303 + dma->mode = MSDC_MODE_DMA_DESC;
3305 + N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen, dma->xfersz);
3307 + msdc_dma_config(host, dma);
3309 + /*if (dma->mode == MSDC_MODE_DMA_DESC) {
3310 + //msdc_dma_dump(host, dma);
3314 +/* set block number before send command */
3315 +static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
3317 + u32 base = host->base;
3319 + sdr_write32(SDC_BLK_NUM, blknum);
3322 +static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
3324 + struct msdc_host *host = mmc_priv(mmc);
3325 + struct mmc_command *cmd;
3326 + struct mmc_data *data;
3327 + u32 base = host->base;
3329 + unsigned int left=0;
3330 + int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
3335 + BUG_ON(mmc == NULL);
3336 + BUG_ON(mrq == NULL);
3339 + atomic_set(&host->abort, 0);
3342 + data = mrq->cmd->data;
3344 +#if 0 /* --- by chhung */
3345 + //if(host->id ==1){
3346 + N_MSG(OPS, "enable clock!");
3347 + msdc_ungate_clock(host->id);
3349 +#endif /* end of --- */
3352 + send_type=SND_CMD;
3353 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3357 + BUG_ON(data->blksz > HOST_MAX_BLKSZ);
3358 + send_type=SND_DAT;
3361 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3362 + host->data = data;
3363 + host->xfer_size = data->blocks * data->blksz;
3364 + host->blksz = data->blksz;
3366 + /* deside the transfer mode */
3367 + if (drv_mode[host->id] == MODE_PIO) {
3368 + host->dma_xfer = dma = 0;
3369 + } else if (drv_mode[host->id] == MODE_DMA) {
3370 + host->dma_xfer = dma = 1;
3371 + } else if (drv_mode[host->id] == MODE_SIZE_DEP) {
3372 + host->dma_xfer = dma = ((host->xfer_size >= dma_size[host->id]) ? 1 : 0);
3376 + if ((host->timeout_ns != data->timeout_ns) ||
3377 + (host->timeout_clks != data->timeout_clks)) {
3378 + msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
3382 + msdc_set_blknum(host, data->blocks);
3383 + //msdc_clr_fifo(); /* no need */
3386 + msdc_dma_on(); /* enable DMA mode first!! */
3387 + init_completion(&host->xfer_done);
3389 + /* start the command first*/
3390 + if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
3393 + dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
3394 + (void)dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3395 + msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
3397 + /* then wait command done */
3398 + if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
3401 + /* for read, the data coming too fast, then CRC error
3402 + start DMA no business with CRC. */
3403 + //init_completion(&host->xfer_done);
3404 + msdc_dma_start(host);
3406 + spin_unlock(&host->lock);
3407 + if(!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)){
3408 + ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
3409 + ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3410 + ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA));
3411 + ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3412 + ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3413 + data->error = (unsigned int)-ETIMEDOUT;
3419 + spin_lock(&host->lock);
3420 + msdc_dma_stop(host);
3422 + /* Firstly: send command */
3423 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3427 + /* Secondly: pio data phase */
3429 + if (msdc_pio_read(host, data)){
3433 + if (msdc_pio_write(host, data)) {
3438 + /* For write case: make sure contents in fifo flushed to device */
3441 + left=msdc_txfifocnt();
3445 + if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
3447 + /* Fix me: what about if data error, when stop ? how to? */
3451 + /* Fix me: read case: need to check CRC error */
3454 + /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
3455 + For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
3458 + /* try not to wait xfer_comp interrupt.
3459 + the next command will check SDC_BUSY.
3460 + SDC_BUSY means xfer_comp assert
3465 + /* Last: stop transfer */
3467 + if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
3474 + if (data != NULL) {
3475 + host->data = NULL;
3476 + host->dma_xfer = 0;
3479 + host->dma.used_bd = 0;
3480 + host->dma.used_gpd = 0;
3481 + dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3485 +#if 0 // don't stop twice!
3486 + if(host->hw->flags & MSDC_REMOVABLE && data->error) {
3487 + msdc_abort_data(host);
3488 + /* reset in IRQ, stop command has issued. -> No need */
3492 + N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio"),
3493 + (read ? "read ":"write") ,data->blksz, data->blocks, data->error);
3496 +#if 0 /* --- by chhung */
3498 + //if(host->id==1) {
3499 + if(send_type==SND_CMD) {
3500 + if(cmd->opcode == MMC_SEND_STATUS) {
3501 + if((cmd->resp[0] & CARD_READY_FOR_DATA) ||(CARD_CURRENT_STATE(cmd->resp[0]) != 7)){
3502 + N_MSG(OPS,"disable clock, CMD13 IDLE");
3503 + msdc_gate_clock(host->id);
3506 + N_MSG(OPS,"disable clock, CMD<%d>", cmd->opcode);
3507 + msdc_gate_clock(host->id);
3511 + N_MSG(OPS,"disable clock!!! Read CMD<%d>",cmd->opcode);
3512 + msdc_gate_clock(host->id);
3517 + msdc_gate_clock(host->id);
3519 +#endif /* end of --- */
3521 + if (mrq->cmd->error) host->error = 0x001;
3522 + if (mrq->data && mrq->data->error) host->error |= 0x010;
3523 + if (mrq->stop && mrq->stop->error) host->error |= 0x100;
3525 + //if (host->error) ERR_MSG("host->error<%d>", host->error);
3527 + return host->error;
3530 +static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
3532 + struct mmc_command cmd;
3533 + struct mmc_request mrq;
3536 + memset(&cmd, 0, sizeof(struct mmc_command));
3537 + cmd.opcode = MMC_APP_CMD;
3538 +#if 0 /* bug: we meet mmc->card is null when ACMD6 */
3539 + cmd.arg = mmc->card->rca << 16;
3541 + cmd.arg = host->app_cmd_arg;
3543 + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
3545 + memset(&mrq, 0, sizeof(struct mmc_request));
3546 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3549 + err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
3553 +static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
3556 + u32 base = host->base;
3557 + u32 rsmpl, cur_rsmpl, orig_rsmpl;
3558 + u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
3561 + /* ==== don't support 3.0 now ====
3563 + 2: PAD_CMD_RESP_RXDLY[26:22]
3564 + ==========================*/
3566 + // save the previous tune result
3567 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
3568 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
3572 + for (rsmpl = 0; rsmpl < 2; rsmpl++) {
3573 + /* Lv1: R_SMPL[1] */
3574 + cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
3579 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
3581 + if (host->app_cmd) {
3582 + result = msdc_app_cmd(host->mmc, host);
3584 + ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
3585 + host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
3589 + result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
3590 + ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
3591 + (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
3593 + if (result == 0) {
3596 + if (result != (unsigned int)(-EIO)) {
3597 + ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
3601 + /* should be EIO */
3602 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
3603 + msdc_abort_data(host);
3607 + /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
3608 + cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
3609 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
3610 + }while (++rrdly < 32);
3615 +/* Support SD2.0 Only */
3616 +static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
3618 + struct msdc_host *host = mmc_priv(mmc);
3619 + u32 base = host->base;
3622 + u32 rxdly, cur_rxdly0, cur_rxdly1;
3623 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3624 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3625 + u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
3626 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3627 + u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
3631 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
3633 + /* Tune Method 2. */
3634 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3638 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3639 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3644 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3646 + if (host->app_cmd) {
3647 + result = msdc_app_cmd(host->mmc, host);
3649 + ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
3653 + result = msdc_do_request(mmc,mrq);
3655 + sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
3656 + if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
3657 + ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
3658 + (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
3659 + sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
3661 + /* Fix me: result is 0, but dcrc is still exist */
3662 + if (result == 0 && dcrc == 0) {
3665 + /* there is a case: command timeout, and data phase not processed */
3666 + if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
3667 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3668 + result, mrq->cmd->error, mrq->data->error);
3674 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3675 + cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
3677 + /* E1 ECO. YD: Reverse */
3678 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3679 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3680 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3681 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3682 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3683 + orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
3684 + orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
3685 + orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
3686 + orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
3688 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3689 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3690 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3691 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3692 + orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
3693 + orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
3694 + orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
3695 + orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
3699 + cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3700 + cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3701 + cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3702 + cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3704 + cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3705 + cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3706 + cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3707 + cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3709 + cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
3710 + cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
3711 + cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
3712 + cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
3714 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3715 + cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
3717 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3718 + sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
3720 + } while (++rxdly < 32);
3726 +static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
3728 + struct msdc_host *host = mmc_priv(mmc);
3729 + u32 base = host->base;
3731 + u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
3732 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3733 + u32 rxdly, cur_rxdly0;
3734 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3735 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3739 + // MSDC_IOCON_DDR50CKD need to check. [Fix me]
3741 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
3742 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl );
3744 + /* Tune Method 2. just DAT0 */
3745 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3746 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3748 + /* E1 ECO. YD: Reverse */
3749 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3750 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3751 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3752 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3753 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3755 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3756 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3757 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3758 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3765 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3766 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3771 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3773 + if (host->app_cmd) {
3774 + result = msdc_app_cmd(host->mmc, host);
3776 + ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
3780 + result = msdc_do_request(mmc,mrq);
3782 + ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
3783 + result == 0 ? "PASS" : "FAIL",
3784 + cur_dsmpl, cur_wrrdly, cur_rxdly0);
3786 + if (result == 0) {
3790 + /* there is a case: command timeout, and data phase not processed */
3791 + if (mrq->data->error != (unsigned int)(-EIO)) {
3792 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3793 + result, mrq->cmd->error, mrq->data->error);
3798 + cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
3799 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
3800 + } while (++wrrdly < 32);
3802 + cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
3803 + cur_dat1 = orig_dat1;
3804 + cur_dat2 = orig_dat2;
3805 + cur_dat3 = orig_dat3;
3807 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3808 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3809 + } while (++rxdly < 32);
3815 +static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
3817 + struct mmc_command cmd;
3818 + struct mmc_request mrq;
3821 + memset(&cmd, 0, sizeof(struct mmc_command));
3822 + cmd.opcode = MMC_SEND_STATUS;
3824 + cmd.arg = mmc->card->rca << 16;
3826 + ERR_MSG("cmd13 mmc card is null");
3827 + cmd.arg = host->app_cmd_arg;
3829 + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
3831 + memset(&mrq, 0, sizeof(struct mmc_request));
3832 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3835 + err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
3838 + *status = cmd.resp[0];
3844 +static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
3850 + err = msdc_get_card_status(mmc, host, &status);
3851 + if (err) return err;
3853 + ERR_MSG("cmd<13> resp<0x%x>", status);
3854 + } while (R1_CURRENT_STATE(status) == 7);
3859 +/* failed when msdc_do_request */
3860 +static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
3862 + struct msdc_host *host = mmc_priv(mmc);
3863 + struct mmc_command *cmd;
3864 + struct mmc_data *data;
3865 + //u32 base = host->base;
3869 + data = mrq->cmd->data;
3871 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3874 + if (data->error == (unsigned int)(-EIO)) {
3875 + ret = msdc_tune_bread(mmc,mrq);
3878 + ret = msdc_check_busy(mmc, host);
3880 + ERR_MSG("XXX cmd13 wait program done failed");
3884 + /* Fix me: don't care card status? */
3885 + ret = msdc_tune_bwrite(mmc,mrq);
3892 +static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
3894 + struct msdc_host *host = mmc_priv(mmc);
3896 + //=== for sdio profile ===
3897 +#if 0 /* --- by chhung */
3898 + u32 old_H32, old_L32, new_H32, new_L32;
3899 + u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
3900 +#endif /* end of --- */
3903 + ERR_MSG("XXX host->mrq<0x%.8x>", (int)host->mrq);
3907 + if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
3908 + ERR_MSG("cmd<%d> card<%d> power<%d>", mrq->cmd->opcode, is_card_present(host), host->power_mode);
3909 + mrq->cmd->error = (unsigned int)-ENOMEDIUM;
3912 + mrq->done(mrq); // call done directly.
3914 + mrq->cmd->retries = 0; // please don't retry.
3915 + mmc_request_done(mmc, mrq);
3921 + /* start to process */
3922 + spin_lock(&host->lock);
3923 +#if 0 /* --- by chhung */
3924 + if (sdio_pro_enable) { //=== for sdio profile ===
3925 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3926 + GPT_GetCounter64(&old_L32, &old_H32);
3929 +#endif /* end of --- */
3933 + if (msdc_do_request(mmc,mrq)) {
3934 + if(host->hw->flags & MSDC_REMOVABLE && mrq->data && mrq->data->error) {
3935 + //msdc_tune_request(mmc,mrq);
3939 + /* ==== when request done, check if app_cmd ==== */
3940 + if (mrq->cmd->opcode == MMC_APP_CMD) {
3941 + host->app_cmd = 1;
3942 + host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
3944 + host->app_cmd = 0;
3945 + //host->app_cmd_arg = 0;
3950 +#if 0 /* --- by chhung */
3951 + //=== for sdio profile ===
3952 + if (sdio_pro_enable) {
3953 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3954 + GPT_GetCounter64(&new_L32, &new_H32);
3955 + ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
3957 + opcode = mrq->cmd->opcode;
3958 + if (mrq->cmd->data) {
3959 + sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
3960 + bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0 ;
3962 + bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
3965 + if (!mrq->cmd->error) {
3966 + msdc_performance(opcode, sizes, bRx, ticks);
3970 +#endif /* end of --- */
3971 + spin_unlock(&host->lock);
3973 + mmc_request_done(mmc, mrq);
3978 +/* called by ops.set_ios */
3979 +static void msdc_set_buswidth(struct msdc_host *host, u32 width)
3981 + u32 base = host->base;
3982 + u32 val = sdr_read32(SDC_CFG);
3984 + val &= ~SDC_CFG_BUSWIDTH;
3988 + case MMC_BUS_WIDTH_1:
3990 + val |= (MSDC_BUS_1BITS << 16);
3992 + case MMC_BUS_WIDTH_4:
3993 + val |= (MSDC_BUS_4BITS << 16);
3995 + case MMC_BUS_WIDTH_8:
3996 + val |= (MSDC_BUS_8BITS << 16);
4000 + sdr_write32(SDC_CFG, val);
4002 + N_MSG(CFG, "Bus Width = %d", width);
4006 +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
4008 + struct msdc_host *host = mmc_priv(mmc);
4009 + struct msdc_hw *hw=host->hw;
4010 + u32 base = host->base;
4013 +#ifdef MT6575_SD_DEBUG
4014 + static char *vdd[] = {
4015 + "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
4016 + "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
4017 + "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
4018 + "3.40v", "3.50v", "3.60v"
4020 + static char *power_mode[] = {
4023 + static char *bus_mode[] = {
4024 + "UNKNOWN", "OPENDRAIN", "PUSHPULL"
4026 + static char *timing[] = {
4027 + "LEGACY", "MMC_HS", "SD_HS"
4030 + printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
4031 + ios->clock / 1000, bus_mode[ios->bus_mode],
4032 + (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
4033 + power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
4036 + msdc_set_buswidth(host, ios->bus_width);
4038 + /* Power control ??? */
4039 + switch (ios->power_mode) {
4040 + case MMC_POWER_OFF:
4041 + case MMC_POWER_UP:
4042 + // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
4044 + case MMC_POWER_ON:
4045 + host->power_mode = MMC_POWER_ON;
4051 + /* Clock control */
4052 + if (host->mclk != ios->clock) {
4053 + if(ios->clock > 25000000) {
4054 + //if (!(host->hw->flags & MSDC_REMOVABLE)) {
4055 + INIT_MSG("SD data latch edge<%d>", hw->data_edge);
4056 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
4057 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
4058 + //} /* for tuning debug */
4059 + } else { /* default value */
4060 + sdr_write32(MSDC_IOCON, 0x00000000);
4061 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4062 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4063 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4064 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4065 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4067 + msdc_set_mclk(host, ddr, ios->clock);
4072 +static int msdc_ops_get_ro(struct mmc_host *mmc)
4074 + struct msdc_host *host = mmc_priv(mmc);
4075 + u32 base = host->base;
4076 + unsigned long flags;
4079 + if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
4080 + spin_lock_irqsave(&host->lock, flags);
4081 + ro = (sdr_read32(MSDC_PS) >> 31);
4082 + spin_unlock_irqrestore(&host->lock, flags);
4088 +static int msdc_ops_get_cd(struct mmc_host *mmc)
4090 + struct msdc_host *host = mmc_priv(mmc);
4091 + u32 base = host->base;
4092 + unsigned long flags;
4095 + /* for sdio, MSDC_REMOVABLE not set, always return 1 */
4096 + if (!(host->hw->flags & MSDC_REMOVABLE)) {
4097 + /* For sdio, read H/W always get<1>, but may timeout some times */
4099 + host->card_inserted = 1;
4102 + host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
4103 + INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
4104 + return host->card_inserted;
4108 + /* MSDC_CD_PIN_EN set for card */
4109 + if (host->hw->flags & MSDC_CD_PIN_EN) {
4110 + spin_lock_irqsave(&host->lock, flags);
4112 + present = host->card_inserted; /* why not read from H/W: Fix me*/
4115 + if (cd_active_low)
4116 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
4118 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 1 : 0;
4119 + host->card_inserted = present;
4121 + spin_unlock_irqrestore(&host->lock, flags);
4123 + present = 0; /* TODO? Check DAT3 pins for card detection */
4126 + INIT_MSG("ops_get_cd return<%d>", present);
4130 +/* ops.enable_sdio_irq */
4131 +static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
4133 + struct msdc_host *host = mmc_priv(mmc);
4134 + struct msdc_hw *hw = host->hw;
4135 + u32 base = host->base;
4138 + if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
4140 + hw->enable_sdio_eirq(); /* combo_sdio_enable_eirq */
4142 + hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
4145 + ERR_MSG("XXX "); /* so never enter here */
4146 + tmp = sdr_read32(SDC_CFG);
4147 + /* FIXME. Need to interrupt gap detection */
4149 + tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4151 + tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4153 + sdr_write32(SDC_CFG, tmp);
4157 +static struct mmc_host_ops mt_msdc_ops = {
4158 + .request = msdc_ops_request,
4159 + .set_ios = msdc_ops_set_ios,
4160 + .get_ro = msdc_ops_get_ro,
4161 + .get_cd = msdc_ops_get_cd,
4162 + .enable_sdio_irq = msdc_ops_enable_sdio_irq,
4165 +/*--------------------------------------------------------------------------*/
4166 +/* interrupt handler */
4167 +/*--------------------------------------------------------------------------*/
4168 +static irqreturn_t msdc_irq(int irq, void *dev_id)
4170 + struct msdc_host *host = (struct msdc_host *)dev_id;
4171 + struct mmc_data *data = host->data;
4172 + struct mmc_command *cmd = host->cmd;
4173 + u32 base = host->base;
4175 + u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
4176 + MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
4177 + MSDC_INT_ACMD19_DONE;
4178 + u32 datsts = MSDC_INT_DATCRCERR |MSDC_INT_DATTMO;
4180 + u32 intsts = sdr_read32(MSDC_INT);
4181 + u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
4183 + sdr_write32(MSDC_INT, intsts); /* clear interrupts */
4184 + /* MSG will cause fatal error */
4186 + /* card change interrupt */
4187 + if (intsts & MSDC_INT_CDSC){
4189 + return IRQ_HANDLED;
4190 + IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
4191 +#if 0 /* ---/+++ by chhung: fix slot mechanical bounce issue */
4192 + tasklet_hi_schedule(&host->card_tasklet);
4194 + schedule_delayed_work(&host->card_delaywork, HZ);
4196 + /* tuning when plug card ? */
4199 + /* sdio interrupt */
4200 + if (intsts & MSDC_INT_SDIOIRQ){
4201 + IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
4202 + //mmc_signal_sdio_irq(host->mmc);
4205 + /* transfer complete interrupt */
4206 + if (data != NULL) {
4207 + if (inten & MSDC_INT_XFER_COMPL) {
4208 + data->bytes_xfered = host->dma.xfersz;
4209 + complete(&host->xfer_done);
4212 + if (intsts & datsts) {
4213 + /* do basic reset, or stop command will sdc_busy */
4217 + atomic_set(&host->abort, 1); /* For PIO mode exit */
4219 + if (intsts & MSDC_INT_DATTMO){
4220 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
4221 + data->error = (unsigned int)-ETIMEDOUT;
4223 + else if (intsts & MSDC_INT_DATCRCERR){
4224 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
4225 + data->error = (unsigned int)-EIO;
4228 + //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
4229 + if (host->dma_xfer) {
4230 + complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
4231 + } /* PIO mode can't do complete, because not init */
4235 + /* command interrupts */
4236 + if ((cmd != NULL) && (intsts & cmdsts)) {
4237 + if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
4238 + (intsts & MSDC_INT_ACMD19_DONE)) {
4239 + u32 *rsp = &cmd->resp[0];
4241 + switch (host->cmd_rsp) {
4245 + *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
4246 + *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
4248 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
4249 + if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
4250 + *rsp = sdr_read32(SDC_ACMD_RESP);
4252 + *rsp = sdr_read32(SDC_RESP0);
4256 + } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
4257 + if(intsts & MSDC_INT_ACMDCRCERR){
4258 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR",cmd->opcode);
4261 + IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR",cmd->opcode);
4263 + cmd->error = (unsigned int)-EIO;
4264 + } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
4265 + if(intsts & MSDC_INT_ACMDTMO){
4266 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO",cmd->opcode);
4269 + IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO",cmd->opcode);
4271 + cmd->error = (unsigned int)-ETIMEDOUT;
4276 + complete(&host->cmd_done);
4279 + /* mmc irq interrupts */
4280 + if (intsts & MSDC_INT_MMCIRQ) {
4281 + printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
4284 +#ifdef MT6575_SD_DEBUG
4286 + msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
4287 + N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
4291 + int_reg->atocmdrdy,
4292 + int_reg->atocmdtmo,
4293 + int_reg->atocmdcrc,
4294 + int_reg->atocmd19done);
4295 + N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
4302 + N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
4304 + int_reg->xfercomp,
4305 + int_reg->dxferdone,
4308 + int_reg->dmaqempty);
4313 + return IRQ_HANDLED;
4316 +/*--------------------------------------------------------------------------*/
4317 +/* platform_driver members */
4318 +/*--------------------------------------------------------------------------*/
4319 +/* called by msdc_drv_probe/remove */
4320 +static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
4322 + struct msdc_hw *hw = host->hw;
4323 + u32 base = host->base;
4325 + /* for sdio, not set */
4326 + if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
4327 + /* Pull down card detection pin since it is not avaiable */
4329 + if (hw->config_gpio_pin)
4330 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4332 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4333 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4334 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4338 + N_MSG(CFG, "CD IRQ Eanable(%d)", enable);
4341 + if (hw->enable_cd_eirq) { /* not set, never enter */
4342 + hw->enable_cd_eirq();
4344 + /* card detection circuit relies on the core power so that the core power
4345 + * shouldn't be turned off. Here adds a reference count to keep
4346 + * the core power alive.
4348 + //msdc_vcore_on(host); //did in msdc_init_hw()
4350 + if (hw->config_gpio_pin) /* NULL */
4351 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
4353 + sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
4354 + sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
4355 + sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4356 + sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
4359 + if (hw->disable_cd_eirq) {
4360 + hw->disable_cd_eirq();
4362 + if (hw->config_gpio_pin) /* NULL */
4363 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4365 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4366 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4367 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4369 + /* Here decreases a reference count to core power since card
4370 + * detection circuit is shutdown.
4372 + //msdc_vcore_off(host);
4377 +/* called by msdc_drv_probe */
4378 +static void msdc_init_hw(struct msdc_host *host)
4380 + u32 base = host->base;
4381 + struct msdc_hw *hw = host->hw;
4383 +#ifdef MT6575_SD_DEBUG
4384 + msdc_reg[host->id] = (struct msdc_regs *)host->base;
4388 +#if 0 /* --- by chhung */
4389 + msdc_vcore_on(host);
4390 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
4391 + msdc_select_clksrc(host, hw->clk_src);
4392 + enable_clock(PERI_MSDC0_PDN + host->id, "SD");
4393 + msdc_vdd_on(host);
4394 +#endif /* end of --- */
4395 + /* Configure to MMC/SD mode */
4396 + sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
4402 + /* Disable card detection */
4403 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4405 + /* Disable and clear all interrupts */
4406 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4407 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4410 + /* reset tuning parameter */
4411 + sdr_write32(MSDC_PAD_CTL0, 0x00090000);
4412 + sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
4413 + sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
4414 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4415 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4416 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4417 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4418 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4419 + sdr_write32(MSDC_IOCON, 0x00000000);
4420 +#if 0 // use MT7620 default value: 0x403c004f
4421 + sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
4424 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
4425 + if (host->id == 1) {
4426 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
4427 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
4429 + /* internal clock: latch read data */
4430 + sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
4435 + /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
4436 + pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
4437 + set when kernel driver wants to use SDIO bus interrupt */
4438 + /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
4439 + sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
4441 + /* disable detect SDIO device interupt function */
4442 + sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
4444 + /* eneable SMT for glitch filter */
4445 + sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
4446 + sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
4447 + sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
4450 + /* set clk, cmd, dat pad driving */
4451 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
4452 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
4453 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
4454 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
4455 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
4456 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
4458 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
4459 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
4460 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
4461 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
4462 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
4463 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
4466 + /* set sampling edge */
4468 + /* write crc timeout detection */
4469 + sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
4471 + /* Configure to default data timeout */
4472 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
4474 + msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
4476 + N_MSG(FUC, "init hardware done!");
4479 +/* called by msdc_drv_remove */
4480 +static void msdc_deinit_hw(struct msdc_host *host)
4482 + u32 base = host->base;
4484 + /* Disable and clear all interrupts */
4485 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4486 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4488 + /* Disable card detection */
4489 + msdc_enable_cd_irq(host, 0);
4490 + // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
4493 +/* init gpd and bd list in msdc_drv_probe */
4494 +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
4496 + gpd_t *gpd = dma->gpd;
4497 + bd_t *bd = dma->bd;
4500 + /* we just support one gpd */
4501 + int bdlen = MAX_BD_PER_GPD;
4503 + /* init the 2 gpd */
4504 + memset(gpd, 0, sizeof(gpd_t) * 2);
4505 + //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */
4506 + //gpd->next = (dma->gpd_addr + 1); /* bug */
4507 + gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));
4510 + gpd->bdp = 1; /* hwo, cs, bd pointer */
4511 + //gpd->ptr = (void*)virt_to_phys(bd);
4512 + gpd->ptr = (void *)dma->bd_addr; /* physical address */
4514 + memset(bd, 0, sizeof(bd_t) * bdlen);
4515 + ptr = bd + bdlen - 1;
4516 + //ptr->eol = 1; /* 0 or 1 [Fix me]*/
4519 + while (ptr != bd) {
4521 + prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
4526 +static int msdc_drv_probe(struct platform_device *pdev)
4528 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4529 + __iomem void *base;
4530 + struct mmc_host *mmc;
4531 + struct resource *mem;
4532 + struct msdc_host *host;
4533 + struct msdc_hw *hw;
4536 + pdev->dev.platform_data = &msdc0_hw;
4538 + /* Allocate MMC host for this device */
4539 + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
4540 + if (!mmc) return -ENOMEM;
4542 + hw = (struct msdc_hw*)pdev->dev.platform_data;
4543 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4544 + irq = platform_get_irq(pdev, 0);
4546 + //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
4548 + base = devm_ioremap_resource(&pdev->dev, res);
4550 + return PTR_ERR(base);
4552 + /* Set host parameters to mmc */
4553 + mmc->ops = &mt_msdc_ops;
4554 + mmc->f_min = HOST_MIN_MCLK;
4555 + mmc->f_max = HOST_MAX_MCLK;
4556 + mmc->ocr_avail = MSDC_OCR_AVAIL;
4558 + /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
4559 + For sdio : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
4560 + if (hw->flags & MSDC_HIGHSPEED) {
4561 + mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
4563 + if (hw->data_pins == 4) { /* current data_pins are all 4*/
4564 + mmc->caps |= MMC_CAP_4_BIT_DATA;
4565 + } else if (hw->data_pins == 8) {
4566 + mmc->caps |= MMC_CAP_8_BIT_DATA;
4568 + if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
4569 + mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
4571 + cd_active_low = !of_property_read_bool(pdev->dev.of_node, "mediatek,cd-high");
4572 + mtk_sw_poll = of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll");
4575 + mmc->caps |= MMC_CAP_NEEDS_POLL;
4577 + /* MMC core transfer sizes tunable parameters */
4578 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
4579 + mmc->max_segs = MAX_HW_SGMTS;
4581 + mmc->max_hw_segs = MAX_HW_SGMTS;
4582 + mmc->max_phys_segs = MAX_PHY_SGMTS;
4584 + mmc->max_seg_size = MAX_SGMT_SZ;
4585 + mmc->max_blk_size = HOST_MAX_BLKSZ;
4586 + mmc->max_req_size = MAX_REQ_SZ;
4587 + mmc->max_blk_count = mmc->max_req_size;
4589 + host = mmc_priv(mmc);
4592 + host->id = pdev->id;
4595 + host->base = (unsigned long) base;
4596 + host->mclk = 0; /* mclk: the request clock of mmc sub-system */
4597 + host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
4598 + host->sclk = 0; /* sclk: the really clock after divition */
4599 + host->pm_state = PMSG_RESUME;
4600 + host->suspend = 0;
4601 + host->core_clkon = 0;
4602 + host->card_clkon = 0;
4603 + host->core_power = 0;
4604 + host->power_mode = MMC_POWER_OFF;
4605 +// host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
4606 + host->timeout_ns = 0;
4607 + host->timeout_clks = DEFAULT_DTOC * 65536;
4610 + //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
4612 + host->dma.used_gpd = 0;
4613 + host->dma.used_bd = 0;
4615 + /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
4616 + host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL);
4617 + host->dma.bd = dma_alloc_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), &host->dma.bd_addr, GFP_KERNEL);
4618 + BUG_ON((!host->dma.gpd) || (!host->dma.bd));
4619 + msdc_init_gpd_bd(host, &host->dma);
4621 + msdc_6575_host[pdev->id] = host;
4624 + tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
4626 + INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
4628 + spin_lock_init(&host->lock);
4629 + msdc_init_hw(host);
4631 + ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
4632 + if (ret) goto release;
4633 + // mt65xx_irq_unmask(irq); /* --- by chhung */
4635 + if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
4636 + if (hw->request_cd_eirq) { /* not set for MT6575 */
4637 + hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
4641 + if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
4642 + hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
4644 + if (hw->register_pm) {/* yes for sdio */
4646 + hw->register_pm(msdc_pm, (void*)host); /* combo_sdio_register_pm() */
4648 + if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
4649 + ERR_MSG("MSDC_SYS_SUSPEND and register_pm both set");
4651 + //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
4654 + platform_set_drvdata(pdev, mmc);
4656 + ret = mmc_add_host(mmc);
4657 + if (ret) goto free_irq;
4659 + /* Config card detection pin and enable interrupts */
4660 + if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
4661 + msdc_enable_cd_irq(host, 1);
4663 + msdc_enable_cd_irq(host, 0);
4669 + free_irq(irq, host);
4671 + platform_set_drvdata(pdev, NULL);
4672 + msdc_deinit_hw(host);
4675 + tasklet_kill(&host->card_tasklet);
4677 + cancel_delayed_work_sync(&host->card_delaywork);
4681 + release_mem_region(mem->start, mem->end - mem->start + 1);
4683 + mmc_free_host(mmc);
4688 +/* 4 device share one driver, using "drvdata" to show difference */
4689 +static int msdc_drv_remove(struct platform_device *pdev)
4691 + struct mmc_host *mmc;
4692 + struct msdc_host *host;
4693 + struct resource *mem;
4695 + mmc = platform_get_drvdata(pdev);
4698 + host = mmc_priv(mmc);
4701 + ERR_MSG("removed !!!");
4703 + platform_set_drvdata(pdev, NULL);
4704 + mmc_remove_host(host->mmc);
4705 + msdc_deinit_hw(host);
4708 + tasklet_kill(&host->card_tasklet);
4710 + cancel_delayed_work_sync(&host->card_delaywork);
4712 + free_irq(host->irq, host);
4714 + dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
4715 + dma_free_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), host->dma.bd, host->dma.bd_addr);
4717 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4720 + release_mem_region(mem->start, mem->end - mem->start + 1);
4722 + mmc_free_host(host->mmc);
4727 +/* Fix me: Power Flow */
4729 +static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
4732 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4733 + struct msdc_host *host = mmc_priv(mmc);
4735 + if (mmc && state.event == PM_EVENT_SUSPEND && (host->hw->flags & MSDC_SYS_SUSPEND)) { /* will set for card */
4736 + msdc_pm(state, (void*)host);
4742 +static int msdc_drv_resume(struct platform_device *pdev)
4745 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4746 + struct msdc_host *host = mmc_priv(mmc);
4747 + struct pm_message state;
4749 + state.event = PM_EVENT_RESUME;
4750 + if (mmc && (host->hw->flags & MSDC_SYS_SUSPEND)) {/* will set for card */
4751 + msdc_pm(state, (void*)host);
4754 + /* This mean WIFI not controller by PM */
4760 +static const struct of_device_id mt7620_sdhci_match[] = {
4761 + { .compatible = "ralink,mt7620-sdhci" },
4764 +MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
4766 +static struct platform_driver mt_msdc_driver = {
4767 + .probe = msdc_drv_probe,
4768 + .remove = msdc_drv_remove,
4770 + .suspend = msdc_drv_suspend,
4771 + .resume = msdc_drv_resume,
4775 + .owner = THIS_MODULE,
4776 + .of_match_table = mt7620_sdhci_match,
4780 +/*--------------------------------------------------------------------------*/
4781 +/* module init/exit */
4782 +/*--------------------------------------------------------------------------*/
4783 +static int __init mt_msdc_init(void)
4786 +/* +++ by chhung */
4789 +#if defined (CONFIG_MTD_ANY_RALINK)
4790 + extern int ra_check_flash_type(void);
4791 + if(ra_check_flash_type() == 2) { /* NAND */
4792 + printk("%s: !!!!! SDXC Module Initialize Fail !!!!!", __func__);
4796 + printk("MTK MSDC device init.\n");
4797 + mtk_sd_device.dev.platform_data = &msdc0_hw;
4798 +if (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7621AT) {
4799 +//#if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
4800 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<18);
4801 +//#if defined (CONFIG_RALINK_MT7620)
4802 + if (ralink_soc == MT762X_SOC_MT7620A)
4806 +//#elif defined (CONFIG_RALINK_MT7628)
4807 + /* TODO: maybe omitted when RAether already toggle AGPIO_CFG */
4808 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c));
4809 + reg |= 0x1e << 16;
4810 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c), reg);
4812 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<10);
4813 +#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
4814 + reg |= 0x3<<26 | 0x3<<28 | 0x3<<30;
4815 + msdc0_hw.data_pins = 8,
4819 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60), reg);
4820 + //platform_device_register(&mtk_sd_device);
4823 + ret = platform_driver_register(&mt_msdc_driver);
4825 + printk(KERN_ERR DRV_NAME ": Can't register driver");
4828 + printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
4830 +#if defined (MT6575_SD_DEBUG)
4831 + msdc_debug_proc_init();
4836 +static void __exit mt_msdc_exit(void)
4838 +// platform_device_unregister(&mtk_sd_device);
4839 + platform_driver_unregister(&mt_msdc_driver);
4842 +module_init(mt_msdc_init);
4843 +module_exit(mt_msdc_exit);
4844 +MODULE_LICENSE("GPL");
4845 +MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
4846 +MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
4848 +EXPORT_SYMBOL(msdc_6575_host);