1 --- a/arch/mips/pci/pci-mt7621.c
2 +++ b/arch/mips/pci/pci-mt7621.c
4 #include <linux/version.h>
7 +#include <asm/mips-cm.h>
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/delay.h>
11 @@ -553,6 +554,23 @@ set_phy_for_ssc(void)
15 +void setup_cm_memory_region(struct resource *mem_resource)
17 + resource_size_t mask;
18 + if (mips_cm_numiocu()) {
19 + /* FIXME: hardware doesn't accept mask values with 1s after
20 + 0s (e.g. 0xffef), so it would be great to warn if that's
22 + mask = ~(mem_resource->end - mem_resource->start);
24 + write_gcr_reg1_base(mem_resource->start);
25 + write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
26 + printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
27 + read_gcr_reg1_base(),
28 + read_gcr_reg1_mask());
32 static int mt7621_pci_probe(struct platform_device *pdev)
34 unsigned long val = 0;
35 @@ -780,6 +798,7 @@ pcie(2/1/0) link status pcie2_num pcie1_
38 pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
39 + setup_cm_memory_region(mt7621_controller.mem_resource);
40 register_pci_controller(&mt7621_controller);