projects / openwrt / staging / chunkeey.git / blob
? search:


064298af529ef555ce6a2ac67eb7005f5e76005f
[openwrt/staging/chunkeey.git] / target / linux / ramips / patches-4.3 / 0502-net-next-mediatek-add-switch-driver-for-rt3050.patch
1 From 2c39ddc83452c34fedc86261ed1f96d7537adfd1 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 14 Dec 2015 21:28:10 +0100
4 Subject: [PATCH 502/513] net-next: mediatek: add switch driver for rt3050
5
6 This driver is very basic and only provides basic init and irq support.
7 Switchdev support for this device will follow.
8
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 ---
11 drivers/net/ethernet/mediatek/esw_rt3050.c | 640 ++++++++++++++++++++++++++++
12 drivers/net/ethernet/mediatek/esw_rt3050.h | 29 ++
13 2 files changed, 669 insertions(+)
14 create mode 100644 drivers/net/ethernet/mediatek/esw_rt3050.c
15 create mode 100644 drivers/net/ethernet/mediatek/esw_rt3050.h
16
17 diff --git a/drivers/net/ethernet/mediatek/esw_rt3050.c b/drivers/net/ethernet/mediatek/esw_rt3050.c
18 new file mode 100644
19 index 0000000..f07f4a5
20 --- /dev/null
21 +++ b/drivers/net/ethernet/mediatek/esw_rt3050.c
22 @@ -0,0 +1,640 @@
23 +/* This program is free software; you can redistribute it and/or modify
24 + * it under the terms of the GNU General Public License as published by
25 + * the Free Software Foundation; version 2 of the License
26 + *
27 + * This program is distributed in the hope that it will be useful,
28 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 + * GNU General Public License for more details.
31 + *
32 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
33 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
34 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
35 + */
36 +
37 +#include <linux/module.h>
38 +#include <linux/kernel.h>
39 +#include <linux/types.h>
40 +#include <linux/dma-mapping.h>
41 +#include <linux/init.h>
42 +#include <linux/skbuff.h>
43 +#include <linux/etherdevice.h>
44 +#include <linux/ethtool.h>
45 +#include <linux/platform_device.h>
46 +#include <linux/of_device.h>
47 +#include <linux/clk.h>
48 +#include <linux/of_net.h>
49 +#include <linux/of_mdio.h>
50 +
51 +#include <asm/mach-ralink/ralink_regs.h>
52 +
53 +#include "mtk_eth_soc.h"
54 +
55 +#include <linux/ioport.h>
56 +#include <linux/mii.h>
57 +
58 +#include <ralink_regs.h>
59 +
60 +/* HW limitations for this switch:
61 + * - No large frame support (PKT_MAX_LEN at most 1536)
62 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
63 + * though this might be possible using the undocumented PPE.
64 + */
65 +
66 +#define RT305X_ESW_REG_ISR 0x00
67 +#define RT305X_ESW_REG_IMR 0x04
68 +#define RT305X_ESW_REG_FCT0 0x08
69 +#define RT305X_ESW_REG_PFC1 0x14
70 +#define RT305X_ESW_REG_ATS 0x24
71 +#define RT305X_ESW_REG_ATS0 0x28
72 +#define RT305X_ESW_REG_ATS1 0x2c
73 +#define RT305X_ESW_REG_ATS2 0x30
74 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
75 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
76 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
77 +#define RT305X_ESW_REG_POA 0x80
78 +#define RT305X_ESW_REG_FPA 0x84
79 +#define RT305X_ESW_REG_SOCPC 0x8c
80 +#define RT305X_ESW_REG_POC0 0x90
81 +#define RT305X_ESW_REG_POC1 0x94
82 +#define RT305X_ESW_REG_POC2 0x98
83 +#define RT305X_ESW_REG_SGC 0x9c
84 +#define RT305X_ESW_REG_STRT 0xa0
85 +#define RT305X_ESW_REG_PCR0 0xc0
86 +#define RT305X_ESW_REG_PCR1 0xc4
87 +#define RT305X_ESW_REG_FPA2 0xc8
88 +#define RT305X_ESW_REG_FCT2 0xcc
89 +#define RT305X_ESW_REG_SGC2 0xe4
90 +#define RT305X_ESW_REG_P0LED 0xa4
91 +#define RT305X_ESW_REG_P1LED 0xa8
92 +#define RT305X_ESW_REG_P2LED 0xac
93 +#define RT305X_ESW_REG_P3LED 0xb0
94 +#define RT305X_ESW_REG_P4LED 0xb4
95 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
96 +#define RT305X_ESW_REG_P1PC 0xec
97 +#define RT305X_ESW_REG_P2PC 0xf0
98 +#define RT305X_ESW_REG_P3PC 0xf4
99 +#define RT305X_ESW_REG_P4PC 0xf8
100 +#define RT305X_ESW_REG_P5PC 0xfc
101 +
102 +#define RT305X_ESW_LED_LINK 0
103 +#define RT305X_ESW_LED_100M 1
104 +#define RT305X_ESW_LED_DUPLEX 2
105 +#define RT305X_ESW_LED_ACTIVITY 3
106 +#define RT305X_ESW_LED_COLLISION 4
107 +#define RT305X_ESW_LED_LINKACT 5
108 +#define RT305X_ESW_LED_DUPLCOLL 6
109 +#define RT305X_ESW_LED_10MACT 7
110 +#define RT305X_ESW_LED_100MACT 8
111 +/* Additional led states not in datasheet: */
112 +#define RT305X_ESW_LED_BLINK 10
113 +#define RT305X_ESW_LED_ON 12
114 +
115 +#define RT305X_ESW_LINK_S 25
116 +#define RT305X_ESW_DUPLEX_S 9
117 +#define RT305X_ESW_SPD_S 0
118 +
119 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
120 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
121 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
122 +
123 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
124 +
125 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
126 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
127 +
128 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
129 +#define RT305X_ESW_PVIDC_PVID_S 12
130 +
131 +#define RT305X_ESW_VLANI_VID_M 0xfff
132 +#define RT305X_ESW_VLANI_VID_S 12
133 +
134 +#define RT305X_ESW_VMSC_MSC_M 0xff
135 +#define RT305X_ESW_VMSC_MSC_S 8
136 +
137 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
138 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
139 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
140 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
141 +
142 +#define RT305X_ESW_POC0_EN_BP_S 0
143 +#define RT305X_ESW_POC0_EN_FC_S 8
144 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
145 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
146 +#define RT305X_ESW_POC0_DIS_PORT_S 23
147 +
148 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
149 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
150 +#define RT305X_ESW_POC2_ENAGING_S 8
151 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
152 +
153 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
154 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
155 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
156 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
157 +
158 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
159 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
160 +#define RT305X_ESW_PFC1_EN_TOS_S 24
161 +
162 +#define RT305X_ESW_VLAN_NONE 0xfff
163 +
164 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
165 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
166 +
167 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
168 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
169 +
170 +#define RT305X_ESW_POA_LINK_MASK 0x1f
171 +#define RT305X_ESW_POA_LINK_SHIFT 25
172 +
173 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
174 +#define RT305X_ESW_PORT0 0
175 +#define RT305X_ESW_PORT1 1
176 +#define RT305X_ESW_PORT2 2
177 +#define RT305X_ESW_PORT3 3
178 +#define RT305X_ESW_PORT4 4
179 +#define RT305X_ESW_PORT5 5
180 +#define RT305X_ESW_PORT6 6
181 +
182 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
183 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
184 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
185 +
186 +#define RT305X_ESW_PORTS_INTERNAL \
187 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
188 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
189 + BIT(RT305X_ESW_PORT4))
190 +
191 +#define RT305X_ESW_PORTS_NOCPU \
192 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
193 +
194 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
195 +
196 +#define RT305X_ESW_PORTS_ALL \
197 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
198 +
199 +#define RT305X_ESW_NUM_PORTS 7
200 +#define RT305X_ESW_NUM_LEDS 5
201 +
202 +#define RT5350_EWS_REG_LED_POLARITY 0x168
203 +#define RT5350_RESET_EPHY BIT(24)
204 +
205 +struct esw_port {
206 + bool disable;
207 + u8 led;
208 +};
209 +
210 +struct rt305x_esw {
211 + struct device *dev;
212 + void __iomem *base;
213 + int irq;
214 +
215 + /* Protects against concurrent register r/w operations. */
216 + spinlock_t reg_rw_lock;
217 +
218 + unsigned char port_map;
219 + unsigned int reg_led_polarity;
220 +
221 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
222 +
223 +};
224 +
225 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
226 +{
227 + __raw_writel(val, esw->base + reg);
228 +}
229 +
230 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
231 +{
232 + return __raw_readl(esw->base + reg);
233 +}
234 +
235 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
236 + unsigned long mask, unsigned long val)
237 +{
238 + unsigned long t;
239 +
240 + t = __raw_readl(esw->base + reg) & ~mask;
241 + __raw_writel(t | val, esw->base + reg);
242 +}
243 +
244 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
245 + unsigned long mask, unsigned long val)
246 +{
247 + unsigned long flags;
248 +
249 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
250 + esw_rmw_raw(esw, reg, mask, val);
251 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
252 +}
253 +
254 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
255 + u32 phy_register, u32 write_data)
256 +{
257 + unsigned long t_start = jiffies;
258 + int ret = 0;
259 +
260 + while (1) {
261 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
262 + RT305X_ESW_PCR1_WT_DONE))
263 + break;
264 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
265 + ret = 1;
266 + goto out;
267 + }
268 + }
269 +
270 + write_data &= 0xffff;
271 + esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
272 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
273 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
274 + RT305X_ESW_REG_PCR0);
275 +
276 + t_start = jiffies;
277 + while (1) {
278 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
279 + RT305X_ESW_PCR1_WT_DONE)
280 + break;
281 +
282 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
283 + ret = 1;
284 + break;
285 + }
286 + }
287 +out:
288 + if (ret)
289 + dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
290 + return ret;
291 +}
292 +
293 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
294 +{
295 + unsigned reg;
296 +
297 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
298 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
299 + RT305X_ESW_POC0_DIS_PORT_M;
300 +}
301 +
302 +static void esw_hw_init(struct rt305x_esw *esw)
303 +{
304 + int i;
305 + u8 port_disable = 0;
306 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
307 +
308 + /* vodoo from original driver */
309 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
310 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
311 + /* Port priority 1 for all ports, vlan enabled. */
312 + esw_w32(esw, 0x00005555 |
313 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
314 + RT305X_ESW_REG_PFC1);
315 +
316 + /* Enable Back Pressure, and Flow Control */
317 + esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
318 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
319 + RT305X_ESW_REG_POC0);
320 +
321 + /* Enable Aging, and VLAN TAG removal */
322 + esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
323 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
324 + RT305X_ESW_REG_POC2);
325 +
326 + esw_w32(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
327 +
328 + /* 300s aging timer, max packet len 1536, broadcast storm prevention
329 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
330 + * pressure jam, GMII disable was_transmit, back pressure disabled,
331 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
332 + * ports.
333 + */
334 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
335 +
336 + /* Setup SoC Port control register */
337 + esw_w32(esw,
338 + (RT305X_ESW_SOCPC_CRC_PADDING |
339 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
340 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
341 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
342 + RT305X_ESW_REG_SOCPC);
343 +
344 + /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
345 + * turbo mii off, rgmi 3.3v off
346 + * port5: disabled
347 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
348 + */
349 + esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
350 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
351 +
352 + /* Force Link/Activity on ports */
353 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
354 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
355 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
356 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
357 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
358 +
359 + /* Copy disabled port configuration from bootloader setup */
360 + port_disable = esw_get_port_disable(esw);
361 + for (i = 0; i < 6; i++)
362 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
363 +
364 + if (ralink_soc == RT305X_SOC_RT3352) {
365 + /* reset EPHY */
366 + fe_reset(RT5350_RESET_EPHY);
367 +
368 + rt305x_mii_write(esw, 0, 31, 0x8000);
369 + for (i = 0; i < 5; i++) {
370 + if (esw->ports[i].disable) {
371 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
372 + } else {
373 + rt305x_mii_write(esw, i, MII_BMCR,
374 + BMCR_FULLDPLX |
375 + BMCR_ANENABLE |
376 + BMCR_SPEED100);
377 + }
378 + /* TX10 waveform coefficient LSB=0 disable PHY */
379 + rt305x_mii_write(esw, i, 26, 0x1601);
380 + /* TX100/TX10 AD/DA current bias */
381 + rt305x_mii_write(esw, i, 29, 0x7016);
382 + /* TX100 slew rate control */
383 + rt305x_mii_write(esw, i, 30, 0x0038);
384 + }
385 +
386 + /* select global register */
387 + rt305x_mii_write(esw, 0, 31, 0x0);
388 + /* enlarge agcsel threshold 3 and threshold 2 */
389 + rt305x_mii_write(esw, 0, 1, 0x4a40);
390 + /* enlarge agcsel threshold 5 and threshold 4 */
391 + rt305x_mii_write(esw, 0, 2, 0x6254);
392 + /* enlarge agcsel threshold */
393 + rt305x_mii_write(esw, 0, 3, 0xa17f);
394 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
395 + /* longer TP_IDL tail length */
396 + rt305x_mii_write(esw, 0, 14, 0x65);
397 + /* increased squelch pulse count threshold. */
398 + rt305x_mii_write(esw, 0, 16, 0x0684);
399 + /* set TX10 signal amplitude threshold to minimum */
400 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
401 + /* set squelch amplitude to higher threshold */
402 + rt305x_mii_write(esw, 0, 18, 0x40ba);
403 + /* tune TP_IDL tail and head waveform, enable power
404 + * down slew rate control
405 + */
406 + rt305x_mii_write(esw, 0, 22, 0x253f);
407 + /* set PLL/Receive bias current are calibrated */
408 + rt305x_mii_write(esw, 0, 27, 0x2fda);
409 + /* change PLL/Receive bias current to internal(RT3350) */
410 + rt305x_mii_write(esw, 0, 28, 0xc410);
411 + /* change PLL bias current to internal(RT3052_MP3) */
412 + rt305x_mii_write(esw, 0, 29, 0x598b);
413 + /* select local register */
414 + rt305x_mii_write(esw, 0, 31, 0x8000);
415 + } else if (ralink_soc == RT305X_SOC_RT5350) {
416 + /* reset EPHY */
417 + fe_reset(RT5350_RESET_EPHY);
418 +
419 + /* set the led polarity */
420 + esw_w32(esw, esw->reg_led_polarity & 0x1F,
421 + RT5350_EWS_REG_LED_POLARITY);
422 +
423 + /* local registers */
424 + rt305x_mii_write(esw, 0, 31, 0x8000);
425 + for (i = 0; i < 5; i++) {
426 + if (esw->ports[i].disable) {
427 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
428 + } else {
429 + rt305x_mii_write(esw, i, MII_BMCR,
430 + BMCR_FULLDPLX |
431 + BMCR_ANENABLE |
432 + BMCR_SPEED100);
433 + }
434 + /* TX10 waveform coefficient LSB=0 disable PHY */
435 + rt305x_mii_write(esw, i, 26, 0x1601);
436 + /* TX100/TX10 AD/DA current bias */
437 + rt305x_mii_write(esw, i, 29, 0x7015);
438 + /* TX100 slew rate control */
439 + rt305x_mii_write(esw, i, 30, 0x0038);
440 + }
441 +
442 + /* global registers */
443 + rt305x_mii_write(esw, 0, 31, 0x0);
444 + /* enlarge agcsel threshold 3 and threshold 2 */
445 + rt305x_mii_write(esw, 0, 1, 0x4a40);
446 + /* enlarge agcsel threshold 5 and threshold 4 */
447 + rt305x_mii_write(esw, 0, 2, 0x6254);
448 + /* enlarge agcsel threshold 6 */
449 + rt305x_mii_write(esw, 0, 3, 0xa17f);
450 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
451 + /* longer TP_IDL tail length */
452 + rt305x_mii_write(esw, 0, 14, 0x65);
453 + /* increased squelch pulse count threshold. */
454 + rt305x_mii_write(esw, 0, 16, 0x0684);
455 + /* set TX10 signal amplitude threshold to minimum */
456 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
457 + /* set squelch amplitude to higher threshold */
458 + rt305x_mii_write(esw, 0, 18, 0x40ba);
459 + /* tune TP_IDL tail and head waveform, enable power
460 + * down slew rate control
461 + */
462 + rt305x_mii_write(esw, 0, 22, 0x253f);
463 + /* set PLL/Receive bias current are calibrated */
464 + rt305x_mii_write(esw, 0, 27, 0x2fda);
465 + /* change PLL/Receive bias current to internal(RT3350) */
466 + rt305x_mii_write(esw, 0, 28, 0xc410);
467 + /* change PLL bias current to internal(RT3052_MP3) */
468 + rt305x_mii_write(esw, 0, 29, 0x598b);
469 + /* select local register */
470 + rt305x_mii_write(esw, 0, 31, 0x8000);
471 + } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
472 + int i;
473 +
474 + /* reset EPHY */
475 + fe_reset(RT5350_RESET_EPHY);
476 +
477 + rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
478 + rt305x_mii_write(esw, 0, 26, 0x0020);
479 +
480 + for (i = 0; i < 5; i++) {
481 + rt305x_mii_write(esw, i, 31, 0x8000);
482 + rt305x_mii_write(esw, i, 0, 0x3100);
483 + rt305x_mii_write(esw, i, 30, 0xa000);
484 + rt305x_mii_write(esw, i, 31, 0xa000);
485 + rt305x_mii_write(esw, i, 16, 0x0606);
486 + rt305x_mii_write(esw, i, 23, 0x0f0e);
487 + rt305x_mii_write(esw, i, 24, 0x1610);
488 + rt305x_mii_write(esw, i, 30, 0x1f15);
489 + rt305x_mii_write(esw, i, 28, 0x6111);
490 + rt305x_mii_write(esw, i, 31, 0x2000);
491 + rt305x_mii_write(esw, i, 26, 0x0000);
492 + }
493 +
494 + /* 100Base AOI setting */
495 + rt305x_mii_write(esw, 0, 31, 0x5000);
496 + rt305x_mii_write(esw, 0, 19, 0x004a);
497 + rt305x_mii_write(esw, 0, 20, 0x015a);
498 + rt305x_mii_write(esw, 0, 21, 0x00ee);
499 + rt305x_mii_write(esw, 0, 22, 0x0033);
500 + rt305x_mii_write(esw, 0, 23, 0x020a);
501 + rt305x_mii_write(esw, 0, 24, 0x0000);
502 + rt305x_mii_write(esw, 0, 25, 0x024a);
503 + rt305x_mii_write(esw, 0, 26, 0x035a);
504 + rt305x_mii_write(esw, 0, 27, 0x02ee);
505 + rt305x_mii_write(esw, 0, 28, 0x0233);
506 + rt305x_mii_write(esw, 0, 29, 0x000a);
507 + rt305x_mii_write(esw, 0, 30, 0x0000);
508 + } else {
509 + rt305x_mii_write(esw, 0, 31, 0x8000);
510 + for (i = 0; i < 5; i++) {
511 + if (esw->ports[i].disable) {
512 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
513 + } else {
514 + rt305x_mii_write(esw, i, MII_BMCR,
515 + BMCR_FULLDPLX |
516 + BMCR_ANENABLE |
517 + BMCR_SPEED100);
518 + }
519 + /* TX10 waveform coefficient */
520 + rt305x_mii_write(esw, i, 26, 0x1601);
521 + /* TX100/TX10 AD/DA current bias */
522 + rt305x_mii_write(esw, i, 29, 0x7058);
523 + /* TX100 slew rate control */
524 + rt305x_mii_write(esw, i, 30, 0x0018);
525 + }
526 +
527 + /* PHY IOT */
528 + /* select global register */
529 + rt305x_mii_write(esw, 0, 31, 0x0);
530 + /* tune TP_IDL tail and head waveform */
531 + rt305x_mii_write(esw, 0, 22, 0x052f);
532 + /* set TX10 signal amplitude threshold to minimum */
533 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
534 + /* set squelch amplitude to higher threshold */
535 + rt305x_mii_write(esw, 0, 18, 0x40ba);
536 + /* longer TP_IDL tail length */
537 + rt305x_mii_write(esw, 0, 14, 0x65);
538 + /* select local register */
539 + rt305x_mii_write(esw, 0, 31, 0x8000);
540 + }
541 +
542 + if (esw->port_map)
543 + port_map = esw->port_map;
544 + else
545 + port_map = RT305X_ESW_PMAP_LLLLLL;
546 +
547 + /* Unused HW feature, but still nice to be consistent here...
548 + * This is also exported to userspace ('lan' attribute) so it's
549 + * conveniently usable to decide which ports go into the wan vlan by
550 + * default.
551 + */
552 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
553 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
554 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
555 +
556 + /* make the switch leds blink */
557 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
558 + esw->ports[i].led = 0x05;
559 +
560 + /* Only unmask the port change interrupt */
561 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
562 +}
563 +
564 +static irqreturn_t esw_interrupt(int irq, void *_esw)
565 +{
566 + struct rt305x_esw *esw = (struct rt305x_esw *)_esw;
567 + u32 status;
568 +
569 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
570 + if (status & RT305X_ESW_PORT_ST_CHG) {
571 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
572 +
573 + link >>= RT305X_ESW_POA_LINK_SHIFT;
574 + link &= RT305X_ESW_POA_LINK_MASK;
575 + dev_info(esw->dev, "link changed 0x%02X\n", link);
576 + }
577 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
578 +
579 + return IRQ_HANDLED;
580 +}
581 +
582 +static int esw_probe(struct platform_device *pdev)
583 +{
584 + struct resource *res = platform_get_resource(p, IORESOURCE_MEM, 0);
585 + struct device_node *np = pdev->dev.of_node;
586 + const __be32 *port_map, *reg_init;
587 + struct rt305x_esw *esw;
588 + struct resource *irq;
589 + int ret;
590 +
591 + esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
592 + if (!esw)
593 + return -ENOMEM;
594 +
595 + esw->dev = &pdev->dev;
596 + esw->irq = irq->start;
597 + esw->base = devm_ioremap_resource(&pdev->dev, res);
598 + if (!esw->base)
599 + return -EADDRNOTAVAIL;
600 +
601 + port_map = of_get_property(np, "mediatek,portmap", NULL);
602 + if (port_map)
603 + esw->port_map = be32_to_cpu(*port_map);
604 +
605 + reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
606 + if (reg_init)
607 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
608 +
609 + platform_set_drvdata(pdev, esw);
610 +
611 + spin_lock_init(&esw->reg_rw_lock);
612 +
613 + esw_hw_init(esw);
614 +
615 + ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
616 + esw);
617 +
618 + if (!ret) {
619 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
620 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
621 + }
622 +
623 + return ret;
624 +}
625 +
626 +static int esw_remove(struct platform_device *pdev)
627 +{
628 + struct rt305x_esw *esw = platform_get_drvdata(pdev);
629 +
630 + if (esw) {
631 + esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
632 + platform_set_drvdata(pdev, NULL);
633 + }
634 +
635 + return 0;
636 +}
637 +
638 +static const struct of_device_id ralink_esw_match[] = {
639 + { .compatible = "ralink,rt3050-esw" },
640 + {},
641 +};
642 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
643 +
644 +static struct platform_driver esw_driver = {
645 + .probe = esw_probe,
646 + .remove = esw_remove,
647 + .driver = {
648 + .name = "rt3050-esw",
649 + .owner = THIS_MODULE,
650 + .of_match_table = ralink_esw_match,
651 + },
652 +};
653 +
654 +int __init mtk_switch_init(void)
655 +{
656 + return platform_driver_register(&esw_driver);
657 +}
658 +
659 +void mtk_switch_exit(void)
660 +{
661 + platform_driver_unregister(&esw_driver);
662 +}
663 diff --git a/drivers/net/ethernet/mediatek/esw_rt3050.h b/drivers/net/ethernet/mediatek/esw_rt3050.h
664 new file mode 100644
665 index 0000000..455107a
666 --- /dev/null
667 +++ b/drivers/net/ethernet/mediatek/esw_rt3050.h
668 @@ -0,0 +1,29 @@
669 +/* This program is free software; you can redistribute it and/or modify
670 + * it under the terms of the GNU General Public License as published by
671 + * the Free Software Foundation; version 2 of the License
672 + *
673 + * This program is distributed in the hope that it will be useful,
674 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
675 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
676 + * GNU General Public License for more details.
677 + *
678 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
679 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
680 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
681 + */
682 +
683 +#ifndef _RALINK_ESW_RT3052_H__
684 +#define _RALINK_ESW_RT3052_H__
685 +
686 +#ifdef CONFIG_NET_MEDIATEK_ESW_RT3052
687 +
688 +int __init mtk_switch_init(void);
689 +void mtk_switch_exit(void);
690 +
691 +#else
692 +
693 +static inline int __init mtk_switch_init(void) { return 0; }
694 +static inline void mtk_switch_exit(void) { }
695 +
696 +#endif
697 +#endif
698 --
699 1.7.10.4
700
Staging tree of Christian Lamparter