target/linux/ramips/patches-4.3/0507-net-next-mediatek-add-support-for-rt3883.patch

   1 From 5ad283c69029a519681ed453e7f7ddf250c10559 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 18 Nov 2015 03:51:24 +0100
   4 Subject: [PATCH 507/513] net-next: mediatek: add support for rt3883
   5
   6 Add support for rt3883 and its smaller version rt3662. They both have a single
   7 gBit port that will normally be attached to an external phy of switch.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  11 Signed-off-by: Michael Lee <igvtee@gmail.com>
  12 ---
  13  drivers/net/ethernet/mediatek/soc_rt3883.c |   75 ++++++++++++++++++++++++++++
  14  1 file changed, 75 insertions(+)
  15  create mode 100644 drivers/net/ethernet/mediatek/soc_rt3883.c
  16
  17 diff --git a/drivers/net/ethernet/mediatek/soc_rt3883.c b/drivers/net/ethernet/mediatek/soc_rt3883.c
  18 new file mode 100644
  19 index 0000000..7f34d4d
  20 --- /dev/null
  21 +++ b/drivers/net/ethernet/mediatek/soc_rt3883.c
  22 @@ -0,0 +1,75 @@
  23 +/*   This program is free software; you can redistribute it and/or modify
  24 + *   it under the terms of the GNU General Public License as published by
  25 + *   the Free Software Foundation; version 2 of the License
  26 + *
  27 + *   This program is distributed in the hope that it will be useful,
  28 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  29 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30 + *   GNU General Public License for more details.
  31 + *
  32 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  33 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
  34 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  35 + */
  36 +
  37 +#include <linux/module.h>
  38 +
  39 +#include <asm/mach-ralink/ralink_regs.h>
  40 +
  41 +#include "mtk_eth_soc.h"
  42 +#include "mdio_rt2880.h"
  43 +
  44 +#define RT3883_RSTCTRL_FE              BIT(21)
  45 +
  46 +static void rt3883_fe_reset(void)
  47 +{
  48 +       fe_reset(RT3883_RSTCTRL_FE);
  49 +}
  50 +
  51 +static int rt3883_fwd_config(struct fe_priv *priv)
  52 +{
  53 +       int ret;
  54 +
  55 +       ret = fe_set_clock_cycle(priv);
  56 +       if (ret)
  57 +               return ret;
  58 +
  59 +       fe_fwd_config(priv);
  60 +       fe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG);
  61 +       fe_csum_config(priv);
  62 +
  63 +       return ret;
  64 +}
  65 +
  66 +static void rt3883_init_data(struct fe_soc_data *data,
  67 +                            struct net_device *netdev)
  68 +{
  69 +       struct fe_priv *priv = netdev_priv(netdev);
  70 +
  71 +       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
  72 +               FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
  73 +       netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
  74 +               NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
  75 +}
  76 +
  77 +static struct fe_soc_data rt3883_data = {
  78 +       .init_data = rt3883_init_data,
  79 +       .reset_fe = rt3883_fe_reset,
  80 +       .fwd_config = rt3883_fwd_config,
  81 +       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
  82 +       .rx_int = FE_RX_DONE_INT,
  83 +       .tx_int = FE_TX_DONE_INT,
  84 +       .status_int = FE_CNT_GDM_AF,
  85 +       .checksum_bit = RX_DMA_L4VALID,
  86 +       .mdio_read = rt2880_mdio_read,
  87 +       .mdio_write = rt2880_mdio_write,
  88 +       .mdio_adjust_link = rt2880_mdio_link_adjust,
  89 +       .port_init = rt2880_port_init,
  90 +};
  91 +
  92 +const struct of_device_id of_fe_match[] = {
  93 +       { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
  94 +       {},
  95 +};
  96 +
  97 +MODULE_DEVICE_TABLE(of, of_fe_match);
  98 --
  99 1.7.10.4
 100