ralink: add reworked ethernet driver
[openwrt/staging/chunkeey.git] / target / linux / ramips / patches-4.3 / 0508-net-next-mediatek-add-support-for-mt7620.patch
1 From 1efca7b539a91c49ab1d6484ec3a69c48fa6062b Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 14 Dec 2015 21:25:35 +0100
4 Subject: [PATCH 508/513] net-next: mediatek: add support for mt7620
5
6 Add support for SoCs from the mt7620 family. This include mt7620 and mt7621.
7 These all have one dedicated external gbit port and a builtin 5 port 100mbit
8 switch. Additionally one of the 5 switch ports can be changed to become an
9 additional gbit port that we can attach a phy to. This patch includes
10 rudimentary code to power up the switch. There are a lot of magic values
11 that get written to the switch and the internal phys. These values come
12 straight from the SDK driver.
13
14 Signed-off-by: John Crispin <blogic@openwrt.org>
15 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
16 Signed-off-by: Michael Lee <igvtee@gmail.com>
17 ---
18 drivers/net/ethernet/mediatek/mdio_mt7620.c | 156 +++++++++++++
19 drivers/net/ethernet/mediatek/soc_mt7620.c | 334 +++++++++++++++++++++++++++
20 2 files changed, 490 insertions(+)
21 create mode 100644 drivers/net/ethernet/mediatek/mdio_mt7620.c
22 create mode 100644 drivers/net/ethernet/mediatek/soc_mt7620.c
23
24 diff --git a/drivers/net/ethernet/mediatek/mdio_mt7620.c b/drivers/net/ethernet/mediatek/mdio_mt7620.c
25 new file mode 100644
26 index 0000000..89c6c30
27 --- /dev/null
28 +++ b/drivers/net/ethernet/mediatek/mdio_mt7620.c
29 @@ -0,0 +1,156 @@
30 +/* This program is free software; you can redistribute it and/or modify
31 + * it under the terms of the GNU General Public License as published by
32 + * the Free Software Foundation; version 2 of the License
33 + *
34 + * This program is distributed in the hope that it will be useful,
35 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 + * GNU General Public License for more details.
38 + *
39 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
40 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
41 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
42 + */
43 +
44 +#include <linux/module.h>
45 +#include <linux/kernel.h>
46 +#include <linux/types.h>
47 +
48 +#include "mtk_eth_soc.h"
49 +#include "gsw_mt7620.h"
50 +#include "mdio.h"
51 +
52 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
53 +{
54 + unsigned long t_start = jiffies;
55 +
56 + while (1) {
57 + if (!(mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
58 + return 0;
59 + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT))
60 + break;
61 + }
62 +
63 + dev_err(gsw->dev, "mdio: MDIO timeout\n");
64 + return -1;
65 +}
66 +
67 +u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
68 + u32 phy_register, u32 write_data)
69 +{
70 + if (mt7620_mii_busy_wait(gsw))
71 + return -1;
72 +
73 + write_data &= 0xffff;
74 +
75 + mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
76 + (phy_register << GSW_MDIO_REG_SHIFT) |
77 + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
78 + MT7620A_GSW_REG_PIAC);
79 +
80 + if (mt7620_mii_busy_wait(gsw))
81 + return -1;
82 +
83 + return 0;
84 +}
85 +
86 +u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
87 +{
88 + u32 d;
89 +
90 + if (mt7620_mii_busy_wait(gsw))
91 + return 0xffff;
92 +
93 + mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
94 + (phy_reg << GSW_MDIO_REG_SHIFT) |
95 + (phy_addr << GSW_MDIO_ADDR_SHIFT),
96 + MT7620A_GSW_REG_PIAC);
97 +
98 + if (mt7620_mii_busy_wait(gsw))
99 + return 0xffff;
100 +
101 + d = mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
102 +
103 + return d;
104 +}
105 +
106 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
107 +{
108 + struct fe_priv *priv = bus->priv;
109 + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
110 +
111 + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
112 +}
113 +
114 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
115 +{
116 + struct fe_priv *priv = bus->priv;
117 + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
118 +
119 + return _mt7620_mii_read(gsw, phy_addr, phy_reg);
120 +}
121 +
122 +void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
123 +{
124 + _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
125 + _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
126 + _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
127 +}
128 +
129 +u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
130 +{
131 + u16 high, low;
132 +
133 + _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
134 + low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
135 + high = _mt7620_mii_read(gsw, 0x1f, 0x10);
136 +
137 + return (high << 16) | (low & 0xffff);
138 +}
139 +
140 +static unsigned char *fe_speed_str(int speed)
141 +{
142 + switch (speed) {
143 + case 2:
144 + case SPEED_1000:
145 + return "1000";
146 + case 1:
147 + case SPEED_100:
148 + return "100";
149 + case 0:
150 + case SPEED_10:
151 + return "10";
152 + }
153 +
154 + return "? ";
155 +}
156 +
157 +int mt7620_has_carrier(struct fe_priv *priv)
158 +{
159 + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
160 + int i;
161 +
162 + for (i = 0; i < GSW_PORT6; i++)
163 + if (mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
164 + return 1;
165 + return 0;
166 +}
167 +
168 +
169 +void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
170 + int speed, int duplex)
171 +{
172 + if (link)
173 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
174 + port, fe_speed_str(speed),
175 + (duplex) ? "Full" : "Half");
176 + else
177 + netdev_info(priv->netdev, "port %d link down\n", port);
178 +}
179 +
180 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
181 +{
182 + mt7620_print_link_state(priv, port, priv->link[port],
183 + priv->phy->speed[port],
184 + (priv->phy->duplex[port] == DUPLEX_FULL));
185 +}
186 diff --git a/drivers/net/ethernet/mediatek/soc_mt7620.c b/drivers/net/ethernet/mediatek/soc_mt7620.c
187 new file mode 100644
188 index 0000000..9ad6bc9
189 --- /dev/null
190 +++ b/drivers/net/ethernet/mediatek/soc_mt7620.c
191 @@ -0,0 +1,334 @@
192 +/* This program is free software; you can redistribute it and/or modify
193 + * it under the terms of the GNU General Public License as published by
194 + * the Free Software Foundation; version 2 of the License
195 + *
196 + * This program is distributed in the hope that it will be useful,
197 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
198 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
199 + * GNU General Public License for more details.
200 + *
201 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
202 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
203 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
204 + */
205 +
206 +#include <linux/module.h>
207 +#include <linux/platform_device.h>
208 +#include <linux/if_vlan.h>
209 +#include <linux/of_net.h>
210 +
211 +#include <asm/mach-ralink/ralink_regs.h>
212 +
213 +#include <mt7620.h>
214 +#include "mtk_eth_soc.h"
215 +#include "gsw_mt7620.h"
216 +#include "mt7530.h"
217 +#include "mdio.h"
218 +
219 +#define MT7620A_CDMA_CSG_CFG 0x400
220 +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
221 +#define MT7621_CDMP_IG_CTRL (MT7620A_CDMA_CSG_CFG + 0x00)
222 +#define MT7621_CDMP_EG_CTRL (MT7620A_CDMA_CSG_CFG + 0x04)
223 +#define MT7620A_RESET_FE BIT(21)
224 +#define MT7621_RESET_FE BIT(6)
225 +#define MT7620A_RESET_ESW BIT(23)
226 +#define MT7620_L4_VALID BIT(23)
227 +#define MT7621_L4_VALID BIT(24)
228 +
229 +#define MT7620_TX_DMA_UDF BIT(15)
230 +#define MT7621_TX_DMA_UDF BIT(19)
231 +#define TX_DMA_FP_BMAP ((0xff) << 19)
232 +
233 +#define CDMA_ICS_EN BIT(2)
234 +#define CDMA_UCS_EN BIT(1)
235 +#define CDMA_TCS_EN BIT(0)
236 +
237 +#define GDMA_ICS_EN BIT(22)
238 +#define GDMA_TCS_EN BIT(21)
239 +#define GDMA_UCS_EN BIT(20)
240 +
241 +/* frame engine counters */
242 +#define MT7620_REG_MIB_OFFSET 0x1000
243 +#define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
244 +#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
245 +#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
246 +
247 +#define MT7621_REG_MIB_OFFSET 0x2000
248 +#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
249 +#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
250 +#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
251 +
252 +#define GSW_REG_GDMA1_MAC_ADRL 0x508
253 +#define GSW_REG_GDMA1_MAC_ADRH 0x50C
254 +
255 +#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
256 +#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08)
257 +
258 +/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
259 + * but after test it should be BIT(13).
260 + */
261 +#define MT7620_FE_GDM1_AF BIT(13)
262 +#define MT7621_FE_GDM1_AF BIT(28)
263 +#define MT7621_FE_GDM2_AF BIT(29)
264 +
265 +static const u16 mt7620_reg_table[FE_REG_COUNT] = {
266 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
267 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
268 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
269 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
270 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
271 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
272 + [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
273 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
274 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
275 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
276 + [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
277 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
278 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
279 + [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
280 + [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
281 + [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
282 + [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
283 +};
284 +
285 +static int mt7620_gsw_config(struct fe_priv *priv)
286 +{
287 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
288 +
289 + /* is the mt7530 internal or external */
290 + if (priv->mii_bus && priv->mii_bus->phy_map[0x1f]) {
291 + mt7530_probe(priv->device, gsw->base, NULL, 0);
292 + mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
293 + } else {
294 + mt7530_probe(priv->device, gsw->base, NULL, 1);
295 + }
296 +
297 + return 0;
298 +}
299 +
300 +static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
301 +{
302 + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
303 + unsigned long flags;
304 +
305 + spin_lock_irqsave(&priv->page_lock, flags);
306 + mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
307 + mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
308 + GSW_REG_SMACCR0);
309 + spin_unlock_irqrestore(&priv->page_lock, flags);
310 +}
311 +
312 +static void mt7620_auto_poll(struct mt7620_gsw *gsw)
313 +{
314 + int phy;
315 + int lsb = -1, msb = 0;
316 +
317 + for_each_set_bit(phy, &gsw->autopoll, 32) {
318 + if (lsb < 0)
319 + lsb = phy;
320 + msb = phy;
321 + }
322 +
323 + if (lsb == msb)
324 + lsb--;
325 +
326 + mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
327 + (msb << 8) | lsb, ESW_PHY_POLLING);
328 +}
329 +
330 +static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
331 +{
332 + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
333 + const __be32 *_id = of_get_property(np, "reg", NULL);
334 + int phy_mode, size, id;
335 + int shift = 12;
336 + u32 val, mask = 0;
337 + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
338 +
339 + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
340 + if (_id)
341 + pr_err("%s: invalid port id %d\n", np->name,
342 + be32_to_cpu(*_id));
343 + else
344 + pr_err("%s: invalid port id\n", np->name);
345 + return;
346 + }
347 +
348 + id = be32_to_cpu(*_id);
349 +
350 + if (id == 4)
351 + shift = 14;
352 +
353 + priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
354 + &size);
355 + if (priv->phy->phy_fixed[id] &&
356 + (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
357 + pr_err("%s: invalid fixed link property\n", np->name);
358 + priv->phy->phy_fixed[id] = NULL;
359 + return;
360 + }
361 +
362 + phy_mode = of_get_phy_mode(np);
363 + switch (phy_mode) {
364 + case PHY_INTERFACE_MODE_RGMII:
365 + mask = 0;
366 + break;
367 + case PHY_INTERFACE_MODE_MII:
368 + mask = 1;
369 + break;
370 + case PHY_INTERFACE_MODE_RMII:
371 + mask = 2;
372 + break;
373 + default:
374 + dev_err(priv->device, "port %d - invalid phy mode\n", id);
375 + return;
376 + }
377 +
378 + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
379 + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
380 + return;
381 +
382 + val = rt_sysc_r32(SYSC_REG_CFG1);
383 + val &= ~(3 << shift);
384 + val |= mask << shift;
385 + rt_sysc_w32(val, SYSC_REG_CFG1);
386 +
387 + if (priv->phy->phy_fixed[id]) {
388 + const __be32 *link = priv->phy->phy_fixed[id];
389 + int tx_fc, rx_fc;
390 + u32 val = 0;
391 +
392 + priv->phy->speed[id] = be32_to_cpup(link++);
393 + tx_fc = be32_to_cpup(link++);
394 + rx_fc = be32_to_cpup(link++);
395 + priv->phy->duplex[id] = be32_to_cpup(link++);
396 + priv->link[id] = 1;
397 +
398 + switch (priv->phy->speed[id]) {
399 + case SPEED_10:
400 + val = 0;
401 + break;
402 + case SPEED_100:
403 + val = 1;
404 + break;
405 + case SPEED_1000:
406 + val = 2;
407 + break;
408 + default:
409 + dev_err(priv->device, "invalid link speed: %d\n",
410 + priv->phy->speed[id]);
411 + priv->phy->phy_fixed[id] = 0;
412 + return;
413 + }
414 + val = PMCR_SPEED(val);
415 + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
416 + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
417 + if (tx_fc)
418 + val |= PMCR_TX_FC;
419 + if (rx_fc)
420 + val |= PMCR_RX_FC;
421 + if (priv->phy->duplex[id])
422 + val |= PMCR_DUPLEX;
423 + mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
424 + dev_info(priv->device, "using fixed link parameters\n");
425 + return;
426 + }
427 +
428 + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
429 + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
430 + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
431 +
432 + mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
433 + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
434 + gsw->autopoll |= BIT(id);
435 + mt7620_auto_poll(gsw);
436 + return;
437 + }
438 +}
439 +
440 +static void mt7620_fe_reset(void)
441 +{
442 + fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
443 +}
444 +
445 +static void mt7620_rxcsum_config(bool enable)
446 +{
447 + if (enable)
448 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
449 + GDMA_TCS_EN | GDMA_UCS_EN),
450 + MT7620A_GDMA1_FWD_CFG);
451 + else
452 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
453 + GDMA_TCS_EN | GDMA_UCS_EN),
454 + MT7620A_GDMA1_FWD_CFG);
455 +}
456 +
457 +static void mt7620_txcsum_config(bool enable)
458 +{
459 + if (enable)
460 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
461 + CDMA_UCS_EN | CDMA_TCS_EN),
462 + MT7620A_CDMA_CSG_CFG);
463 + else
464 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
465 + CDMA_UCS_EN | CDMA_TCS_EN),
466 + MT7620A_CDMA_CSG_CFG);
467 +}
468 +
469 +static int mt7620_fwd_config(struct fe_priv *priv)
470 +{
471 + struct net_device *dev = priv_netdev(priv);
472 +
473 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
474 +
475 + mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
476 + mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
477 +
478 + return 0;
479 +}
480 +
481 +static void mt7620_tx_dma(struct fe_tx_dma *txd)
482 +{
483 +}
484 +
485 +static void mt7620_init_data(struct fe_soc_data *data,
486 + struct net_device *netdev)
487 +{
488 + struct fe_priv *priv = netdev_priv(netdev);
489 +
490 + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
491 + FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
492 +
493 + netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
494 + NETIF_F_HW_VLAN_CTAG_TX;
495 + if (mt7620_get_eco() >= 5)
496 + netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
497 + NETIF_F_IPV6_CSUM;
498 +}
499 +
500 +static struct fe_soc_data mt7620_data = {
501 + .init_data = mt7620_init_data,
502 + .reset_fe = mt7620_fe_reset,
503 + .set_mac = mt7620_set_mac,
504 + .fwd_config = mt7620_fwd_config,
505 + .tx_dma = mt7620_tx_dma,
506 + .switch_init = mtk_gsw_init,
507 + .port_init = mt7620_port_init,
508 + .reg_table = mt7620_reg_table,
509 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
510 + .rx_int = RT5350_RX_DONE_INT,
511 + .tx_int = RT5350_TX_DONE_INT,
512 + .status_int = MT7620_FE_GDM1_AF,
513 + .checksum_bit = MT7620_L4_VALID,
514 + .has_carrier = mt7620_has_carrier,
515 + .mdio_read = mt7620_mdio_read,
516 + .mdio_write = mt7620_mdio_write,
517 + .mdio_adjust_link = mt7620_mdio_link_adjust,
518 +};
519 +
520 +const struct of_device_id of_fe_match[] = {
521 + { .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
522 + {},
523 +};
524 +
525 +MODULE_DEVICE_TABLE(of, of_fe_match);
526 --
527 1.7.10.4
528