1 From fec11d4e8dc5cc79bcd7c8fd55038ac21ac39965 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 05:22:39 +0000
4 Subject: [PATCH 04/53] MIPS: ralink: add MT7621 pcie driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/pci/Makefile | 1 +
9 arch/mips/pci/pci-mt7621.c | 813 ++++++++++++++++++++++++++++++++++++++++++++
10 2 files changed, 814 insertions(+)
11 create mode 100644 arch/mips/pci/pci-mt7621.c
13 --- a/arch/mips/pci/Makefile
14 +++ b/arch/mips/pci/Makefile
15 @@ -46,6 +46,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
16 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
17 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
18 obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
19 +obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
20 obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
21 obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
22 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
24 +++ b/arch/mips/pci/pci-mt7621.c
26 +/**************************************************************************
28 + * BRIEF MODULE DESCRIPTION
29 + * PCI init for Ralink RT2880 solution
31 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
33 + * This program is free software; you can redistribute it and/or modify it
34 + * under the terms of the GNU General Public License as published by the
35 + * Free Software Foundation; either version 2 of the License, or (at your
36 + * option) any later version.
38 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
39 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
40 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
41 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
42 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
43 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
44 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
45 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
47 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 + * You should have received a copy of the GNU General Public License along
50 + * with this program; if not, write to the Free Software Foundation, Inc.,
51 + * 675 Mass Ave, Cambridge, MA 02139, USA.
54 + **************************************************************************
55 + * May 2007 Bruce Chang
58 + * May 2009 Bruce Chang
59 + * support RT2880/RT3883 PCIe
61 + * May 2011 Bruce Chang
62 + * support RT6855/MT7620 PCIe
64 + **************************************************************************
67 +#include <linux/types.h>
68 +#include <linux/pci.h>
69 +#include <linux/kernel.h>
70 +#include <linux/slab.h>
71 +#include <linux/version.h>
74 +#include <asm/mips-cm.h>
75 +#include <linux/init.h>
76 +#include <linux/module.h>
77 +#include <linux/delay.h>
78 +#include <linux/of.h>
79 +#include <linux/of_pci.h>
80 +#include <linux/of_irq.h>
81 +#include <linux/platform_device.h>
83 +#include <ralink_regs.h>
85 +extern void pcie_phy_init(void);
86 +extern void chk_phy_pll(void);
89 + * These functions and structures provide the BIOS scan and mapping of the PCI
93 +#define CONFIG_PCIE_PORT0
94 +#define CONFIG_PCIE_PORT1
95 +#define CONFIG_PCIE_PORT2
96 +#define RALINK_PCIE0_CLK_EN (1<<24)
97 +#define RALINK_PCIE1_CLK_EN (1<<25)
98 +#define RALINK_PCIE2_CLK_EN (1<<26)
100 +#define RALINK_PCI_CONFIG_ADDR 0x20
101 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
102 +#define RALINK_INT_PCIE0 pcie_irq[0]
103 +#define RALINK_INT_PCIE1 pcie_irq[1]
104 +#define RALINK_INT_PCIE2 pcie_irq[2]
105 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
106 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
107 +#define RALINK_PCIE0_RST (1<<24)
108 +#define RALINK_PCIE1_RST (1<<25)
109 +#define RALINK_PCIE2_RST (1<<26)
110 +#define RALINK_SYSCTL_BASE 0xBE000000
112 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
113 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
114 +#define RALINK_PCI_BASE 0xBE140000
116 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
117 +#define RT6855_PCIE0_OFFSET 0x2000
118 +#define RT6855_PCIE1_OFFSET 0x3000
119 +#define RT6855_PCIE2_OFFSET 0x4000
121 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
122 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
123 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
124 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
125 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
126 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
127 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
128 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
130 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
131 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
132 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
133 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
134 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
135 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
136 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
137 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
139 +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
140 +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
141 +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
142 +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
143 +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
144 +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
145 +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
146 +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
148 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
149 +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
152 +#define MV_WRITE(ofs, data) \
153 + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
154 +#define MV_READ(ofs, data) \
155 + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
156 +#define MV_READ_DATA(ofs) \
157 + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
159 +#define MV_WRITE_16(ofs, data) \
160 + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
161 +#define MV_READ_16(ofs, data) \
162 + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
164 +#define MV_WRITE_8(ofs, data) \
165 + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
166 +#define MV_READ_8(ofs, data) \
167 + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
171 +#define RALINK_PCI_MM_MAP_BASE 0x60000000
172 +#define RALINK_PCI_IO_MAP_BASE 0x1e160000
174 +#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
176 +#define ASSERT_SYSRST_PCIE(val) do { \
177 + if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
178 + RALINK_RSTCTRL |= val; \
180 + RALINK_RSTCTRL &= ~val; \
182 +#define DEASSERT_SYSRST_PCIE(val) do { \
183 + if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
184 + RALINK_RSTCTRL &= ~val; \
186 + RALINK_RSTCTRL |= val; \
188 +#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
189 +#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
190 +#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
191 +#define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
192 +#define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
193 +#define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
194 +#define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
195 +#define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
196 +//RALINK_SYSCFG1 bit
197 +#define RALINK_PCI_HOST_MODE_EN (1<<7)
198 +#define RALINK_PCIE_RC_MODE_EN (1<<8)
199 +//RALINK_RSTCTRL bit
200 +#define RALINK_PCIE_RST (1<<23)
201 +#define RALINK_PCI_RST (1<<24)
202 +//RALINK_CLKCFG1 bit
203 +#define RALINK_PCI_CLK_EN (1<<19)
204 +#define RALINK_PCIE_CLK_EN (1<<21)
205 +//RALINK_GPIOMODE bit
206 +#define PCI_SLOTx2 (1<<11)
207 +#define PCI_SLOTx1 (2<<11)
209 +#define PDRV_SW_SET (1<<31)
210 +#define LC_CKDRVPD_ (1<<19)
212 +#define MEMORY_BASE 0x0
213 +static int pcie_link_status = 0;
215 +#define PCI_ACCESS_READ_1 0
216 +#define PCI_ACCESS_READ_2 1
217 +#define PCI_ACCESS_READ_4 2
218 +#define PCI_ACCESS_WRITE_1 3
219 +#define PCI_ACCESS_WRITE_2 4
220 +#define PCI_ACCESS_WRITE_4 5
222 +static int pcie_irq[3];
224 +static int config_access(unsigned char access_type, struct pci_bus *bus,
225 + unsigned int devfn, unsigned int where, u32 * data)
227 + unsigned int slot = PCI_SLOT(devfn);
228 + u8 func = PCI_FUNC(devfn);
229 + uint32_t address_reg, data_reg;
230 + unsigned int address;
232 + address_reg = RALINK_PCI_CONFIG_ADDR;
233 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
235 + address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
236 + MV_WRITE(address_reg, address);
238 + switch(access_type) {
239 + case PCI_ACCESS_WRITE_1:
240 + MV_WRITE_8(data_reg+(where&0x3), *data);
242 + case PCI_ACCESS_WRITE_2:
243 + MV_WRITE_16(data_reg+(where&0x3), *data);
245 + case PCI_ACCESS_WRITE_4:
246 + MV_WRITE(data_reg, *data);
248 + case PCI_ACCESS_READ_1:
249 + MV_READ_8( data_reg+(where&0x3), data);
251 + case PCI_ACCESS_READ_2:
252 + MV_READ_16(data_reg+(where&0x3), data);
254 + case PCI_ACCESS_READ_4:
255 + MV_READ(data_reg, data);
258 + printk("no specify access type\n");
265 +read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
267 + return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
271 +read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
273 + return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
277 +read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
279 + return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
283 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
285 + if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
288 + return PCIBIOS_SUCCESSFUL;
292 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
294 + if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
297 + return PCIBIOS_SUCCESSFUL;
301 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
303 + if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
306 + return PCIBIOS_SUCCESSFUL;
311 +pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
315 + return read_config_byte(bus, devfn, where, (u8 *) val);
317 + return read_config_word(bus, devfn, where, (u16 *) val);
319 + return read_config_dword(bus, devfn, where, val);
324 +pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
328 + return write_config_byte(bus, devfn, where, (u8) val);
330 + return write_config_word(bus, devfn, where, (u16) val);
332 + return write_config_dword(bus, devfn, where, val);
336 +struct pci_ops mt7621_pci_ops= {
337 + .read = pci_config_read,
338 + .write = pci_config_write,
341 +static struct resource mt7621_res_pci_mem1 = {
342 + .name = "PCI MEM1",
343 + .start = RALINK_PCI_MM_MAP_BASE,
344 + .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
345 + .flags = IORESOURCE_MEM,
347 +static struct resource mt7621_res_pci_io1 = {
348 + .name = "PCI I/O1",
349 + .start = RALINK_PCI_IO_MAP_BASE,
350 + .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
351 + .flags = IORESOURCE_IO,
354 +static struct pci_controller mt7621_controller = {
355 + .pci_ops = &mt7621_pci_ops,
356 + .mem_resource = &mt7621_res_pci_mem1,
357 + .io_resource = &mt7621_res_pci_io1,
358 + .mem_offset = 0x00000000UL,
359 + .io_offset = 0x00000000UL,
360 + .io_map_base = 0xa0000000,
364 +read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
366 + unsigned int address_reg, data_reg, address;
368 + address_reg = RALINK_PCI_CONFIG_ADDR;
369 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
370 + address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
371 + MV_WRITE(address_reg, address);
372 + MV_READ(data_reg, val);
377 +write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
379 + unsigned int address_reg, data_reg, address;
381 + address_reg = RALINK_PCI_CONFIG_ADDR;
382 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
383 + address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
384 + MV_WRITE(address_reg, address);
385 + MV_WRITE(data_reg, val);
391 +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
397 + if ((dev->bus->number == 0) && (slot == 0)) {
398 + write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
399 + read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
400 + printk("BAR0 at slot 0 = %x\n", val);
401 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
402 + } else if((dev->bus->number == 0) && (slot == 0x1)) {
403 + write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
404 + read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
405 + printk("BAR0 at slot 1 = %x\n", val);
406 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
407 + } else if((dev->bus->number == 0) && (slot == 0x2)) {
408 + write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
409 + read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
410 + printk("BAR0 at slot 2 = %x\n", val);
411 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
412 + } else if ((dev->bus->number == 1) && (slot == 0x0)) {
413 + switch (pcie_link_status) {
416 + irq = RALINK_INT_PCIE1;
419 + irq = RALINK_INT_PCIE2;
422 + irq = RALINK_INT_PCIE0;
424 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
425 + } else if ((dev->bus->number == 2) && (slot == 0x0)) {
426 + switch (pcie_link_status) {
429 + irq = RALINK_INT_PCIE2;
432 + irq = RALINK_INT_PCIE1;
434 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
435 + } else if ((dev->bus->number == 2) && (slot == 0x1)) {
436 + switch (pcie_link_status) {
439 + irq = RALINK_INT_PCIE2;
442 + irq = RALINK_INT_PCIE1;
444 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
445 + } else if ((dev->bus->number ==3) && (slot == 0x0)) {
446 + irq = RALINK_INT_PCIE2;
447 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
448 + } else if ((dev->bus->number ==3) && (slot == 0x1)) {
449 + irq = RALINK_INT_PCIE2;
450 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
451 + } else if ((dev->bus->number ==3) && (slot == 0x2)) {
452 + irq = RALINK_INT_PCIE2;
453 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
455 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
459 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
460 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
461 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
462 + cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
463 + pci_write_config_word(dev, PCI_COMMAND, cmd);
464 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
469 +set_pcie_phy(u32 *addr, int start_b, int bits, int val)
471 +// printk("0x%p:", addr);
472 +// printk(" %x", *addr);
473 + *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
474 + *(unsigned int *)(addr) |= val << start_b;
475 +// printk(" -> %x\n", *addr);
479 +bypass_pipe_rst(void)
481 +#if defined (CONFIG_PCIE_PORT0)
483 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
484 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
486 +#if defined (CONFIG_PCIE_PORT1)
488 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
489 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
491 +#if defined (CONFIG_PCIE_PORT2)
493 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
494 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
499 +set_phy_for_ssc(void)
501 + unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
503 + reg = (reg >> 6) & 0x7;
504 +#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
505 + /* Set PCIe Port0 & Port1 PHY to disable SSC */
506 + /* Debug Xtal Type */
507 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
508 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
509 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
510 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
511 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
512 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
513 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
514 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
515 + printk("***** Xtal 40MHz *****\n");
516 + } else { // 25MHz | 20MHz Xtal
517 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
519 + printk("***** Xtal 25MHz *****\n");
520 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
521 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
522 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
523 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
524 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
526 + printk("***** Xtal 20MHz *****\n");
529 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
530 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
531 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
532 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
533 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
534 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
535 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
536 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
537 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
538 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
540 + /* Enable PHY and disable force mode */
541 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
542 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
543 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
544 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
546 +#if defined (CONFIG_PCIE_PORT2)
547 + /* Set PCIe Port2 PHY to disable SSC */
548 + /* Debug Xtal Type */
549 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
550 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
551 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
552 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
553 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
554 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
555 + } else { // 25MHz | 20MHz Xtal
556 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
557 + if (reg >= 6) { // 25MHz Xtal
558 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
559 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
560 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
561 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
562 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
565 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
566 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
567 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
568 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
569 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
570 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
571 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
572 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
573 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
574 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
576 + /* Enable PHY and disable force mode */
577 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
578 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
582 +void setup_cm_memory_region(struct resource *mem_resource)
584 + resource_size_t mask;
585 + if (mips_cm_numiocu()) {
586 + /* FIXME: hardware doesn't accept mask values with 1s after
587 + 0s (e.g. 0xffef), so it would be great to warn if that's
589 + mask = ~(mem_resource->end - mem_resource->start);
591 + write_gcr_reg1_base(mem_resource->start);
592 + write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
593 + printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
594 + read_gcr_reg1_base(),
595 + read_gcr_reg1_mask());
599 +static int mt7621_pci_probe(struct platform_device *pdev)
601 + unsigned long val = 0;
604 + for (i = 0; i < 3; i++)
605 + pcie_irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
607 + iomem_resource.start = 0;
608 + iomem_resource.end= ~0;
609 + ioport_resource.start= 0;
610 + ioport_resource.end = ~0;
612 +#if defined (CONFIG_PCIE_PORT0)
613 + val = RALINK_PCIE0_RST;
615 +#if defined (CONFIG_PCIE_PORT1)
616 + val |= RALINK_PCIE1_RST;
618 +#if defined (CONFIG_PCIE_PORT2)
619 + val |= RALINK_PCIE2_RST;
621 + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
622 + printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
623 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
624 + *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
625 + *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
627 + *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
629 + *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
633 + *(unsigned int *)(0xbe000060) &= ~0x00000c00;
635 +#if defined (CONFIG_PCIE_PORT0)
636 + val = RALINK_PCIE0_RST;
638 +#if defined (CONFIG_PCIE_PORT1)
639 + val |= RALINK_PCIE1_RST;
641 +#if defined (CONFIG_PCIE_PORT2)
642 + val |= RALINK_PCIE2_RST;
644 + DEASSERT_SYSRST_PCIE(val);
645 + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
647 + if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
650 + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
652 +#if defined (CONFIG_PCIE_PORT0)
653 + read_config(0, 0, 0, 0x70c, &val);
654 + printk("Port 0 N_FTS = %x\n", (unsigned int)val);
656 +#if defined (CONFIG_PCIE_PORT1)
657 + read_config(0, 1, 0, 0x70c, &val);
658 + printk("Port 1 N_FTS = %x\n", (unsigned int)val);
660 +#if defined (CONFIG_PCIE_PORT2)
661 + read_config(0, 2, 0, 0x70c, &val);
662 + printk("Port 2 N_FTS = %x\n", (unsigned int)val);
665 + RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
666 + RALINK_SYSCFG1 &= ~(0x30);
667 + RALINK_SYSCFG1 |= (2<<4);
668 + RALINK_PCIE_CLK_GEN &= 0x7fffffff;
669 + RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
670 + RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
671 + RALINK_PCIE_CLK_GEN |= 0x80000000;
673 + RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
676 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
677 + *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
680 + RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
686 +#if defined (CONFIG_PCIE_PORT0)
687 + if(( RALINK_PCI0_STATUS & 0x1) == 0)
689 + printk("PCIE0 no card, disable it(RST&CLK)\n");
690 + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
691 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
692 + pcie_link_status &= ~(1<<0);
694 + pcie_link_status |= 1<<0;
695 + RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
698 +#if defined (CONFIG_PCIE_PORT1)
699 + if(( RALINK_PCI1_STATUS & 0x1) == 0)
701 + printk("PCIE1 no card, disable it(RST&CLK)\n");
702 + ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
703 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
704 + pcie_link_status &= ~(1<<1);
706 + pcie_link_status |= 1<<1;
707 + RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
710 +#if defined (CONFIG_PCIE_PORT2)
711 + if (( RALINK_PCI2_STATUS & 0x1) == 0) {
712 + printk("PCIE2 no card, disable it(RST&CLK)\n");
713 + ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
714 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
715 + pcie_link_status &= ~(1<<2);
717 + pcie_link_status |= 1<<2;
718 + RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
721 + if (pcie_link_status == 0)
725 +pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
735 + switch(pcie_link_status) {
737 + RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
738 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
739 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
742 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
743 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
744 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
745 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
748 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
749 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
750 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
751 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
754 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
755 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
756 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
757 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
760 + printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
761 + //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
764 + ioport_resource.start = mt7621_res_pci_io1.start;
765 + ioport_resource.end = mt7621_res_pci_io1.end;
768 + RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
769 + RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
771 +#if defined (CONFIG_PCIE_PORT0)
773 + if((pcie_link_status & 0x1) != 0) {
774 + RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
775 + RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
776 + RALINK_PCI0_CLASS = 0x06040001;
777 + printk("PCIE0 enabled\n");
780 +#if defined (CONFIG_PCIE_PORT1)
782 + if ((pcie_link_status & 0x2) != 0) {
783 + RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
784 + RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
785 + RALINK_PCI1_CLASS = 0x06040001;
786 + printk("PCIE1 enabled\n");
789 +#if defined (CONFIG_PCIE_PORT2)
791 + if ((pcie_link_status & 0x4) != 0) {
792 + RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
793 + RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
794 + RALINK_PCI2_CLASS = 0x06040001;
795 + printk("PCIE2 enabled\n");
800 + switch(pcie_link_status) {
802 + read_config(0, 2, 0, 0x4, &val);
803 + write_config(0, 2, 0, 0x4, val|0x4);
804 + // write_config(0, 1, 0, 0x4, val|0x7);
805 + read_config(0, 2, 0, 0x70c, &val);
808 + write_config(0, 2, 0, 0x70c, val);
812 + read_config(0, 1, 0, 0x4, &val);
813 + write_config(0, 1, 0, 0x4, val|0x4);
814 + // write_config(0, 1, 0, 0x4, val|0x7);
815 + read_config(0, 1, 0, 0x70c, &val);
818 + write_config(0, 1, 0, 0x70c, val);
820 + read_config(0, 0, 0, 0x4, &val);
821 + write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
822 + // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
823 + read_config(0, 0, 0, 0x70c, &val);
826 + write_config(0, 0, 0, 0x70c, val);
829 + pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
830 + setup_cm_memory_region(mt7621_controller.mem_resource);
831 + register_pci_controller(&mt7621_controller);
836 +int pcibios_plat_dev_init(struct pci_dev *dev)
841 +static const struct of_device_id mt7621_pci_ids[] = {
842 + { .compatible = "mediatek,mt7621-pci" },
845 +MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
847 +static struct platform_driver mt7621_pci_driver = {
848 + .probe = mt7621_pci_probe,
850 + .name = "mt7621-pci",
851 + .owner = THIS_MODULE,
852 + .of_match_table = of_match_ptr(mt7621_pci_ids),
856 +static int __init mt7621_pci_init(void)
858 + return platform_driver_register(&mt7621_pci_driver);
861 +arch_initcall(mt7621_pci_init);