1 There is a variant of MT7621 which contains only one CPU core instead of 2.
2 This is not reflected in the config register, so the kernel detects more
3 physical cores, which leads to a hang on SMP bringup.
4 Add a hack to detect missing cores.
6 Signed-off-by: Felix Fietkau <nbd@nbd.name>
8 --- a/arch/mips/kernel/smp-cps.c
9 +++ b/arch/mips/kernel/smp-cps.c
10 @@ -43,6 +43,11 @@ static unsigned core_vpe_count(unsigned
11 return mips_cps_numvps(cluster, core);
14 +bool __weak plat_cpu_core_present(int core)
19 static void __init cps_smp_setup(void)
21 unsigned int nclusters, ncores, nvpes, core_vpes;
22 @@ -60,6 +65,8 @@ static void __init cps_smp_setup(void)
24 ncores = mips_cps_numcores(cl);
25 for (c = 0; c < ncores; c++) {
26 + if (!plat_cpu_core_present(c))
28 core_vpes = core_vpe_count(cl, c);
31 --- a/arch/mips/ralink/mt7621.c
32 +++ b/arch/mips/ralink/mt7621.c
34 #include <asm/mips-cps.h>
35 #include <asm/mach-ralink/ralink_regs.h>
36 #include <asm/mach-ralink/mt7621.h>
37 +#include <asm/mips-boards/launch.h>
41 @@ -160,6 +161,20 @@ void __init ralink_of_remap(void)
42 panic("Failed to remap core resources");
45 +bool plat_cpu_core_present(int core)
47 + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
51 + launch += core * 2; /* 2 VPEs per core */
52 + if (!(launch->flags & LAUNCH_FREADY))
54 + if (launch->flags & (LAUNCH_FGO | LAUNCH_FGONE))
59 void prom_soc_init(struct ralink_soc_info *soc_info)
61 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);