1 From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 11:15:12 +0100
4 Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver
6 Add the driver needed to make SPI work on Ralink SoC.
8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
9 Acked-by: John Crispin <blogic@openwrt.org>
11 drivers/spi/Kconfig | 6 +
12 drivers/spi/Makefile | 1 +
13 drivers/spi/spi-rt2880.c | 530 ++++++++++++++++++++++++++++++++++++++++++++++
14 3 files changed, 537 insertions(+)
15 create mode 100644 drivers/spi/spi-rt2880.c
17 --- a/drivers/spi/Kconfig
18 +++ b/drivers/spi/Kconfig
19 @@ -718,6 +718,12 @@ config SPI_QCOM_GENI
20 This driver can also be built as a module. If so, the module
21 will be called spi-geni-qcom.
24 + tristate "Ralink RT288x SPI Controller"
27 + This selects a driver for the Ralink RT288x/RT305x SPI Controller.
30 tristate "Samsung S3C24XX series SPI"
31 depends on ARCH_S3C24XX
32 --- a/drivers/spi/Makefile
33 +++ b/drivers/spi/Makefile
34 @@ -100,6 +100,7 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
35 obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
36 obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
37 obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
38 +obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o
39 obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
40 spi-s3c24xx-hw-y := spi-s3c24xx.o
41 obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o
43 +++ b/drivers/spi/spi-rt2880.c
46 + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
48 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
49 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
51 + * Some parts are based on spi-orion.c:
52 + * Author: Shadi Ammouri <shadi@marvell.com>
53 + * Copyright (C) 2007-2008 Marvell Ltd.
55 + * This program is free software; you can redistribute it and/or modify
56 + * it under the terms of the GNU General Public License version 2 as
57 + * published by the Free Software Foundation.
60 +#include <linux/init.h>
61 +#include <linux/module.h>
62 +#include <linux/clk.h>
63 +#include <linux/err.h>
64 +#include <linux/delay.h>
65 +#include <linux/io.h>
66 +#include <linux/reset.h>
67 +#include <linux/spi/spi.h>
68 +#include <linux/platform_device.h>
69 +#include <linux/gpio.h>
71 +#define DRIVER_NAME "spi-rt2880"
73 +#define RAMIPS_SPI_STAT 0x00
74 +#define RAMIPS_SPI_CFG 0x10
75 +#define RAMIPS_SPI_CTL 0x14
76 +#define RAMIPS_SPI_DATA 0x20
77 +#define RAMIPS_SPI_ADDR 0x24
78 +#define RAMIPS_SPI_BS 0x28
79 +#define RAMIPS_SPI_USER 0x2C
80 +#define RAMIPS_SPI_TXFIFO 0x30
81 +#define RAMIPS_SPI_RXFIFO 0x34
82 +#define RAMIPS_SPI_FIFO_STAT 0x38
83 +#define RAMIPS_SPI_MODE 0x3C
84 +#define RAMIPS_SPI_DEV_OFFSET 0x40
85 +#define RAMIPS_SPI_DMA 0x80
86 +#define RAMIPS_SPI_DMASTAT 0x84
87 +#define RAMIPS_SPI_ARBITER 0xF0
89 +/* SPISTAT register bit field */
90 +#define SPISTAT_BUSY BIT(0)
92 +/* SPICFG register bit field */
93 +#define SPICFG_ADDRMODE BIT(12)
94 +#define SPICFG_RXENVDIS BIT(11)
95 +#define SPICFG_RXCAP BIT(10)
96 +#define SPICFG_SPIENMODE BIT(9)
97 +#define SPICFG_MSBFIRST BIT(8)
98 +#define SPICFG_SPICLKPOL BIT(6)
99 +#define SPICFG_RXCLKEDGE_FALLING BIT(5)
100 +#define SPICFG_TXCLKEDGE_FALLING BIT(4)
101 +#define SPICFG_HIZSPI BIT(3)
102 +#define SPICFG_SPICLK_PRESCALE_MASK 0x7
103 +#define SPICFG_SPICLK_DIV2 0
104 +#define SPICFG_SPICLK_DIV4 1
105 +#define SPICFG_SPICLK_DIV8 2
106 +#define SPICFG_SPICLK_DIV16 3
107 +#define SPICFG_SPICLK_DIV32 4
108 +#define SPICFG_SPICLK_DIV64 5
109 +#define SPICFG_SPICLK_DIV128 6
110 +#define SPICFG_SPICLK_DISABLE 7
112 +/* SPICTL register bit field */
113 +#define SPICTL_START BIT(4)
114 +#define SPICTL_HIZSDO BIT(3)
115 +#define SPICTL_STARTWR BIT(2)
116 +#define SPICTL_STARTRD BIT(1)
117 +#define SPICTL_SPIENA BIT(0)
119 +/* SPIUSER register bit field */
120 +#define SPIUSER_USERMODE BIT(21)
121 +#define SPIUSER_INSTR_PHASE BIT(20)
122 +#define SPIUSER_ADDR_PHASE_MASK 0x7
123 +#define SPIUSER_ADDR_PHASE_OFFSET 17
124 +#define SPIUSER_MODE_PHASE BIT(16)
125 +#define SPIUSER_DUMMY_PHASE_MASK 0x3
126 +#define SPIUSER_DUMMY_PHASE_OFFSET 14
127 +#define SPIUSER_DATA_PHASE_MASK 0x3
128 +#define SPIUSER_DATA_PHASE_OFFSET 12
129 +#define SPIUSER_DATA_READ (BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
130 +#define SPIUSER_DATA_WRITE (BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
131 +#define SPIUSER_ADDR_TYPE_OFFSET 9
132 +#define SPIUSER_MODE_TYPE_OFFSET 6
133 +#define SPIUSER_DUMMY_TYPE_OFFSET 3
134 +#define SPIUSER_DATA_TYPE_OFFSET 0
135 +#define SPIUSER_TRANSFER_MASK 0x7
136 +#define SPIUSER_TRANSFER_SINGLE BIT(0)
137 +#define SPIUSER_TRANSFER_DUAL BIT(1)
138 +#define SPIUSER_TRANSFER_QUAD BIT(2)
140 +#define SPIUSER_TRANSFER_TYPE(type) ( \
141 + (type << SPIUSER_ADDR_TYPE_OFFSET) | \
142 + (type << SPIUSER_MODE_TYPE_OFFSET) | \
143 + (type << SPIUSER_DUMMY_TYPE_OFFSET) | \
144 + (type << SPIUSER_DATA_TYPE_OFFSET) \
147 +/* SPIFIFOSTAT register bit field */
148 +#define SPIFIFOSTAT_TXEMPTY BIT(19)
149 +#define SPIFIFOSTAT_RXEMPTY BIT(18)
150 +#define SPIFIFOSTAT_TXFULL BIT(17)
151 +#define SPIFIFOSTAT_RXFULL BIT(16)
152 +#define SPIFIFOSTAT_FIFO_MASK 0xff
153 +#define SPIFIFOSTAT_TX_OFFSET 8
154 +#define SPIFIFOSTAT_RX_OFFSET 0
156 +#define SPI_FIFO_DEPTH 16
158 +/* SPIMODE register bit field */
159 +#define SPIMODE_MODE_OFFSET 24
160 +#define SPIMODE_DUMMY_OFFSET 0
162 +/* SPIARB register bit field */
163 +#define SPICTL_ARB_EN BIT(31)
164 +#define SPICTL_CSCTL1 BIT(16)
165 +#define SPI1_POR BIT(1)
166 +#define SPI0_POR BIT(0)
168 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \
171 +static atomic_t hw_reset_count = ATOMIC_INIT(0);
174 + struct spi_master *master;
175 + void __iomem *base;
182 +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
184 + return spi_master_get_devdata(spi->master);
187 +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
189 + return ioread32(rs->base + reg);
192 +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,
195 + iowrite32(val, rs->base + reg);
198 +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
200 + void __iomem *addr = rs->base + reg;
202 + iowrite32((ioread32(addr) | mask), addr);
205 +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
207 + void __iomem *addr = rs->base + reg;
209 + iowrite32((ioread32(addr) & ~mask), addr);
212 +static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)
214 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
219 + * the supported rates are: 2, 4, 8, ... 128
220 + * round up as we look for equal or less speed
222 + rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);
223 + rate = roundup_pow_of_two(rate);
225 + /* Convert the rate to SPI clock divisor value. */
226 + prescale = ilog2(rate / 2);
228 + /* some tolerance. double and add 100 */
229 + rs->wait_loops = (8 * HZ * loops_per_jiffy) /
230 + (clk_get_rate(rs->clk) / rate);
231 + rs->wait_loops = (rs->wait_loops << 1) + 100;
234 + dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n",
235 + clk_get_rate(rs->clk) / rate, speed, rate, prescale,
241 +static u32 get_arbiter_offset(struct spi_master *master)
245 + offset = RAMIPS_SPI_ARBITER;
246 + if (master->bus_num == 1)
247 + offset -= RAMIPS_SPI_DEV_OFFSET;
252 +static void rt2880_spi_set_cs(struct spi_device *spi, bool enable)
254 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
257 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
259 + rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
262 +static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)
264 + int loop = rs->wait_loops * len;
266 + while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)
275 +static void rt2880_dump_reg(struct spi_master *master)
277 + struct rt2880_spi *rs = spi_master_get_devdata(master);
279 + dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \
280 + "data: %08x, arb: %08x\n",
281 + rt2880_spi_read(rs, RAMIPS_SPI_STAT),
282 + rt2880_spi_read(rs, RAMIPS_SPI_CFG),
283 + rt2880_spi_read(rs, RAMIPS_SPI_CTL),
284 + rt2880_spi_read(rs, RAMIPS_SPI_DATA),
285 + rt2880_spi_read(rs, get_arbiter_offset(master)));
288 +static int rt2880_spi_transfer_one(struct spi_master *master,
289 + struct spi_device *spi, struct spi_transfer *xfer)
291 + struct rt2880_spi *rs = spi_master_get_devdata(master);
293 + const u8 *tx = xfer->tx_buf;
294 + u8 *rx = xfer->rx_buf;
297 + /* change clock speed */
298 + if (unlikely(rs->speed != xfer->speed_hz)) {
300 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
301 + reg &= ~SPICFG_SPICLK_PRESCALE_MASK;
302 + reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz);
303 + rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
308 + while (len-- > 0) {
309 + rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++);
310 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
311 + err = rt2880_spi_wait_ready(rs, 1);
313 + dev_err(&spi->dev, "TX failed, err=%d\n", err);
321 + while (len-- > 0) {
322 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
323 + err = rt2880_spi_wait_ready(rs, 1);
325 + dev_err(&spi->dev, "RX failed, err=%d\n", err);
328 + *rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
336 +/* copy from spi.c */
337 +static void spi_set_cs(struct spi_device *spi, bool enable)
339 + if (spi->mode & SPI_CS_HIGH)
343 + gpiod_set_value(spi->cs_gpiod, !enable);
344 + else if (spi->master->set_cs)
345 + spi->master->set_cs(spi, !enable);
348 +static int rt2880_spi_setup(struct spi_device *spi)
350 + struct spi_master *master = spi->master;
351 + struct rt2880_spi *rs = spi_master_get_devdata(master);
352 + u32 reg, old_reg, arbit_off;
354 + if ((spi->max_speed_hz > master->max_speed_hz) ||
355 + (spi->max_speed_hz < master->min_speed_hz)) {
356 + dev_err(&spi->dev, "invalide requested speed %d Hz\n",
357 + spi->max_speed_hz);
361 + if (!(master->bits_per_word_mask &
362 + BIT(spi->bits_per_word - 1))) {
363 + dev_err(&spi->dev, "invalide bits_per_word %d\n",
364 + spi->bits_per_word);
368 + /* the hardware seems can't work on mode0 force it to mode3 */
369 + if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {
370 + dev_warn(&spi->dev, "force spi mode3\n");
371 + spi->mode |= SPI_MODE_3;
374 + /* chip polarity */
375 + arbit_off = get_arbiter_offset(master);
376 + reg = old_reg = rt2880_spi_read(rs, arbit_off);
377 + if (spi->mode & SPI_CS_HIGH) {
378 + switch (master->bus_num) {
387 + switch (master->bus_num) {
398 + if (master->bus_num == 1)
399 + reg |= SPICTL_ARB_EN;
401 + if (reg != old_reg)
402 + rt2880_spi_write(rs, arbit_off, reg);
404 + /* deselected the spi device */
405 + spi_set_cs(spi, false);
407 + rt2880_dump_reg(master);
412 +static int rt2880_spi_prepare_message(struct spi_master *master,
413 + struct spi_message *msg)
415 + struct rt2880_spi *rs = spi_master_get_devdata(master);
416 + struct spi_device *spi = msg->spi;
419 + if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))
423 + /* set spido to tri-state */
424 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);
427 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
429 + reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |
430 + SPICFG_RXCLKEDGE_FALLING |
431 + SPICFG_TXCLKEDGE_FALLING |
432 + SPICFG_SPICLK_PRESCALE_MASK);
435 + if (!(spi->mode & SPI_LSB_FIRST))
436 + reg |= SPICFG_MSBFIRST;
439 + switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
441 + reg |= SPICFG_TXCLKEDGE_FALLING;
444 + reg |= SPICFG_RXCLKEDGE_FALLING;
447 + reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
450 + reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
453 + rs->mode = spi->mode;
456 + /* set spiclk and spiena to tri-state */
457 + reg |= SPICFG_HIZSPI;
461 + reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);
463 + rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
468 +static int rt2880_spi_probe(struct platform_device *pdev)
470 + struct spi_master *master;
471 + struct rt2880_spi *rs;
472 + void __iomem *base;
473 + struct resource *r;
477 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 + base = devm_ioremap_resource(&pdev->dev, r);
480 + return PTR_ERR(base);
482 + clk = devm_clk_get(&pdev->dev, NULL);
484 + dev_err(&pdev->dev, "unable to get SYS clock\n");
485 + return PTR_ERR(clk);
488 + ret = clk_prepare_enable(clk);
492 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
493 + if (master == NULL) {
494 + dev_dbg(&pdev->dev, "master allocation failed\n");
499 + master->dev.of_node = pdev->dev.of_node;
500 + master->mode_bits = RT2880_SPI_MODE_BITS;
501 + master->bits_per_word_mask = SPI_BPW_MASK(8);
502 + master->min_speed_hz = clk_get_rate(clk) / 128;
503 + master->max_speed_hz = clk_get_rate(clk) / 2;
504 + master->flags = SPI_MASTER_HALF_DUPLEX;
505 + master->setup = rt2880_spi_setup;
506 + master->prepare_message = rt2880_spi_prepare_message;
507 + master->set_cs = rt2880_spi_set_cs;
508 + master->transfer_one = rt2880_spi_transfer_one,
510 + dev_set_drvdata(&pdev->dev, master);
512 + rs = spi_master_get_devdata(master);
513 + rs->master = master;
517 + if (atomic_inc_return(&hw_reset_count) == 1) {
518 + ret = device_reset(&pdev->dev);
520 + dev_err(&pdev->dev, "device_reset error.\n");
525 + ret = devm_spi_register_master(&pdev->dev, master);
527 + dev_err(&pdev->dev, "devm_spi_register_master error.\n");
534 + spi_master_put(master);
537 + clk_disable_unprepare(clk);
542 +static int rt2880_spi_remove(struct platform_device *pdev)
544 + struct spi_master *master;
545 + struct rt2880_spi *rs;
547 + master = dev_get_drvdata(&pdev->dev);
548 + rs = spi_master_get_devdata(master);
550 + clk_disable_unprepare(rs->clk);
551 + atomic_dec(&hw_reset_count);
556 +MODULE_ALIAS("platform:" DRIVER_NAME);
558 +static const struct of_device_id rt2880_spi_match[] = {
559 + { .compatible = "ralink,rt2880-spi" },
562 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
564 +static struct platform_driver rt2880_spi_driver = {
566 + .name = DRIVER_NAME,
567 + .owner = THIS_MODULE,
568 + .of_match_table = rt2880_spi_match,
570 + .probe = rt2880_spi_probe,
571 + .remove = rt2880_spi_remove,
574 +module_platform_driver(rt2880_spi_driver);
576 +MODULE_DESCRIPTION("Ralink SPI driver");
577 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
578 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
579 +MODULE_LICENSE("GPL");