1 From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:52:56 +0100
4 Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
9 drivers/i2c/busses/Kconfig | 4 +
10 drivers/i2c/busses/Makefile | 1 +
11 drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++
12 4 files changed, 359 insertions(+)
13 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
14 create mode 100644 drivers/i2c/busses/i2c-ralink.c
17 +++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
19 +I2C for Ralink platforms
21 +Required properties :
22 +- compatible : Must be "link,rt3052-i2c"
23 +- reg: physical base address of the controller and length of memory mapped
25 +- #address-cells = <1>;
29 +- Child nodes conforming to i2c bus binding
35 + compatible = "link,rt3052-i2c";
36 + reg = <0x900 0x100>;
37 + #address-cells = <1>;
41 + compatible = "national,lm92";
46 --- a/drivers/i2c/busses/Kconfig
47 +++ b/drivers/i2c/busses/Kconfig
48 @@ -998,6 +998,11 @@ config I2C_RK3X
49 This driver can also be built as a module. If so, the module will
53 + tristate "Ralink I2C Controller"
54 + depends on RALINK && !SOC_MT7621
58 tristate "Renesas RZ/V2M adapter"
59 depends on ARCH_RENESAS || COMPILE_TEST
60 --- a/drivers/i2c/busses/Makefile
61 +++ b/drivers/i2c/busses/Makefile
62 @@ -97,6 +97,7 @@ obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pc
63 obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
64 obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
65 obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
66 +obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
67 obj-$(CONFIG_I2C_QCOM_CCI) += i2c-qcom-cci.o
68 obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o
69 obj-$(CONFIG_I2C_QUP) += i2c-qup.o
71 +++ b/drivers/i2c/busses/i2c-ralink.c
74 + * drivers/i2c/busses/i2c-ralink.c
76 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
77 + * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
79 + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
80 + * (C) 2014 Sittisak <sittisaks@hotmail.com>
82 + * This software is licensed under the terms of the GNU General Public
83 + * License version 2, as published by the Free Software Foundation, and
84 + * may be copied, distributed, and modified under those terms.
86 + * This program is distributed in the hope that it will be useful,
87 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
88 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
89 + * GNU General Public License for more details.
93 +#include <linux/interrupt.h>
94 +#include <linux/kernel.h>
95 +#include <linux/module.h>
96 +#include <linux/reset.h>
97 +#include <linux/delay.h>
98 +#include <linux/slab.h>
99 +#include <linux/init.h>
100 +#include <linux/errno.h>
101 +#include <linux/platform_device.h>
102 +#include <linux/of_platform.h>
103 +#include <linux/i2c.h>
104 +#include <linux/io.h>
105 +#include <linux/err.h>
106 +#include <linux/clk.h>
108 +#define REG_CONFIG_REG 0x00
109 +#define REG_CLKDIV_REG 0x04
110 +#define REG_DEVADDR_REG 0x08
111 +#define REG_ADDR_REG 0x0C
112 +#define REG_DATAOUT_REG 0x10
113 +#define REG_DATAIN_REG 0x14
114 +#define REG_STATUS_REG 0x18
115 +#define REG_STARTXFR_REG 0x1C
116 +#define REG_BYTECNT_REG 0x20
118 +/* REG_CONFIG_REG */
119 +#define I2C_ADDRLEN_OFFSET 5
120 +#define I2C_DEVADLEN_OFFSET 2
121 +#define I2C_ADDRLEN_MASK 0x3
122 +#define I2C_ADDR_DIS BIT(1)
123 +#define I2C_DEVADDR_DIS BIT(0)
124 +#define I2C_ADDRLEN_8 (7 << I2C_ADDRLEN_OFFSET)
125 +#define I2C_DEVADLEN_7 (6 << I2C_DEVADLEN_OFFSET)
126 +#define I2C_CONF_DEFAULT (I2C_ADDRLEN_8 | I2C_DEVADLEN_7)
128 +/* REG_CLKDIV_REG */
129 +#define I2C_CLKDIV_MASK 0xffff
131 +/* REG_DEVADDR_REG */
132 +#define I2C_DEVADDR_MASK 0x7f
135 +#define I2C_ADDR_MASK 0xff
137 +/* REG_STATUS_REG */
138 +#define I2C_STARTERR BIT(4)
139 +#define I2C_ACKERR BIT(3)
140 +#define I2C_DATARDY BIT(2)
141 +#define I2C_SDOEMPTY BIT(1)
142 +#define I2C_BUSY BIT(0)
144 +/* REG_STARTXFR_REG */
145 +#define NOSTOP_CMD BIT(2)
146 +#define NODATA_CMD BIT(1)
147 +#define READ_CMD BIT(0)
149 +/* REG_BYTECNT_REG */
150 +#define BYTECNT_MAX 64
151 +#define SET_BYTECNT(x) (x - 1)
153 +/* timeout waiting for I2C devices to respond (clock streching) */
154 +#define TIMEOUT_MS 1000
155 +#define DELAY_INTERVAL_US 100
158 + void __iomem *base;
160 + struct device *dev;
161 + struct i2c_adapter adap;
167 +static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg)
169 + iowrite32(val, i2c->base + reg);
172 +static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg)
174 + return ioread32(i2c->base + reg);
177 +static int poll_down_timeout(void __iomem *addr, u32 mask)
179 + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
182 + if (!(readl_relaxed(addr) & mask))
185 + usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
186 + } while (time_before(jiffies, timeout));
188 + return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
191 +static int rt_i2c_wait_idle(struct rt_i2c *i2c)
195 + ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY);
197 + dev_dbg(i2c->dev, "idle err(%d)\n", ret);
202 +static int poll_up_timeout(void __iomem *addr, u32 mask)
204 + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
208 + status = readl_relaxed(addr);
210 + /* check error status */
211 + if (status & I2C_STARTERR)
213 + else if (status & I2C_ACKERR)
215 + else if (status & mask)
218 + usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
219 + } while (time_before(jiffies, timeout));
224 +static int rt_i2c_wait_rx_done(struct rt_i2c *i2c)
228 + ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY);
230 + dev_dbg(i2c->dev, "rx err(%d)\n", ret);
235 +static int rt_i2c_wait_tx_done(struct rt_i2c *i2c)
239 + ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY);
241 + dev_dbg(i2c->dev, "tx err(%d)\n", ret);
246 +static void rt_i2c_reset(struct rt_i2c *i2c)
250 + ret = device_reset(i2c->adap.dev.parent);
252 + dev_err(i2c->dev, "Failed to reset device");
255 + rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG);
258 +static void rt_i2c_dump_reg(struct rt_i2c *i2c)
260 + dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \
261 + "addr %08x, dataout %08x, datain %08x, " \
262 + "status %08x, startxfr %08x, bytecnt %08x\n",
263 + rt_i2c_r32(i2c, REG_CONFIG_REG),
264 + rt_i2c_r32(i2c, REG_CLKDIV_REG),
265 + rt_i2c_r32(i2c, REG_DEVADDR_REG),
266 + rt_i2c_r32(i2c, REG_ADDR_REG),
267 + rt_i2c_r32(i2c, REG_DATAOUT_REG),
268 + rt_i2c_r32(i2c, REG_DATAIN_REG),
269 + rt_i2c_r32(i2c, REG_STATUS_REG),
270 + rt_i2c_r32(i2c, REG_STARTXFR_REG),
271 + rt_i2c_r32(i2c, REG_BYTECNT_REG));
274 +static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
277 + struct rt_i2c *i2c;
278 + struct i2c_msg *pmsg;
279 + unsigned char addr;
283 + i2c = i2c_get_adapdata(adap);
285 + for (i = 0; i < num; i++) {
287 + if (i == (num - 1))
292 + dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n",
293 + pmsg->addr, pmsg->len, pmsg->flags,
294 + (cmd == 0)? 1 : 0);
296 + /* wait hardware idle */
297 + if ((ret = rt_i2c_wait_idle(i2c)))
300 + if (pmsg->flags & I2C_M_TEN) {
301 + rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG);
302 + /* 10 bits address */
303 + addr = 0x78 | ((pmsg->addr >> 8) & 0x03);
304 + rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK,
306 + rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK,
309 + rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS,
311 + /* 7 bits address */
312 + rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
316 + /* buffer length */
317 + if (pmsg->len == 0)
320 + rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
324 + if (pmsg->flags & I2C_M_RD) {
326 + /* start transfer */
328 + rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
331 + if ((ret = rt_i2c_wait_rx_done(i2c)))
335 + pmsg->buf[j] = rt_i2c_r32(i2c,
338 + } while (j < pmsg->len);
343 + rt_i2c_w32(i2c, pmsg->buf[j],
345 + /* start transfer */
348 + rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
351 + if ((ret = rt_i2c_wait_tx_done(i2c)))
354 + } while (j < pmsg->len);
357 + /* the return value is number of executed messages */
363 + rt_i2c_dump_reg(i2c);
368 +static u32 rt_i2c_func(struct i2c_adapter *a)
370 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
373 +static const struct i2c_algorithm rt_i2c_algo = {
374 + .master_xfer = rt_i2c_master_xfer,
375 + .functionality = rt_i2c_func,
378 +static const struct of_device_id i2c_rt_dt_ids[] = {
379 + { .compatible = "ralink,rt2880-i2c" },
383 +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
385 +static struct i2c_adapter_quirks rt_i2c_quirks = {
386 + .max_write_len = BYTECNT_MAX,
387 + .max_read_len = BYTECNT_MAX,
390 +static int rt_i2c_init(struct rt_i2c *i2c)
394 + /* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */
395 + i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) /
396 + (2 * i2c->cur_clk);
397 + if (i2c->clk_div < 8)
399 + if (i2c->clk_div > I2C_CLKDIV_MASK)
400 + i2c->clk_div = I2C_CLKDIV_MASK;
402 + /* check support combinde/repeated start message */
403 + rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG);
404 + reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD;
411 +static int rt_i2c_probe(struct platform_device *pdev)
413 + struct resource *res;
414 + struct rt_i2c *i2c;
415 + struct i2c_adapter *adap;
416 + const struct of_device_id *match;
419 + match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
421 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
423 + dev_err(&pdev->dev, "no memory resource found\n");
427 + i2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL);
429 + dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
433 + i2c->base = devm_ioremap_resource(&pdev->dev, res);
434 + if (IS_ERR(i2c->base))
435 + return PTR_ERR(i2c->base);
437 + i2c->clk = devm_clk_get(&pdev->dev, NULL);
438 + if (IS_ERR(i2c->clk)) {
439 + dev_err(&pdev->dev, "no clock defined\n");
442 + clk_prepare_enable(i2c->clk);
443 + i2c->dev = &pdev->dev;
445 + if (of_property_read_u32(pdev->dev.of_node,
446 + "clock-frequency", &i2c->cur_clk))
447 + i2c->cur_clk = 100000;
450 + adap->owner = THIS_MODULE;
451 + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
452 + adap->algo = &rt_i2c_algo;
454 + adap->dev.parent = &pdev->dev;
455 + i2c_set_adapdata(adap, i2c);
456 + adap->dev.of_node = pdev->dev.of_node;
457 + strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
458 + adap->quirks = &rt_i2c_quirks;
460 + platform_set_drvdata(pdev, i2c);
462 + restart = rt_i2c_init(i2c);
464 + ret = i2c_add_adapter(adap);
466 + dev_err(&pdev->dev, "failed to add adapter\n");
467 + clk_disable_unprepare(i2c->clk);
471 + dev_info(&pdev->dev, "clock %uKHz, re-start %ssupport\n",
472 + i2c->cur_clk/1000, restart ? "" : "not ");
477 +static int rt_i2c_remove(struct platform_device *pdev)
479 + struct rt_i2c *i2c = platform_get_drvdata(pdev);
481 + i2c_del_adapter(&i2c->adap);
482 + clk_disable_unprepare(i2c->clk);
487 +static struct platform_driver rt_i2c_driver = {
488 + .probe = rt_i2c_probe,
489 + .remove = rt_i2c_remove,
491 + .owner = THIS_MODULE,
492 + .name = "i2c-ralink",
493 + .of_match_table = i2c_rt_dt_ids,
497 +static int __init i2c_rt_init (void)
499 + return platform_driver_register(&rt_i2c_driver);
501 +subsys_initcall(i2c_rt_init);
503 +static void __exit i2c_rt_exit (void)
505 + platform_driver_unregister(&rt_i2c_driver);
507 +module_exit(i2c_rt_exit);
509 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
510 +MODULE_DESCRIPTION("Ralink I2c host driver");
511 +MODULE_LICENSE("GPL");
512 +MODULE_ALIAS("platform:Ralink-I2C");