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backport r6040 mainline fixes to 8.09
[openwrt/svn-archive/openwrt.git] / target / linux / rdc / files / drivers / net / r6040.c
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/mii.h>
41 #include <linux/ethtool.h>
42 #include <linux/crc32.h>
43 #include <linux/spinlock.h>
44 #include <linux/bitops.h>
45 #include <linux/io.h>
46 #include <linux/irq.h>
47 #include <linux/uaccess.h>
48
49 #include <asm/processor.h>
50
51 #define DRV_NAME "r6040"
52 #define DRV_VERSION "0.22"
53 #define DRV_RELDATE "25Mar2009"
54
55 /* PHY CHIP Address */
56 #define PHY1_ADDR 1 /* For MAC1 */
57 #define PHY2_ADDR 3 /* For MAC2 */
58 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
59 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
60
61 /* Time in jiffies before concluding the transmitter is hung. */
62 #define TX_TIMEOUT (6000 * HZ / 1000)
63
64 /* RDC MAC I/O Size */
65 #define R6040_IO_SIZE 256
66
67 /* MAX RDC MAC */
68 #define MAX_MAC 2
69
70 /* MAC registers */
71 #define MCR0 0x00 /* Control register 0 */
72 #define MCR1 0x04 /* Control register 1 */
73 #define MAC_RST 0x0001 /* Reset the MAC */
74 #define MBCR 0x08 /* Bus control */
75 #define MT_ICR 0x0C /* TX interrupt control */
76 #define MR_ICR 0x10 /* RX interrupt control */
77 #define MTPR 0x14 /* TX poll command register */
78 #define MR_BSR 0x18 /* RX buffer size */
79 #define MR_DCR 0x1A /* RX descriptor control */
80 #define MLSR 0x1C /* Last status */
81 #define MMDIO 0x20 /* MDIO control register */
82 #define MDIO_WRITE 0x4000 /* MDIO write */
83 #define MDIO_READ 0x2000 /* MDIO read */
84 #define MMRD 0x24 /* MDIO read data register */
85 #define MMWD 0x28 /* MDIO write data register */
86 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
87 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
88 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
89 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
90 #define MISR 0x3C /* Status register */
91 #define MIER 0x40 /* INT enable register */
92 #define MSK_INT 0x0000 /* Mask off interrupts */
93 #define RX_FINISH 0x0001 /* RX finished */
94 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
95 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
96 #define RX_EARLY 0x0008 /* RX early */
97 #define TX_FINISH 0x0010 /* TX finished */
98 #define TX_EARLY 0x0080 /* TX early */
99 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
100 #define LINK_CHANGED 0x0200 /* PHY link changed */
101 #define ME_CISR 0x44 /* Event counter INT status */
102 #define ME_CIER 0x48 /* Event counter INT enable */
103 #define MR_CNT 0x50 /* Successfully received packet counter */
104 #define ME_CNT0 0x52 /* Event counter 0 */
105 #define ME_CNT1 0x54 /* Event counter 1 */
106 #define ME_CNT2 0x56 /* Event counter 2 */
107 #define ME_CNT3 0x58 /* Event counter 3 */
108 #define MT_CNT 0x5A /* Successfully transmit packet counter */
109 #define ME_CNT4 0x5C /* Event counter 4 */
110 #define MP_CNT 0x5E /* Pause frame counter register */
111 #define MAR0 0x60 /* Hash table 0 */
112 #define MAR1 0x62 /* Hash table 1 */
113 #define MAR2 0x64 /* Hash table 2 */
114 #define MAR3 0x66 /* Hash table 3 */
115 #define MID_0L 0x68 /* Multicast address MID0 Low */
116 #define MID_0M 0x6A /* Multicast address MID0 Medium */
117 #define MID_0H 0x6C /* Multicast address MID0 High */
118 #define MID_1L 0x70 /* MID1 Low */
119 #define MID_1M 0x72 /* MID1 Medium */
120 #define MID_1H 0x74 /* MID1 High */
121 #define MID_2L 0x78 /* MID2 Low */
122 #define MID_2M 0x7A /* MID2 Medium */
123 #define MID_2H 0x7C /* MID2 High */
124 #define MID_3L 0x80 /* MID3 Low */
125 #define MID_3M 0x82 /* MID3 Medium */
126 #define MID_3H 0x84 /* MID3 High */
127 #define PHY_CC 0x88 /* PHY status change configuration register */
128 #define PHY_ST 0x8A /* PHY status register */
129 #define MAC_SM 0xAC /* MAC status machine */
130 #define MAC_ID 0xBE /* Identifier register */
131
132 #define TX_DCNT 0x80 /* TX descriptor count */
133 #define RX_DCNT 0x80 /* RX descriptor count */
134 #define MAX_BUF_SIZE 0x600
135 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
136 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
137 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
138 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
139
140 /* Descriptor status */
141 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
142 #define DSC_RX_OK 0x4000 /* RX was successful */
143 #define DSC_RX_ERR 0x0800 /* RX PHY error */
144 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
145 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
146 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
147 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
148 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
149 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
150 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
151 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
152 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
153 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
154
155 /* PHY settings */
156 #define ICPLUS_PHY_ID 0x0243
157
158 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
159 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
160 "Florian Fainelli <florian@openwrt.org>");
161 MODULE_LICENSE("GPL");
162 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
163 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
164
165 /* RX and TX interrupts that we handle */
166 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
167 #define TX_INTS (TX_FINISH)
168 #define INT_MASK (RX_INTS | TX_INTS)
169
170 struct r6040_descriptor {
171 u16 status, len; /* 0-3 */
172 __le32 buf; /* 4-7 */
173 __le32 ndesc; /* 8-B */
174 u32 rev1; /* C-F */
175 char *vbufp; /* 10-13 */
176 struct r6040_descriptor *vndescp; /* 14-17 */
177 struct sk_buff *skb_ptr; /* 18-1B */
178 u32 rev2; /* 1C-1F */
179 } __attribute__((aligned(32)));
180
181 struct r6040_private {
182 spinlock_t lock; /* driver lock */
183 struct timer_list timer;
184 struct pci_dev *pdev;
185 struct r6040_descriptor *rx_insert_ptr;
186 struct r6040_descriptor *rx_remove_ptr;
187 struct r6040_descriptor *tx_insert_ptr;
188 struct r6040_descriptor *tx_remove_ptr;
189 struct r6040_descriptor *rx_ring;
190 struct r6040_descriptor *tx_ring;
191 dma_addr_t rx_ring_dma;
192 dma_addr_t tx_ring_dma;
193 u16 tx_free_desc, phy_addr, phy_mode;
194 u16 mcr0, mcr1;
195 u16 switch_sig;
196 struct net_device *dev;
197 struct mii_if_info mii_if;
198 struct napi_struct napi;
199 void __iomem *base;
200 };
201
202 static char version[] __devinitdata = KERN_INFO DRV_NAME
203 ": RDC R6040 NAPI net driver,"
204 "version "DRV_VERSION " (" DRV_RELDATE ")";
205
206 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
207
208 /* Read a word data from PHY Chip */
209 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
210 {
211 int limit = 2048;
212 u16 cmd;
213
214 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
215 /* Wait for the read bit to be cleared */
216 while (limit--) {
217 cmd = ioread16(ioaddr + MMDIO);
218 if (!(cmd & MDIO_READ))
219 break;
220 }
221
222 return ioread16(ioaddr + MMRD);
223 }
224
225 /* Write a word data from PHY Chip */
226 static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
227 {
228 int limit = 2048;
229 u16 cmd;
230
231 iowrite16(val, ioaddr + MMWD);
232 /* Write the command to the MDIO bus */
233 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
234 /* Wait for the write bit to be cleared */
235 while (limit--) {
236 cmd = ioread16(ioaddr + MMDIO);
237 if (!(cmd & MDIO_WRITE))
238 break;
239 }
240 }
241
242 static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
243 {
244 struct r6040_private *lp = netdev_priv(dev);
245 void __iomem *ioaddr = lp->base;
246
247 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
248 }
249
250 static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
251 {
252 struct r6040_private *lp = netdev_priv(dev);
253 void __iomem *ioaddr = lp->base;
254
255 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
256 }
257
258 static void r6040_free_txbufs(struct net_device *dev)
259 {
260 struct r6040_private *lp = netdev_priv(dev);
261 int i;
262
263 for (i = 0; i < TX_DCNT; i++) {
264 if (lp->tx_insert_ptr->skb_ptr) {
265 pci_unmap_single(lp->pdev,
266 le32_to_cpu(lp->tx_insert_ptr->buf),
267 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
268 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
269 lp->tx_insert_ptr->skb_ptr = NULL;
270 }
271 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
272 }
273 }
274
275 static void r6040_free_rxbufs(struct net_device *dev)
276 {
277 struct r6040_private *lp = netdev_priv(dev);
278 int i;
279
280 for (i = 0; i < RX_DCNT; i++) {
281 if (lp->rx_insert_ptr->skb_ptr) {
282 pci_unmap_single(lp->pdev,
283 le32_to_cpu(lp->rx_insert_ptr->buf),
284 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
285 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
286 lp->rx_insert_ptr->skb_ptr = NULL;
287 }
288 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
289 }
290 }
291
292 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
293 dma_addr_t desc_dma, int size)
294 {
295 struct r6040_descriptor *desc = desc_ring;
296 dma_addr_t mapping = desc_dma;
297
298 while (size-- > 0) {
299 mapping += sizeof(*desc);
300 desc->ndesc = cpu_to_le32(mapping);
301 desc->vndescp = desc + 1;
302 desc++;
303 }
304 desc--;
305 desc->ndesc = cpu_to_le32(desc_dma);
306 desc->vndescp = desc_ring;
307 }
308
309 static void r6040_init_txbufs(struct net_device *dev)
310 {
311 struct r6040_private *lp = netdev_priv(dev);
312
313 lp->tx_free_desc = TX_DCNT;
314
315 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
316 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
317 }
318
319 static int r6040_alloc_rxbufs(struct net_device *dev)
320 {
321 struct r6040_private *lp = netdev_priv(dev);
322 struct r6040_descriptor *desc;
323 struct sk_buff *skb;
324 int rc;
325
326 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
327 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
328
329 /* Allocate skbs for the rx descriptors */
330 desc = lp->rx_ring;
331 do {
332 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
333 if (!skb) {
334 printk(KERN_ERR DRV_NAME "%s: failed to alloc skb for rx\n", dev->name);
335 rc = -ENOMEM;
336 goto err_exit;
337 }
338 desc->skb_ptr = skb;
339 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
340 desc->skb_ptr->data,
341 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
342 desc->status = DSC_OWNER_MAC;
343 desc = desc->vndescp;
344 } while (desc != lp->rx_ring);
345
346 return 0;
347
348 err_exit:
349 /* Deallocate all previously allocated skbs */
350 r6040_free_rxbufs(dev);
351 return rc;
352 }
353
354 static void r6040_init_mac_regs(struct net_device *dev)
355 {
356 struct r6040_private *lp = netdev_priv(dev);
357 void __iomem *ioaddr = lp->base;
358 int limit = 2048;
359 u16 cmd;
360
361 /* Mask Off Interrupt */
362 iowrite16(MSK_INT, ioaddr + MIER);
363
364 /* Reset RDC MAC */
365 iowrite16(MAC_RST, ioaddr + MCR1);
366 while (limit--) {
367 cmd = ioread16(ioaddr + MCR1);
368 if (cmd & 0x1)
369 break;
370 }
371 /* Reset internal state machine */
372 iowrite16(2, ioaddr + MAC_SM);
373 iowrite16(0, ioaddr + MAC_SM);
374 mdelay(5);
375
376 /* MAC Bus Control Register */
377 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
378
379 /* Buffer Size Register */
380 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
381
382 /* Write TX ring start address */
383 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
384 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
385
386 /* Write RX ring start address */
387 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
388 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
389
390 /* Set interrupt waiting time and packet numbers */
391 iowrite16(0, ioaddr + MT_ICR);
392 iowrite16(0, ioaddr + MR_ICR);
393
394 /* Enable interrupts */
395 iowrite16(INT_MASK, ioaddr + MIER);
396
397 /* Enable TX and RX */
398 iowrite16(lp->mcr0 | 0x0002, ioaddr);
399
400 /* Let TX poll the descriptors
401 * we may got called by r6040_tx_timeout which has left
402 * some unsent tx buffers */
403 iowrite16(0x01, ioaddr + MTPR);
404 }
405
406 static void r6040_tx_timeout(struct net_device *dev)
407 {
408 struct r6040_private *priv = netdev_priv(dev);
409 void __iomem *ioaddr = priv->base;
410
411 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
412 "status %4.4x, PHY status %4.4x\n",
413 dev->name, ioread16(ioaddr + MIER),
414 ioread16(ioaddr + MISR),
415 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
416
417 dev->stats.tx_errors++;
418
419 /* Reset MAC and re-init all registers */
420 r6040_init_mac_regs(dev);
421 }
422
423 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
424 {
425 struct r6040_private *priv = netdev_priv(dev);
426 void __iomem *ioaddr = priv->base;
427 unsigned long flags;
428
429 spin_lock_irqsave(&priv->lock, flags);
430 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
431 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
432 spin_unlock_irqrestore(&priv->lock, flags);
433
434 return &dev->stats;
435 }
436
437 /* Stop RDC MAC and Free the allocated resource */
438 static void r6040_down(struct net_device *dev)
439 {
440 struct r6040_private *lp = netdev_priv(dev);
441 void __iomem *ioaddr = lp->base;
442 int limit = 2048;
443 u16 *adrp;
444 u16 cmd;
445
446 /* Stop MAC */
447 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
448 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
449 while (limit--) {
450 cmd = ioread16(ioaddr + MCR1);
451 if (cmd & 0x1)
452 break;
453 }
454
455 /* Restore MAC Address to MIDx */
456 adrp = (u16 *) dev->dev_addr;
457 iowrite16(adrp[0], ioaddr + MID_0L);
458 iowrite16(adrp[1], ioaddr + MID_0M);
459 iowrite16(adrp[2], ioaddr + MID_0H);
460 }
461
462 static int r6040_close(struct net_device *dev)
463 {
464 struct r6040_private *lp = netdev_priv(dev);
465 struct pci_dev *pdev = lp->pdev;
466
467 /* deleted timer */
468 del_timer_sync(&lp->timer);
469
470 spin_lock_irq(&lp->lock);
471 napi_disable(&lp->napi);
472 netif_stop_queue(dev);
473 r6040_down(dev);
474
475 free_irq(dev->irq, dev);
476
477 /* Free RX buffer */
478 r6040_free_rxbufs(dev);
479
480 /* Free TX buffer */
481 r6040_free_txbufs(dev);
482
483 spin_unlock_irq(&lp->lock);
484
485 /* Free Descriptor memory */
486 if (lp->rx_ring) {
487 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
488 lp->rx_ring = NULL;
489 }
490
491 if (lp->tx_ring) {
492 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
493 lp->tx_ring = NULL;
494 }
495
496 return 0;
497 }
498
499 /* Status of PHY CHIP */
500 static int r6040_phy_mode_chk(struct net_device *dev)
501 {
502 struct r6040_private *lp = netdev_priv(dev);
503 void __iomem *ioaddr = lp->base;
504 int phy_dat;
505
506 /* PHY Link Status Check */
507 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
508 if (!(phy_dat & 0x4))
509 phy_dat = 0x8000; /* Link Failed, full duplex */
510
511 /* PHY Chip Auto-Negotiation Status */
512 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
513 if (phy_dat & 0x0020) {
514 /* Auto Negotiation Mode */
515 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
516 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
517 if (phy_dat & 0x140)
518 /* Force full duplex */
519 phy_dat = 0x8000;
520 else
521 phy_dat = 0;
522 } else {
523 /* Force Mode */
524 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
525 if (phy_dat & 0x100)
526 phy_dat = 0x8000;
527 else
528 phy_dat = 0x0000;
529 }
530
531 mii_check_media(&lp->mii_if, 1, 1);
532
533 return phy_dat;
534 };
535
536 static void r6040_set_carrier(struct mii_if_info *mii)
537 {
538 if (r6040_phy_mode_chk(mii->dev)) {
539 /* autoneg is off: Link is always assumed to be up */
540 if (!netif_carrier_ok(mii->dev))
541 netif_carrier_on(mii->dev);
542 } else
543 r6040_phy_mode_chk(mii->dev);
544 }
545
546 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
547 {
548 struct r6040_private *lp = netdev_priv(dev);
549 struct mii_ioctl_data *data = if_mii(rq);
550 int rc;
551
552 if (!netif_running(dev))
553 return -EINVAL;
554 spin_lock_irq(&lp->lock);
555 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
556 spin_unlock_irq(&lp->lock);
557 r6040_set_carrier(&lp->mii_if);
558 return rc;
559 }
560
561 static int r6040_rx(struct net_device *dev, int limit)
562 {
563 struct r6040_private *priv = netdev_priv(dev);
564 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
565 struct sk_buff *skb_ptr, *new_skb;
566 int count = 0;
567 u16 err;
568
569 /* Limit not reached and the descriptor belongs to the CPU */
570 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
571 /* Read the descriptor status */
572 err = descptr->status;
573 /* Global error status set */
574 if (err & DSC_RX_ERR) {
575 /* RX dribble */
576 if (err & DSC_RX_ERR_DRI)
577 dev->stats.rx_frame_errors++;
578 /* Buffer lenght exceeded */
579 if (err & DSC_RX_ERR_BUF)
580 dev->stats.rx_length_errors++;
581 /* Packet too long */
582 if (err & DSC_RX_ERR_LONG)
583 dev->stats.rx_length_errors++;
584 /* Packet < 64 bytes */
585 if (err & DSC_RX_ERR_RUNT)
586 dev->stats.rx_length_errors++;
587 /* CRC error */
588 if (err & DSC_RX_ERR_CRC) {
589 spin_lock(&priv->lock);
590 dev->stats.rx_crc_errors++;
591 spin_unlock(&priv->lock);
592 }
593 goto next_descr;
594 }
595
596 /* Packet successfully received */
597 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
598 if (!new_skb) {
599 dev->stats.rx_dropped++;
600 goto next_descr;
601 }
602 skb_ptr = descptr->skb_ptr;
603 skb_ptr->dev = priv->dev;
604
605 /* Do not count the CRC */
606 skb_put(skb_ptr, descptr->len - 4);
607 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
608 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
609 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
610
611 /* Send to upper layer */
612 netif_receive_skb(skb_ptr);
613 dev->stats.rx_packets++;
614 dev->stats.rx_bytes += descptr->len - 4;
615
616 /* put new skb into descriptor */
617 descptr->skb_ptr = new_skb;
618 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
619 descptr->skb_ptr->data,
620 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
621
622 next_descr:
623 /* put the descriptor back to the MAC */
624 descptr->status = DSC_OWNER_MAC;
625 descptr = descptr->vndescp;
626 count++;
627 }
628 priv->rx_remove_ptr = descptr;
629
630 return count;
631 }
632
633 static void r6040_tx(struct net_device *dev)
634 {
635 struct r6040_private *priv = netdev_priv(dev);
636 struct r6040_descriptor *descptr;
637 void __iomem *ioaddr = priv->base;
638 struct sk_buff *skb_ptr;
639 u16 err;
640
641 spin_lock(&priv->lock);
642 descptr = priv->tx_remove_ptr;
643 while (priv->tx_free_desc < TX_DCNT) {
644 /* Check for errors */
645 err = ioread16(ioaddr + MLSR);
646
647 if (err & 0x0200)
648 dev->stats.rx_fifo_errors++;
649 if (err & (0x2000 | 0x4000))
650 dev->stats.tx_carrier_errors++;
651
652 if (descptr->status & DSC_OWNER_MAC)
653 break; /* Not complete */
654 skb_ptr = descptr->skb_ptr;
655 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
656 skb_ptr->len, PCI_DMA_TODEVICE);
657 /* Free buffer */
658 dev_kfree_skb_irq(skb_ptr);
659 descptr->skb_ptr = NULL;
660 /* To next descriptor */
661 descptr = descptr->vndescp;
662 priv->tx_free_desc++;
663 }
664 priv->tx_remove_ptr = descptr;
665
666 if (priv->tx_free_desc)
667 netif_wake_queue(dev);
668 spin_unlock(&priv->lock);
669 }
670
671 static int r6040_poll(struct napi_struct *napi, int budget)
672 {
673 struct r6040_private *priv =
674 container_of(napi, struct r6040_private, napi);
675 struct net_device *dev = priv->dev;
676 void __iomem *ioaddr = priv->base;
677 int work_done;
678
679 work_done = r6040_rx(dev, budget);
680
681 if (work_done < budget) {
682 napi_complete(napi);
683 /* Enable RX interrupt */
684 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
685 }
686 return work_done;
687 }
688
689 /* The RDC interrupt handler. */
690 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
691 {
692 struct net_device *dev = dev_id;
693 struct r6040_private *lp = netdev_priv(dev);
694 void __iomem *ioaddr = lp->base;
695 u16 misr, status;
696
697 /* Save MIER */
698 misr = ioread16(ioaddr + MIER);
699 /* Mask off RDC MAC interrupt */
700 iowrite16(MSK_INT, ioaddr + MIER);
701 /* Read MISR status and clear */
702 status = ioread16(ioaddr + MISR);
703
704 if (status == 0x0000 || status == 0xffff)
705 return IRQ_NONE;
706
707 /* RX interrupt request */
708 if (status & RX_INTS) {
709 if (status & RX_NO_DESC) {
710 /* RX descriptor unavailable */
711 dev->stats.rx_dropped++;
712 dev->stats.rx_missed_errors++;
713 }
714 if (status & RX_FIFO_FULL)
715 dev->stats.rx_fifo_errors++;
716
717 /* Mask off RX interrupt */
718 misr &= ~RX_INTS;
719 napi_schedule(&lp->napi);
720 }
721
722 /* TX interrupt request */
723 if (status & TX_INTS)
724 r6040_tx(dev);
725
726 /* Restore RDC MAC interrupt */
727 iowrite16(misr, ioaddr + MIER);
728
729 return IRQ_HANDLED;
730 }
731
732 #ifdef CONFIG_NET_POLL_CONTROLLER
733 static void r6040_poll_controller(struct net_device *dev)
734 {
735 disable_irq(dev->irq);
736 r6040_interrupt(dev->irq, dev);
737 enable_irq(dev->irq);
738 }
739 #endif
740
741 /* Init RDC MAC */
742 static int r6040_up(struct net_device *dev)
743 {
744 struct r6040_private *lp = netdev_priv(dev);
745 void __iomem *ioaddr = lp->base;
746 int ret;
747
748 /* Initialise and alloc RX/TX buffers */
749 r6040_init_txbufs(dev);
750 ret = r6040_alloc_rxbufs(dev);
751 if (ret)
752 return ret;
753
754 /* Read the PHY ID */
755 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
756
757 if (lp->switch_sig == ICPLUS_PHY_ID) {
758 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
759 lp->phy_mode = 0x8000;
760 } else {
761 /* PHY Mode Check */
762 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
763 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
764
765 if (PHY_MODE == 0x3100)
766 lp->phy_mode = r6040_phy_mode_chk(dev);
767 else
768 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
769 }
770
771 /* Set duplex mode */
772 lp->mcr0 |= lp->phy_mode;
773
774 /* improve performance (by RDC guys) */
775 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
776 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
777 r6040_phy_write(ioaddr, 0, 19, 0x0000);
778 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
779
780 /* Initialize all MAC registers */
781 r6040_init_mac_regs(dev);
782
783 return 0;
784 }
785
786 /*
787 A periodic timer routine
788 Polling PHY Chip Link Status
789 */
790 static void r6040_timer(unsigned long data)
791 {
792 struct net_device *dev = (struct net_device *)data;
793 struct r6040_private *lp = netdev_priv(dev);
794 void __iomem *ioaddr = lp->base;
795 u16 phy_mode;
796
797 /* Polling PHY Chip Status */
798 if (PHY_MODE == 0x3100)
799 phy_mode = r6040_phy_mode_chk(dev);
800 else
801 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
802
803 if (phy_mode != lp->phy_mode) {
804 lp->phy_mode = phy_mode;
805 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
806 iowrite16(lp->mcr0, ioaddr);
807 //printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
808 }
809
810 /* Timer active again */
811 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
812 }
813
814 /* Read/set MAC address routines */
815 static void r6040_mac_address(struct net_device *dev)
816 {
817 struct r6040_private *lp = netdev_priv(dev);
818 void __iomem *ioaddr = lp->base;
819 u16 *adrp;
820
821 /* MAC operation register */
822 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
823 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
824 iowrite16(0, ioaddr + MAC_SM);
825 mdelay(5);
826
827 /* Restore MAC Address */
828 adrp = (u16 *) dev->dev_addr;
829 iowrite16(adrp[0], ioaddr + MID_0L);
830 iowrite16(adrp[1], ioaddr + MID_0M);
831 iowrite16(adrp[2], ioaddr + MID_0H);
832 }
833
834 static int r6040_open(struct net_device *dev)
835 {
836 struct r6040_private *lp = netdev_priv(dev);
837 int ret;
838
839 /* Request IRQ and Register interrupt handler */
840 ret = request_irq(dev->irq, &r6040_interrupt,
841 IRQF_SHARED, dev->name, dev);
842 if (ret)
843 return ret;
844
845 /* Set MAC address */
846 r6040_mac_address(dev);
847
848 /* Allocate Descriptor memory */
849 lp->rx_ring =
850 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
851 if (!lp->rx_ring)
852 return -ENOMEM;
853
854 lp->tx_ring =
855 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
856 if (!lp->tx_ring) {
857 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
858 lp->rx_ring_dma);
859 return -ENOMEM;
860 }
861
862 ret = r6040_up(dev);
863 if (ret) {
864 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
865 lp->tx_ring_dma);
866 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
867 lp->rx_ring_dma);
868 return ret;
869 }
870
871 napi_enable(&lp->napi);
872 netif_start_queue(dev);
873
874 /* set and active a timer process */
875 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
876 if (lp->switch_sig != ICPLUS_PHY_ID)
877 mod_timer(&lp->timer, jiffies + HZ);
878 return 0;
879 }
880
881 static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
882 {
883 struct r6040_private *lp = netdev_priv(dev);
884 struct r6040_descriptor *descptr;
885 void __iomem *ioaddr = lp->base;
886 unsigned long flags;
887 int ret = NETDEV_TX_OK;
888
889 /* Critical Section */
890 spin_lock_irqsave(&lp->lock, flags);
891
892 /* TX resource check */
893 if (!lp->tx_free_desc) {
894 spin_unlock_irqrestore(&lp->lock, flags);
895 netif_stop_queue(dev);
896 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
897 ret = NETDEV_TX_BUSY;
898 return ret;
899 }
900
901 /* Statistic Counter */
902 dev->stats.tx_packets++;
903 dev->stats.tx_bytes += skb->len;
904 /* Set TX descriptor & Transmit it */
905 lp->tx_free_desc--;
906 descptr = lp->tx_insert_ptr;
907 if (skb->len < MISR)
908 descptr->len = MISR;
909 else
910 descptr->len = skb->len;
911
912 descptr->skb_ptr = skb;
913 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
914 skb->data, skb->len, PCI_DMA_TODEVICE));
915 descptr->status = DSC_OWNER_MAC;
916 /* Trigger the MAC to check the TX descriptor */
917 iowrite16(0x01, ioaddr + MTPR);
918 lp->tx_insert_ptr = descptr->vndescp;
919
920 /* If no tx resource, stop */
921 if (!lp->tx_free_desc)
922 netif_stop_queue(dev);
923
924 dev->trans_start = jiffies;
925 spin_unlock_irqrestore(&lp->lock, flags);
926 return ret;
927 }
928
929 static void r6040_multicast_list(struct net_device *dev)
930 {
931 struct r6040_private *lp = netdev_priv(dev);
932 void __iomem *ioaddr = lp->base;
933 u16 *adrp;
934 u16 reg;
935 unsigned long flags;
936 struct dev_mc_list *dmi = dev->mc_list;
937 int i;
938
939 /* MAC Address */
940 adrp = (u16 *)dev->dev_addr;
941 iowrite16(adrp[0], ioaddr + MID_0L);
942 iowrite16(adrp[1], ioaddr + MID_0M);
943 iowrite16(adrp[2], ioaddr + MID_0H);
944
945 /* Promiscous Mode */
946 spin_lock_irqsave(&lp->lock, flags);
947
948 /* Clear AMCP & PROM bits */
949 reg = ioread16(ioaddr) & ~0x0120;
950 if (dev->flags & IFF_PROMISC) {
951 reg |= 0x0020;
952 lp->mcr0 |= 0x0020;
953 }
954 /* Too many multicast addresses
955 * accept all traffic */
956 else if ((dev->mc_count > MCAST_MAX)
957 || (dev->flags & IFF_ALLMULTI))
958 reg |= 0x0020;
959
960 iowrite16(reg, ioaddr);
961 spin_unlock_irqrestore(&lp->lock, flags);
962
963 /* Build the hash table */
964 if (dev->mc_count > MCAST_MAX) {
965 u16 hash_table[4];
966 u32 crc;
967
968 for (i = 0; i < 4; i++)
969 hash_table[i] = 0;
970
971 for (i = 0; i < dev->mc_count; i++) {
972 char *addrs = dmi->dmi_addr;
973
974 dmi = dmi->next;
975
976 if (!(*addrs & 1))
977 continue;
978
979 crc = ether_crc_le(6, addrs);
980 crc >>= 26;
981 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
982 }
983 /* Write the index of the hash table */
984 for (i = 0; i < 4; i++)
985 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
986 /* Fill the MAC hash tables with their values */
987 iowrite16(hash_table[0], ioaddr + MAR0);
988 iowrite16(hash_table[1], ioaddr + MAR1);
989 iowrite16(hash_table[2], ioaddr + MAR2);
990 iowrite16(hash_table[3], ioaddr + MAR3);
991 }
992 /* Multicast Address 1~4 case */
993 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
994 adrp = (u16 *)dmi->dmi_addr;
995 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
996 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
997 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
998 dmi = dmi->next;
999 }
1000 for (i = dev->mc_count; i < MCAST_MAX; i++) {
1001 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
1002 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
1003 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
1004 }
1005 }
1006
1007 static void netdev_get_drvinfo(struct net_device *dev,
1008 struct ethtool_drvinfo *info)
1009 {
1010 struct r6040_private *rp = netdev_priv(dev);
1011
1012 strcpy(info->driver, DRV_NAME);
1013 strcpy(info->version, DRV_VERSION);
1014 strcpy(info->bus_info, pci_name(rp->pdev));
1015 }
1016
1017 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1018 {
1019 struct r6040_private *rp = netdev_priv(dev);
1020 int rc;
1021
1022 spin_lock_irq(&rp->lock);
1023 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1024 spin_unlock_irq(&rp->lock);
1025
1026 return rc;
1027 }
1028
1029 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1030 {
1031 struct r6040_private *rp = netdev_priv(dev);
1032 int rc;
1033
1034 spin_lock_irq(&rp->lock);
1035 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1036 spin_unlock_irq(&rp->lock);
1037 r6040_set_carrier(&rp->mii_if);
1038
1039 return rc;
1040 }
1041
1042 static u32 netdev_get_link(struct net_device *dev)
1043 {
1044 struct r6040_private *rp = netdev_priv(dev);
1045
1046 return mii_link_ok(&rp->mii_if);
1047 }
1048
1049 static struct ethtool_ops netdev_ethtool_ops = {
1050 .get_drvinfo = netdev_get_drvinfo,
1051 .get_settings = netdev_get_settings,
1052 .set_settings = netdev_set_settings,
1053 .get_link = netdev_get_link,
1054 };
1055
1056 static int __devinit r6040_init_one(struct pci_dev *pdev,
1057 const struct pci_device_id *ent)
1058 {
1059 struct net_device *dev;
1060 struct r6040_private *lp;
1061 void __iomem *ioaddr;
1062 int err, io_size = R6040_IO_SIZE;
1063 static int card_idx = -1;
1064 int bar = 0;
1065 long pioaddr;
1066 u16 *adrp;
1067
1068 printk(KERN_INFO "%s\n", version);
1069
1070 err = pci_enable_device(pdev);
1071 if (err)
1072 goto err_out;
1073
1074 /* this should always be supported */
1075 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1076 if (err) {
1077 printk(KERN_ERR DRV_NAME ": 32-bit PCI DMA addresses"
1078 "not supported by the card\n");
1079 goto err_out;
1080 }
1081 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1082 if (err) {
1083 printk(KERN_ERR DRV_NAME ": 32-bit PCI DMA addresses"
1084 "not supported by the card\n");
1085 goto err_out;
1086 }
1087
1088 /* IO Size check */
1089 if (pci_resource_len(pdev, 0) < io_size) {
1090 printk(KERN_ERR DRV_NAME ": Insufficient PCI resources, aborting\n");
1091 err = -EIO;
1092 goto err_out;
1093 }
1094
1095 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1096 pci_set_master(pdev);
1097
1098 dev = alloc_etherdev(sizeof(struct r6040_private));
1099 if (!dev) {
1100 printk(KERN_ERR DRV_NAME ": Failed to allocate etherdev\n");
1101 err = -ENOMEM;
1102 goto err_out;
1103 }
1104 SET_NETDEV_DEV(dev, &pdev->dev);
1105 lp = netdev_priv(dev);
1106
1107 err = pci_request_regions(pdev, DRV_NAME);
1108
1109 if (err) {
1110 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1111 goto err_out_free_dev;
1112 }
1113
1114 ioaddr = pci_iomap(pdev, bar, io_size);
1115 if (!ioaddr) {
1116 printk(KERN_ERR DRV_NAME ": ioremap failed for device %s\n",
1117 pci_name(pdev));
1118 err = -EIO;
1119 goto err_out_free_res;
1120 }
1121 /* If PHY status change register is still set to zero it means the
1122 * bootloader didn't initialize it */
1123 if (ioread16(ioaddr + PHY_CC) == 0)
1124 iowrite16(0x9f07, ioaddr + PHY_CC);
1125
1126 /* Init system & device */
1127 lp->base = ioaddr;
1128 dev->irq = pdev->irq;
1129
1130 spin_lock_init(&lp->lock);
1131 pci_set_drvdata(pdev, dev);
1132
1133 /* Set MAC address */
1134 card_idx++;
1135
1136 adrp = (u16 *)dev->dev_addr;
1137 adrp[0] = ioread16(ioaddr + MID_0L);
1138 adrp[1] = ioread16(ioaddr + MID_0M);
1139 adrp[2] = ioread16(ioaddr + MID_0H);
1140
1141 /* Some bootloader/BIOSes do not initialize
1142 * MAC address, warn about that */
1143 if (!(adrp[0] || adrp[1] || adrp[2])) {
1144 printk(KERN_WARNING DRV_NAME ": MAC address not initialized, generating random\n");
1145 random_ether_addr(dev->dev_addr);
1146 }
1147
1148 /* Link new device into r6040_root_dev */
1149 lp->pdev = pdev;
1150 lp->dev = dev;
1151
1152 /* Init RDC private data */
1153 lp->mcr0 = 0x1002;
1154 lp->phy_addr = phy_table[card_idx];
1155 lp->switch_sig = 0;
1156
1157 /* The RDC-specific entries in the device structure. */
1158 dev->open = &r6040_open;
1159 dev->hard_start_xmit = &r6040_start_xmit;
1160 dev->stop = &r6040_close;
1161 dev->get_stats = r6040_get_stats;
1162 dev->set_multicast_list = &r6040_multicast_list;
1163 dev->do_ioctl = &r6040_ioctl;
1164 dev->ethtool_ops = &netdev_ethtool_ops;
1165 dev->tx_timeout = &r6040_tx_timeout;
1166 dev->watchdog_timeo = TX_TIMEOUT;
1167 #ifdef CONFIG_NET_POLL_CONTROLLER
1168 dev->poll_controller = r6040_poll_controller;
1169 #endif
1170 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1171 lp->mii_if.dev = dev;
1172 lp->mii_if.mdio_read = r6040_mdio_read;
1173 lp->mii_if.mdio_write = r6040_mdio_write;
1174 lp->mii_if.phy_id = lp->phy_addr;
1175 lp->mii_if.phy_id_mask = 0x1f;
1176 lp->mii_if.reg_num_mask = 0x1f;
1177
1178 /* Register net device. After this dev->name assign */
1179 err = register_netdev(dev);
1180 if (err) {
1181 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1182 goto err_out_unmap;
1183 }
1184 return 0;
1185
1186 err_out_unmap:
1187 pci_iounmap(pdev, ioaddr);
1188 err_out_free_res:
1189 pci_release_regions(pdev);
1190 err_out_free_dev:
1191 free_netdev(dev);
1192 err_out:
1193 return err;
1194 }
1195
1196 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1197 {
1198 struct net_device *dev = pci_get_drvdata(pdev);
1199
1200 unregister_netdev(dev);
1201 pci_release_regions(pdev);
1202 free_netdev(dev);
1203 pci_disable_device(pdev);
1204 pci_set_drvdata(pdev, NULL);
1205 }
1206
1207
1208 static struct pci_device_id r6040_pci_tbl[] = {
1209 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1210 { 0 }
1211 };
1212 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1213
1214 static struct pci_driver r6040_driver = {
1215 .name = DRV_NAME,
1216 .id_table = r6040_pci_tbl,
1217 .probe = r6040_init_one,
1218 .remove = __devexit_p(r6040_remove_one),
1219 };
1220
1221
1222 static int __init r6040_init(void)
1223 {
1224 return pci_register_driver(&r6040_driver);
1225 }
1226
1227
1228 static void __exit r6040_cleanup(void)
1229 {
1230 pci_unregister_driver(&r6040_driver);
1231 }
1232
1233 module_init(r6040_init);
1234 module_exit(r6040_cleanup);
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