realtek: copy dts directory for Kernel 5.10
[openwrt/staging/dedeckeh.git] / target / linux / realtek / dts-5.10 / rtl8380_zyxel_gs1900.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include "rtl838x.dtsi"
4
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
7
8 / {
9 aliases {
10 led-boot = &led_sys;
11 led-failsafe = &led_sys;
12 led-running = &led_sys;
13 led-upgrade = &led_sys;
14 };
15
16 chosen {
17 bootargs = "console=ttyS0,115200";
18 };
19
20 memory@0 {
21 device_type = "memory";
22 reg = <0x0 0x8000000>;
23 };
24
25 gpio1: rtl8231-gpio {
26 status = "okay";
27
28 poe_enable {
29 gpio-hog;
30 gpios = <13 0>;
31 output-high;
32 };
33 };
34
35 keys {
36 compatible = "gpio-keys-polled";
37 poll-interval = <20>;
38
39 reset {
40 label = "reset";
41 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_RESTART>;
43 };
44 };
45
46 leds {
47 compatible = "gpio-leds";
48
49 led_sys: sys {
50 label = "green:sys";
51 gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>;
52 };
53 };
54 };
55
56 &spi0 {
57 status = "okay";
58
59 flash@0 {
60 compatible = "jedec,spi-nor";
61 reg = <0>;
62 spi-max-frequency = <10000000>;
63
64 partitions {
65 compatible = "fixed-partitions";
66 #address-cells = <1>;
67 #size-cells = <1>;
68
69 partition@0 {
70 label = "u-boot";
71 reg = <0x0 0x40000>;
72 read-only;
73 };
74 partition@40000 {
75 label = "u-boot-env";
76 reg = <0x40000 0x10000>;
77 read-only;
78 };
79 partition@50000 {
80 label = "u-boot-env2";
81 reg = <0x50000 0x10000>;
82 };
83 partition@60000 {
84 label = "jffs";
85 reg = <0x60000 0x100000>;
86 };
87 partition@160000 {
88 label = "jffs2";
89 reg = <0x160000 0x100000>;
90 };
91 partition@b260000 {
92 label = "firmware";
93 reg = <0x260000 0x6d0000>;
94 compatible = "openwrt,uimage", "denx,uimage";
95 openwrt,ih-magic = <0x83800000>;
96 };
97 partition@930000 {
98 label = "runtime2";
99 reg = <0x930000 0x6d0000>;
100 };
101 };
102 };
103 };
104
105 &ethernet0 {
106 mdio: mdio-bus {
107 compatible = "realtek,rtl838x-mdio";
108 regmap = <&ethernet0>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111
112 INTERNAL_PHY(8)
113 INTERNAL_PHY(9)
114 INTERNAL_PHY(10)
115 INTERNAL_PHY(11)
116 INTERNAL_PHY(12)
117 INTERNAL_PHY(13)
118 INTERNAL_PHY(14)
119 INTERNAL_PHY(15)
120 };
121 };
122
123 &switch0 {
124 ports {
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 SWITCH_PORT(8, 1, internal)
129 SWITCH_PORT(9, 2, internal)
130 SWITCH_PORT(10, 3, internal)
131 SWITCH_PORT(11, 4, internal)
132 SWITCH_PORT(12, 5, internal)
133 SWITCH_PORT(13, 6, internal)
134 SWITCH_PORT(14, 7, internal)
135 SWITCH_PORT(15, 8, internal)
136
137 port@28 {
138 ethernet = <&ethernet0>;
139 reg = <28>;
140 phy-mode = "internal";
141
142 fixed-link {
143 speed = <1000>;
144 full-duplex;
145 };
146 };
147 };
148 };