target/linux/realtek/dts-5.10/rtl8382_inaba_aml2-17gp.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "rtl838x.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
  10         model = "INABA Abaniact AML2-17GP";
  11
  12         memory@0 {
  13                 device_type = "memory";
  14                 reg = <0x0 0x8000000>;
  15         };
  16
  17         keys {
  18                 compatible = "gpio-keys";
  19
  20                 reset {
  21                         label = "reset";
  22                         gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
  23                         linux,code = <KEY_RESTART>;
  24                 };
  25         };
  26 };
  27
  28 &spi0 {
  29         status = "okay";
  30
  31         flash@0 {
  32                 compatible = "jedec,spi-nor";
  33                 reg = <0>;
  34                 spi-max-frequency = <10000000>;
  35
  36                 partitions {
  37                         compatible = "fixed-partitions";
  38                         #address-cells = <1>;
  39                         #size-cells = <1>;
  40
  41                         partition@0 {
  42                                 label = "u-boot";
  43                                 reg = <0x0 0x80000>;
  44                                 read-only;
  45                         };
  46
  47                         partition@80000 {
  48                                 label = "u-boot-env";
  49                                 reg = <0x80000 0x10000>;
  50                                 read-only;
  51                         };
  52
  53                         partition@90000 {
  54                                 label = "u-boot-env2";
  55                                 reg = <0x90000 0x10000>;
  56                         };
  57
  58                         partition@a0000 {
  59                                 label = "jffs2_cfg";
  60                                 reg = <0xa0000 0x400000>;
  61                                 read-only;
  62                         };
  63
  64                         partition@4a0000 {
  65                                 label = "jffs2_log";
  66                                 reg = <0x4a0000 0x100000>;
  67                                 read-only;
  68                         };
  69
  70                         partition@5a0000 {
  71                                 compatible = "openwrt,uimage", "denx,uimage";
  72                                 label = "firmware";
  73                                 reg = <0x5a0000 0xd30000>;
  74                                 openwrt,ih-magic = <0x83800000>;
  75                         };
  76
  77                         partition@12d0000 {
  78                                 label = "runtime2";
  79                                 reg = <0x12d0000 0xd30000>;
  80                         };
  81                 };
  82         };
  83 };
  84
  85 &ethernet0 {
  86         mdio-bus {
  87                 compatible = "realtek,rtl838x-mdio";
  88                 regmap = <&ethernet0>;
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91
  92                 INTERNAL_PHY(8)
  93                 INTERNAL_PHY(9)
  94                 INTERNAL_PHY(10)
  95                 INTERNAL_PHY(11)
  96                 INTERNAL_PHY(12)
  97                 INTERNAL_PHY(13)
  98                 INTERNAL_PHY(14)
  99                 INTERNAL_PHY(15)
 100
 101                 EXTERNAL_PHY(16)
 102                 EXTERNAL_PHY(17)
 103                 EXTERNAL_PHY(18)
 104                 EXTERNAL_PHY(19)
 105                 EXTERNAL_PHY(20)
 106                 EXTERNAL_PHY(21)
 107                 EXTERNAL_PHY(22)
 108                 EXTERNAL_PHY(23)
 109
 110                 EXTERNAL_PHY(24)
 111         };
 112 };
 113
 114 &switch0 {
 115         ports {
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118
 119                 SWITCH_PORT(8, 1, internal)
 120                 SWITCH_PORT(9, 2, internal)
 121                 SWITCH_PORT(10, 3, internal)
 122                 SWITCH_PORT(11, 4, internal)
 123                 SWITCH_PORT(12, 5, internal)
 124                 SWITCH_PORT(13, 6, internal)
 125                 SWITCH_PORT(14, 7, internal)
 126                 SWITCH_PORT(15, 8, internal)
 127
 128                 SWITCH_PORT(16, 9, qsgmii)
 129                 SWITCH_PORT(17, 10, qsgmii)
 130                 SWITCH_PORT(18, 11, qsgmii)
 131                 SWITCH_PORT(19, 12, qsgmii)
 132                 SWITCH_PORT(20, 13, qsgmii)
 133                 SWITCH_PORT(21, 14, qsgmii)
 134                 SWITCH_PORT(22, 15, qsgmii)
 135                 SWITCH_PORT(23, 16, qsgmii)
 136
 137                 port@24 {
 138                         reg = <24>;
 139                         label = "wan";
 140                         phy-handle = <&phy24>;
 141                         phy-mode = "qsgmii";
 142                 };
 143
 144                 port@28 {
 145                         ethernet = <&ethernet0>;
 146                         reg = <28>;
 147                         phy-mode = "internal";
 148
 149                         fixed-link {
 150                                 speed = <1000>;
 151                                 full-duplex;
 152                         };
 153                 };
 154         };
 155 };