3 #include "rtl839x.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 compatible = "zyxel,gs1900-48", "realtek,rtl8393-soc";
10 model = "Zyxel GS1900-48";
14 led-failsafe = &led_sys;
15 led-running = &led_sys;
16 led-upgrade = &led_sys;
20 device_type = "memory";
21 reg = <0x0 0x8000000>;
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinmux_disable_sys_led>;
27 compatible = "gpio-leds";
31 gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
36 compatible = "realtek,rtl8231-gpio";
38 indirect-access-bus-id = <3>;
43 compatible = "gpio-restart";
44 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
48 compatible = "gpio-keys-polled";
53 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
54 linux,code = <KEY_RESTART>;
58 /* i2c of the left SFP cage: port 49 */
60 compatible = "i2c-gpio";
61 sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
62 scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
63 i2c-gpio,delay-us = <2>;
69 compatible = "sff,sfp";
71 los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
72 tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
73 mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
74 tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
77 /* i2c of the right SFP cage: port 50 */
79 compatible = "i2c-gpio";
80 sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
81 scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
82 i2c-gpio,delay-us = <2>;
88 compatible = "sff,sfp";
90 los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
91 tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
92 mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
93 tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
100 compatible = "jedec,spi-nor";
102 spi-max-frequency = <10000000>;
105 compatible = "fixed-partitions";
106 #address-cells = <1>;
115 label = "u-boot-env";
116 reg = <0x40000 0x10000>;
120 label = "u-boot-env2";
121 reg = <0x50000 0x10000>;
126 reg = <0x60000 0x100000>;
130 reg = <0x160000 0x100000>;
134 reg = <0x260000 0xda0000>;
135 compatible = "openwrt,uimage", "denx,uimage";
136 openwrt,ih-magic = <0x83800000>;
140 reg = <0x930000 0x6d0000>;
148 compatible = "realtek,rtl838x-mdio";
149 regmap = <ðernet0>;
150 #address-cells = <1>;
153 /* External phy RTL8218B #1 */
163 /* External phy RTL8218B #2 */
173 /* External phy RTL8218B #3 */
183 /* External phy RTL8218B #4 */
193 /* External phy RTL8218B #5 */
203 /* External phy RTL8218B #6 */
213 /* RTL8393 Internal SerDes */
221 #address-cells = <1>;
224 SWITCH_PORT(0, 01, qsgmii)
225 SWITCH_PORT(1, 02, qsgmii)
226 SWITCH_PORT(2, 03, qsgmii)
227 SWITCH_PORT(3, 04, qsgmii)
228 SWITCH_PORT(4, 05, qsgmii)
229 SWITCH_PORT(5, 06, qsgmii)
230 SWITCH_PORT(6, 07, qsgmii)
231 SWITCH_PORT(7, 08, qsgmii)
233 SWITCH_PORT(8, 09, qsgmii)
234 SWITCH_PORT(9, 10, qsgmii)
235 SWITCH_PORT(10, 11, qsgmii)
236 SWITCH_PORT(11, 12, qsgmii)
237 SWITCH_PORT(12, 13, qsgmii)
238 SWITCH_PORT(13, 14, qsgmii)
239 SWITCH_PORT(14, 15, qsgmii)
240 SWITCH_PORT(15, 16, qsgmii)
242 SWITCH_PORT(16, 17, qsgmii)
243 SWITCH_PORT(17, 18, qsgmii)
244 SWITCH_PORT(18, 19, qsgmii)
245 SWITCH_PORT(19, 20, qsgmii)
246 SWITCH_PORT(20, 21, qsgmii)
247 SWITCH_PORT(21, 22, qsgmii)
248 SWITCH_PORT(22, 23, qsgmii)
249 SWITCH_PORT(23, 24, qsgmii)
251 SWITCH_PORT(24, 25, qsgmii)
252 SWITCH_PORT(25, 26, qsgmii)
253 SWITCH_PORT(26, 27, qsgmii)
254 SWITCH_PORT(27, 28, qsgmii)
255 SWITCH_PORT(28, 29, qsgmii)
256 SWITCH_PORT(29, 30, qsgmii)
257 SWITCH_PORT(30, 31, qsgmii)
258 SWITCH_PORT(31, 32, qsgmii)
260 SWITCH_PORT(32, 33, qsgmii)
261 SWITCH_PORT(33, 34, qsgmii)
262 SWITCH_PORT(34, 35, qsgmii)
263 SWITCH_PORT(35, 36, qsgmii)
264 SWITCH_PORT(36, 37, qsgmii)
265 SWITCH_PORT(37, 38, qsgmii)
266 SWITCH_PORT(38, 39, qsgmii)
267 SWITCH_PORT(39, 40, qsgmii)
269 SWITCH_PORT(40, 41, qsgmii)
270 SWITCH_PORT(41, 42, qsgmii)
271 SWITCH_PORT(42, 43, qsgmii)
272 SWITCH_PORT(43, 44, qsgmii)
273 SWITCH_PORT(44, 45, qsgmii)
274 SWITCH_PORT(45, 46, qsgmii)
275 SWITCH_PORT(46, 47, qsgmii)
276 SWITCH_PORT(47, 48, qsgmii)
283 phy-handle = <&phy48>;
298 phy-handle = <&phy49>;
311 ethernet = <ðernet0>;