d8164fd5c22dfc5cc656744b34e05ab073e42f23
[openwrt/staging/nbd.git] / target / linux / realtek / dts-5.10 / rtl9302_zyxel_xgs1250-12.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /dts-v1/;
3
4 #include "rtl930x.dtsi"
5
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/gpio/gpio.h>
8
9 / {
10 compatible = "zyxel,xgs1250-12", "realtek,rtl838x-soc";
11 model = "Zyxel XGS1250-12 Switch";
12
13 keys {
14 compatible = "gpio-keys";
15
16 mode {
17 label = "reset";
18 gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
19 linux,code = <KEY_RESTART>;
20 };
21 };
22
23 /* i2c of the SFP cage: port 12 */
24 i2c0: i2c-rtl9300 {
25 compatible = "realtek,rtl9300-i2c";
26 reg = <0x1b00036c 0x3c>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 sda-pin = <10>;
30 scl-pin = <8>;
31 clock-frequency = <100000>;
32 };
33
34
35 sfp0: sfp-p12 {
36 compatible = "sff,sfp";
37 i2c-bus = <&i2c0>;
38 los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
39 tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
40 mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
41 tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
42 };
43
44 led_set: led_set@0 {
45 compatible = "realtek,rtl9300-leds";
46 led_set0 = <0x0000 0xffff 0x0a20 0x0b80>; // LED set 0: 1000Mbps, 10/100Mbps
47 led_set1 = <0x0a0b 0x0a28 0x0a82 0x0a0b>; // LED set 1: (10G, 5G, 2.5G) (2.5G, 1G)
48 // (5G, 10/100) (10G, 5G, 2.5G)
49 led_set2 = <0x0000 0xffff 0x0a20 0x0a01>; // LED set 2: 1000MBit, 10GBit
50 };
51 };
52
53 &spi0 {
54 status = "okay";
55 flash@0 {
56 compatible = "jedec,spi-nor";
57 reg = <0>;
58 spi-max-frequency = <10000000>;
59
60 partitions {
61 compatible = "fixed-partitions";
62 #address-cells = <1>;
63 #size-cells = <1>;
64
65 partition@0 {
66 label = "u-boot";
67 reg = <0x0 0xe0000>;
68 read-only;
69 };
70 partition@e0000 {
71 label = "u-boot-env";
72 reg = <0xe0000 0x10000>;
73 };
74 partition@f0000 {
75 label = "u-boot-env2";
76 reg = <0xf0000 0x10000>;
77 read-only;
78 };
79 partition@100000 {
80 label = "jffs";
81 reg = <0x100000 0x100000>;
82 };
83 partition@200000 {
84 label = "jffs2";
85 reg = <0x200000 0x100000>;
86 };
87 partition@b300000 {
88 label = "firmware";
89 reg = <0x300000 0xce0000>;
90 compatible = "openwrt,uimage", "denx,uimage";
91 openwrt,ih-magic = <0x93001250>;
92 };
93 partition@fe0000 {
94 label = "log";
95 reg = <0xfe0000 0x20000>;
96 };
97 };
98 };
99 };
100
101 &ethernet0 {
102 mdio: mdio-bus {
103 compatible = "realtek,rtl838x-mdio";
104 regmap = <&ethernet0>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107
108 /* External RTL8218D PHY */
109 phy0: ethernet-phy@0 {
110 reg = <0>;
111 compatible = "ethernet-phy-ieee802.3-c22";
112 rtl9300,smi-address = <0 0>;
113 sds = < 2 >;
114 // Disabled because we do not know how to bring up again
115 // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
116 };
117 phy1: ethernet-phy@1 {
118 reg = <1>;
119 compatible = "ethernet-phy-ieee802.3-c22";
120 rtl9300,smi-address = <0 1>;
121 };
122 phy2: ethernet-phy@2 {
123 reg = <2>;
124 compatible = "ethernet-phy-ieee802.3-c22";
125 rtl9300,smi-address = <0 2>;
126 };
127 phy3: ethernet-phy@3 {
128 reg = <3>;
129 compatible = "ethernet-phy-ieee802.3-c22";
130 rtl9300,smi-address = <0 3>;
131 };
132 phy4: ethernet-phy@4 {
133 reg = <4>;
134 compatible = "ethernet-phy-ieee802.3-c22";
135 rtl9300,smi-address = <0 4>;
136 };
137 phy5: ethernet-phy@5 {
138 reg = <5>;
139 compatible = "ethernet-phy-ieee802.3-c22";
140 rtl9300,smi-address = <0 5>;
141 };
142 phy6: ethernet-phy@6 {
143 reg = <6>;
144 compatible = "ethernet-phy-ieee802.3-c22";
145 rtl9300,smi-address = <0 6>;
146 };
147 phy7: ethernet-phy@7 {
148 reg = <7>;
149 compatible = "ethernet-phy-ieee802.3-c22";
150 rtl9300,smi-address = <0 7>;
151 };
152
153 /* External Aquantia 113C PHYs */
154 phy24: ethernet-phy@24 {
155 reg = <24>;
156 compatible = "ethernet-phy-ieee802.3-c45";
157 rtl9300,smi-address = <1 8>;
158 sds = < 6 >;
159 // Disabled because we do not know how to bring up again
160 // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
161 };
162
163 phy25: ethernet-phy@25 {
164 reg = <25>;
165 compatible = "ethernet-phy-ieee802.3-c45";
166 rtl9300,smi-address = <2 8>;
167 sds = < 7 >;
168 // Disabled because we do not know how to bring up again
169 // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
170 };
171
172 phy26: ethernet-phy@26 {
173 reg = <26>;
174 compatible = "ethernet-phy-ieee802.3-c45";
175 rtl9300,smi-address = <3 8>;
176 sds = < 8 >;
177 // Disabled because we do not know how to bring up again
178 // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
179 };
180
181 /* SFP Ports */
182 phy27: ethernet-phy@27 {
183 compatible = "ethernet-phy-ieee802.3-c22";
184 phy-is-integrated;
185 reg = <27>;
186 rtl9300,smi-address = <4 0>;
187 sds = < 9 >;
188 };
189
190 };
191 };
192
193 &switch0 {
194 ports {
195 #address-cells = <1>;
196 #size-cells = <0>;
197
198 port@0 {
199 reg = <0>;
200 label = "lan1";
201 phy-handle = <&phy0>;
202 phy-mode = "xgmii";
203 led-set = <0>;
204 };
205 port@1 {
206 reg = <1>;
207 label = "lan2";
208 phy-handle = <&phy1>;
209 phy-mode = "xgmii";
210 led-set = <0>;
211 };
212 port@2 {
213 reg = <2>;
214 label = "lan3";
215 phy-handle = <&phy2>;
216 phy-mode = "xgmii";
217 led-set = <0>;
218 };
219 port@3 {
220 reg = <3>;
221 label = "lan4";
222 phy-handle = <&phy3>;
223 phy-mode = "xgmii";
224 led-set = <0>;
225 };
226 port@4 {
227 reg = <4>;
228 label = "lan5";
229 phy-handle = <&phy4>;
230 phy-mode = "xgmii";
231 led-set = <0>;
232 };
233 port@5 {
234 reg = <5>;
235 label = "lan6";
236 phy-handle = <&phy5>;
237 phy-mode = "xgmii";
238 led-set = <0>;
239 };
240 port@6 {
241 reg = <6>;
242 label = "lan7";
243 phy-handle = <&phy6>;
244 phy-mode = "xgmii";
245 led-set = <0>;
246 };
247 port@7 {
248 reg = <7>;
249 label = "lan8";
250 phy-handle = <&phy7>;
251 phy-mode = "xgmii";
252 led-set = <0>;
253 };
254
255 port@24 {
256 reg = <24>;
257 label = "lan9";
258 phy-mode = "usxgmii";
259 phy-handle = <&phy24>;
260 led-set = <1>;
261 };
262 port@25 {
263 reg = <25>;
264 label = "lan10";
265 phy-mode = "usxgmii";
266 phy-handle = <&phy25>;
267 led-set = <1>;
268 };
269 port@26 {
270 reg = <26>;
271 label = "lan11";
272 phy-mode = "usxgmii";
273 phy-handle = <&phy26>;
274 led-set = <1>;
275 };
276
277 port@27 {
278 reg = <27>;
279 label = "lan12";
280 phy-mode = "10gbase-r";
281 phy-handle = <&phy27>;
282 sfp = <&sfp0>;
283 led-set = <2>;
284
285 fixed-link {
286 speed = <10000>;
287 full-duplex;
288 pause;
289 };
290
291 };
292
293 port@28 {
294 ethernet = <&ethernet0>;
295 reg = <28>;
296 phy-mode = "internal";
297 fixed-link {
298 speed = <10000>;
299 full-duplex;
300 };
301 };
302 };
303 };