realtek: cleanup and update soc dtsi in 5.10
[openwrt/staging/hauke.git] / target / linux / realtek / dts-5.10 / rtl930x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 /dts-v1/;
4
5 #define STRINGIZE(s) #s
6 #define LAN_LABEL(p, s) STRINGIZE(p ## s)
7 #define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
8
9 #define INTERNAL_PHY(n) \
10 phy##n: ethernet-phy@##n { \
11 reg = <##n>; \
12 compatible = "ethernet-phy-ieee802.3-c22"; \
13 phy-is-integrated; \
14 };
15
16 #define EXTERNAL_PHY(n) \
17 phy##n: ethernet-phy@##n { \
18 reg = <##n>; \
19 compatible = "ethernet-phy-ieee802.3-c22"; \
20 };
21
22 #define EXTERNAL_SFP_PHY(n) \
23 phy##n: ethernet-phy@##n { \
24 compatible = "ethernet-phy-ieee802.3-c22"; \
25 sfp; \
26 media = "fibre"; \
27 reg = <##n>; \
28 };
29
30 #define SWITCH_PORT(n, s, m) \
31 port@##n { \
32 reg = <##n>; \
33 label = SWITCH_PORT_LABEL(s) ; \
34 phy-handle = <&phy##n>; \
35 phy-mode = #m ; \
36 };
37
38 #define SWITCH_SFP_PORT(n, s, m) \
39 port@##n { \
40 reg = <##n>; \
41 label = SWITCH_PORT_LABEL(s) ; \
42 phy-handle = <&phy##n>; \
43 phy-mode = #m ; \
44 fixed-link { \
45 speed = <1000>; \
46 full-duplex; \
47 }; \
48 };
49
50 / {
51 #address-cells = <1>;
52 #size-cells = <1>;
53
54 compatible = "realtek,rtl838x-soc";
55
56 cpus {
57 #address-cells = <1>;
58 #size-cells = <0>;
59 frequency = <800000000>;
60
61 cpu@0 {
62 compatible = "mips,mips34Kc";
63 reg = <0>;
64 };
65 };
66
67 memory@0 {
68 device_type = "memory";
69 reg = <0x0 0x8000000>;
70 };
71
72 chosen {
73 bootargs = "console=ttyS0,38400";
74 };
75
76 cpuintc: cpuintc {
77 compatible = "mti,cpu-interrupt-controller";
78 #address-cells = <0>;
79 #interrupt-cells = <1>;
80 interrupt-controller;
81 };
82
83 intc: rtlintc {
84 compatible = "realtek,rt9300-intc";
85 reg = <0xb8003000 0x20>;
86 #address-cells = <0>;
87 #interrupt-cells = <1>;
88 interrupt-controller;
89 };
90
91 osc: oscillator {
92 compatible = "fixed-clock";
93 #clock-cells = <1>;
94 clock-frequency = <175000000>;
95 clock-output-names = "osc";
96 };
97
98 timer: timer@b8003200 {
99 compatible = "realtek,rtl9300-timer";
100 reg = <0xb8003200 0x60>;
101 interrupt-parent = <&intc>;
102 interrupts = <8>;
103 interrupt-names = "ostimer";
104 clocks = <&osc 0>;
105 };
106
107 spi0: spi@b8001200 {
108 compatible = "realtek,rtl838x-nor";
109 reg = <0xb8001200 0x100>;
110
111 #address-cells = <1>;
112 #size-cells = <0>;
113 };
114
115 uart0: uart@b8002000 {
116 compatible = "ns16550a";
117 reg = <0xb8002000 0x100>;
118
119 clock-frequency = <175000000>;
120
121 interrupt-parent = <&intc>;
122 interrupts = <30>;
123
124 reg-io-width = <1>;
125 reg-shift = <2>;
126 fifo-size = <1>;
127 no-loopback-test;
128 };
129
130 uart1: uart@b8002100 {
131 compatible = "ns16550a";
132 reg = <0xb8002100 0x100>;
133
134 clock-frequency = <175000000>;
135
136 interrupt-parent = <&intc>;
137 interrupts = <31>;
138
139 reg-io-width = <1>;
140 reg-shift = <2>;
141 fifo-size = <1>;
142 no-loopback-test;
143 };
144
145 gpio0: gpio-controller@b8003500 {
146 compatible = "realtek,rtl838x-gpio";
147 reg = <0xb8003500 0x20>;
148 gpio-controller;
149 #gpio-cells = <2>;
150 interrupt-parent = <&intc>;
151 interrupts = <31>;
152 };
153
154 ethernet0: ethernet@bb00a300 {
155 compatible = "realtek,rtl838x-eth";
156 reg = <0xbb00a300 0x100>;
157 interrupt-parent = <&intc>;
158 interrupts = <24>;
159 #interrupt-cells = <1>;
160 phy-mode = "internal";
161
162 fixed-link {
163 speed = <1000>;
164 full-duplex;
165 };
166 };
167
168 switch0: switch@bb000000 {
169 compatible = "realtek,rtl83xx-switch";
170
171 interrupt-parent = <&intc>;
172 interrupts = <20>;
173 };
174 };