target/linux/realtek/dts-5.15/rtl8382_inaba_aml2-17gp.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "rtl838x.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
  10         model = "INABA Abaniact AML2-17GP";
  11
  12         memory@0 {
  13                 device_type = "memory";
  14                 reg = <0x0 0x8000000>;
  15         };
  16
  17         keys {
  18                 pinctrl-names = "default";
  19                 pinctrl-0 = <&pinmux_disable_sys_led>;
  20
  21                 compatible = "gpio-keys";
  22
  23                 reset {
  24                         label = "reset";
  25                         gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
  26                         linux,code = <KEY_RESTART>;
  27                 };
  28         };
  29 };
  30
  31 &spi0 {
  32         status = "okay";
  33
  34         flash@0 {
  35                 compatible = "jedec,spi-nor";
  36                 reg = <0>;
  37                 spi-max-frequency = <10000000>;
  38
  39                 partitions {
  40                         compatible = "fixed-partitions";
  41                         #address-cells = <1>;
  42                         #size-cells = <1>;
  43
  44                         partition@0 {
  45                                 label = "u-boot";
  46                                 reg = <0x0 0x80000>;
  47                                 read-only;
  48                         };
  49
  50                         partition@80000 {
  51                                 label = "u-boot-env";
  52                                 reg = <0x80000 0x10000>;
  53                                 read-only;
  54                         };
  55
  56                         partition@90000 {
  57                                 label = "u-boot-env2";
  58                                 reg = <0x90000 0x10000>;
  59                         };
  60
  61                         partition@a0000 {
  62                                 label = "jffs2_cfg";
  63                                 reg = <0xa0000 0x400000>;
  64                                 read-only;
  65                         };
  66
  67                         partition@4a0000 {
  68                                 label = "jffs2_log";
  69                                 reg = <0x4a0000 0x100000>;
  70                                 read-only;
  71                         };
  72
  73                         partition@5a0000 {
  74                                 compatible = "openwrt,uimage", "denx,uimage";
  75                                 label = "firmware";
  76                                 reg = <0x5a0000 0xd30000>;
  77                                 openwrt,ih-magic = <0x83800000>;
  78                         };
  79
  80                         partition@12d0000 {
  81                                 label = "runtime2";
  82                                 reg = <0x12d0000 0xd30000>;
  83                         };
  84                 };
  85         };
  86 };
  87
  88 &ethernet0 {
  89         mdio-bus {
  90                 compatible = "realtek,rtl838x-mdio";
  91                 regmap = <&ethernet0>;
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94
  95                 INTERNAL_PHY(8)
  96                 INTERNAL_PHY(9)
  97                 INTERNAL_PHY(10)
  98                 INTERNAL_PHY(11)
  99                 INTERNAL_PHY(12)
 100                 INTERNAL_PHY(13)
 101                 INTERNAL_PHY(14)
 102                 INTERNAL_PHY(15)
 103
 104                 EXTERNAL_PHY(16)
 105                 EXTERNAL_PHY(17)
 106                 EXTERNAL_PHY(18)
 107                 EXTERNAL_PHY(19)
 108                 EXTERNAL_PHY(20)
 109                 EXTERNAL_PHY(21)
 110                 EXTERNAL_PHY(22)
 111                 EXTERNAL_PHY(23)
 112
 113                 EXTERNAL_PHY(24)
 114         };
 115 };
 116
 117 &switch0 {
 118         ports {
 119                 #address-cells = <1>;
 120                 #size-cells = <0>;
 121
 122                 SWITCH_PORT(8, 1, internal)
 123                 SWITCH_PORT(9, 2, internal)
 124                 SWITCH_PORT(10, 3, internal)
 125                 SWITCH_PORT(11, 4, internal)
 126                 SWITCH_PORT(12, 5, internal)
 127                 SWITCH_PORT(13, 6, internal)
 128                 SWITCH_PORT(14, 7, internal)
 129                 SWITCH_PORT(15, 8, internal)
 130
 131                 SWITCH_PORT(16, 9, qsgmii)
 132                 SWITCH_PORT(17, 10, qsgmii)
 133                 SWITCH_PORT(18, 11, qsgmii)
 134                 SWITCH_PORT(19, 12, qsgmii)
 135                 SWITCH_PORT(20, 13, qsgmii)
 136                 SWITCH_PORT(21, 14, qsgmii)
 137                 SWITCH_PORT(22, 15, qsgmii)
 138                 SWITCH_PORT(23, 16, qsgmii)
 139
 140                 port@24 {
 141                         reg = <24>;
 142                         label = "wan";
 143                         phy-handle = <&phy24>;
 144                         phy-mode = "qsgmii";
 145                 };
 146
 147                 port@28 {
 148                         ethernet = <&ethernet0>;
 149                         reg = <28>;
 150                         phy-mode = "internal";
 151
 152                         fixed-link {
 153                                 speed = <1000>;
 154                                 full-duplex;
 155                         };
 156                 };
 157         };
 158 };