target/linux/realtek/dts-5.15/rtl8382_tplink_t1600g-28ts-v3.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "rtl838x.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         compatible = "tplink,t1600g-28ts-v3", "realtek,rtl838x-soc";
  11         model = "TP-Link T1600G-28TS v3";
  12
  13         aliases {
  14                 led-boot = &led_sys;
  15                 led-failsafe = &led_sys;
  16                 led-running = &led_sys;
  17                 led-upgrade = &led_sys;
  18                 label-mac-device = &ethernet0;
  19         };
  20
  21         chosen {
  22                 stdout-path = "serial0:38400n8";
  23         };
  24
  25         leds {
  26                 pinctrl-names = "default";
  27                 compatible = "gpio-leds";
  28
  29                 led_sys: led-0 {
  30                         label = "green:sys";
  31                         gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
  32                         color = <LED_COLOR_ID_GREEN>;
  33                         function = LED_FUNCTION_STATUS;
  34                 };
  35         };
  36
  37         memory@0 {
  38                 device_type = "memory";
  39                 reg = <0x0 0x10000000>;
  40         };
  41 };
  42
  43 &spi0 {
  44         status = "okay";
  45
  46         flash@0 {
  47                 compatible = "jedec,spi-nor";
  48                 reg = <0>;
  49                 spi-max-frequency = <10000000>;
  50
  51                 partitions {
  52                         compatible = "fixed-partitions";
  53                         #address-cells = <1>;
  54                         #size-cells = <1>;
  55
  56                         partition@0 {
  57                                 label = "u-boot";
  58                                 reg = <0x0 0xe0000>;
  59                                 read-only;
  60                         };
  61                         partition@e0000 {
  62                                 label = "u-boot-env";
  63                                 reg = <0xe0000 0x20000>;
  64                         };
  65                         partition@100000 {
  66                                 compatible = "denx,uimage";
  67                                 label = "firmware";
  68                                 reg = <0x100000 0x1a00000>;
  69                         };
  70                         partition@1b00000 {
  71                                 label = "usrappfs";
  72                                 reg = <0x1b00000 0x400000>;
  73                         };
  74                         partition@1f00000 {
  75                                 label = "para";
  76                                 reg = <0x1f00000 0x100000>;
  77                                 read-only;
  78
  79                                 nvmem-layout {
  80                                         compatible = "fixed-layout";
  81                                         #address-cells = <1>;
  82                                         #size-cells = <1>;
  83
  84                                         factory_macaddr: macaddr@fdff4 {
  85                                                 reg = <0xfdff4 0x6>;
  86                                         };
  87                                 };
  88                         };
  89                 };
  90         };
  91 };
  92
  93 &ethernet0 {
  94         nvmem-cells = <&factory_macaddr>;
  95         nvmem-cell-names = "mac-address";
  96
  97         mdio-bus {
  98                 compatible = "realtek,rtl838x-mdio";
  99                 regmap = <&ethernet0>;
 100                 #address-cells = <1>;
 101                 #size-cells = <0>;
 102
 103                 EXTERNAL_PHY(0)
 104                 EXTERNAL_PHY(1)
 105                 EXTERNAL_PHY(2)
 106                 EXTERNAL_PHY(3)
 107                 EXTERNAL_PHY(4)
 108                 EXTERNAL_PHY(5)
 109                 EXTERNAL_PHY(6)
 110                 EXTERNAL_PHY(7)
 111
 112                 INTERNAL_PHY(8)
 113                 INTERNAL_PHY(9)
 114                 INTERNAL_PHY(10)
 115                 INTERNAL_PHY(11)
 116                 INTERNAL_PHY(12)
 117                 INTERNAL_PHY(13)
 118                 INTERNAL_PHY(14)
 119                 INTERNAL_PHY(15)
 120
 121                 EXTERNAL_PHY(16)
 122                 EXTERNAL_PHY(17)
 123                 EXTERNAL_PHY(18)
 124                 EXTERNAL_PHY(19)
 125                 EXTERNAL_PHY(20)
 126                 EXTERNAL_PHY(21)
 127                 EXTERNAL_PHY(22)
 128                 EXTERNAL_PHY(23)
 129         };
 130 };
 131
 132 &switch0 {
 133         ports {
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136
 137                 SWITCH_PORT(0, 1, qsgmii)
 138                 SWITCH_PORT(1, 2, qsgmii)
 139                 SWITCH_PORT(2, 3, qsgmii)
 140                 SWITCH_PORT(3, 4, qsgmii)
 141                 SWITCH_PORT(4, 5, qsgmii)
 142                 SWITCH_PORT(5, 6, qsgmii)
 143                 SWITCH_PORT(6, 7, qsgmii)
 144                 SWITCH_PORT(7, 8, qsgmii)
 145
 146                 SWITCH_PORT(8, 9, internal)
 147                 SWITCH_PORT(9, 10, internal)
 148                 SWITCH_PORT(10, 11, internal)
 149                 SWITCH_PORT(11, 12, internal)
 150                 SWITCH_PORT(12, 13, internal)
 151                 SWITCH_PORT(13, 14, internal)
 152                 SWITCH_PORT(14, 15, internal)
 153                 SWITCH_PORT(15, 16, internal)
 154
 155                 SWITCH_PORT(16, 17, qsgmii)
 156                 SWITCH_PORT(17, 18, qsgmii)
 157                 SWITCH_PORT(18, 19, qsgmii)
 158                 SWITCH_PORT(19, 20, qsgmii)
 159                 SWITCH_PORT(20, 21, qsgmii)
 160                 SWITCH_PORT(21, 22, qsgmii)
 161                 SWITCH_PORT(22, 23, qsgmii)
 162                 SWITCH_PORT(23, 24, qsgmii)
 163
 164                 port@28 {
 165                         ethernet = <&ethernet0>;
 166                         reg = <28>;
 167                         phy-mode = "internal";
 168
 169                         fixed-link {
 170                                 speed = <1000>;
 171                                 full-duplex;
 172                         };
 173                 };
 174         };
 175 };