1 // SPDX-License-Identifier: GPL-2.0-only
4 * Early intialization code for the Realtek RTL838X SoC
6 * based on the original BSP by
7 * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
8 * Copyright (C) 2020 B. Koblitz
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/of_fdt.h>
16 #include <linux/libfdt.h>
17 #include <asm/bootinfo.h>
18 #include <asm/addrspace.h>
21 #include <asm/smp-ops.h>
22 #include <asm/mips-cps.h>
24 #include <mach-rtl83xx.h>
26 extern char arcs_cmdline
[];
27 extern const char __appended_dtb
;
29 struct rtl83xx_soc_info soc_info
;
32 #ifdef CONFIG_MIPS_MT_SMP
33 extern const struct plat_smp_ops vsmp_smp_ops
;
34 static struct plat_smp_ops rtl_smp_ops
;
36 static void rtl_init_secondary(void)
38 #ifndef CONFIG_CEVT_R4K
40 * These devices are low on resources. There might be the chance that CEVT_R4K
41 * is not enabled in kernel build. Nevertheless the timer and interrupt 7 might
42 * be active by default after startup of secondary VPE. With no registered
43 * handler that leads to continuous unhandeled interrupts. In this case disable
44 * counting (DC) in the core and confirm a pending interrupt.
46 write_c0_cause(read_c0_cause() | CAUSEF_DC
);
48 #endif /* CONFIG_CEVT_R4K */
50 * Enable all CPU interrupts, as everything is managed by the external
51 * controller. TODO: Standard vsmp_init_secondary() has special treatment for
52 * Malta if external GIC is available. Maybe we need this too.
54 if (mips_gic_present())
55 pr_warn("%s: GIC present. Maybe interrupt enabling required.\n", __func__
);
57 set_c0_status(ST0_IM
);
59 #endif /* CONFIG_MIPS_MT_SMP */
61 const char *get_system_type(void)
66 void __init
prom_free_prom_memory(void)
71 void __init
device_tree_init(void)
73 if (!fdt_check_header(&__appended_dtb
)) {
74 fdt
= &__appended_dtb
;
75 pr_info("Using appended Device Tree.\n");
77 initial_boot_params
= (void *)fdt
;
78 unflatten_and_copy_device_tree();
81 static void __init
prom_init_cmdline(void)
84 char **argv
= (char **) KSEG1ADDR(fw_arg1
);
87 arcs_cmdline
[0] = '\0';
89 for (i
= 0; i
< argc
; i
++) {
90 char *p
= (char *) KSEG1ADDR(argv
[i
]);
92 if (CPHYSADDR(p
) && *p
) {
93 strlcat(arcs_cmdline
, p
, sizeof(arcs_cmdline
));
94 strlcat(arcs_cmdline
, " ", sizeof(arcs_cmdline
));
97 pr_info("Kernel command line: %s\n", arcs_cmdline
);
100 void __init
identify_rtl9302(void)
102 switch (sw_r32(RTL93XX_MODEL_NAME_INFO
) & 0xfffffff0) {
104 soc_info
.name
= "RTL9302A 12x2.5G";
107 soc_info
.name
= "RTL9302B 8x2.5G";
110 soc_info
.name
= "RTL9302C 16x2.5G";
113 soc_info
.name
= "RTL9302D 24x2.5G";
116 soc_info
.name
= "RTL9302A";
119 soc_info
.name
= "RTL9302B";
122 soc_info
.name
= "RTL9302C";
125 soc_info
.name
= "RTL9302D";
128 soc_info
.name
= "RTL9302F";
131 soc_info
.name
= "RTL9302";
135 void __init
prom_init(void)
140 setup_8250_early_printk_port(0xb8002000, 2, 0);
142 model
= sw_r32(RTL838X_MODEL_NAME_INFO
);
143 pr_info("RTL838X model is %x\n", model
);
144 model
= model
>> 16 & 0xFFFF;
146 if ((model
!= 0x8328) && (model
!= 0x8330) && (model
!= 0x8332)
147 && (model
!= 0x8380) && (model
!= 0x8382)) {
148 model
= sw_r32(RTL839X_MODEL_NAME_INFO
);
149 pr_info("RTL839X model is %x\n", model
);
150 model
= model
>> 16 & 0xFFFF;
153 if ((model
& 0x8390) != 0x8380 && (model
& 0x8390) != 0x8390) {
154 model
= sw_r32(RTL93XX_MODEL_NAME_INFO
);
155 pr_info("RTL93XX model is %x\n", model
);
156 model
= model
>> 16 & 0xFFFF;
163 soc_info
.name
= "RTL8328";
164 soc_info
.family
= RTL8328_FAMILY_ID
;
167 soc_info
.name
= "RTL8332";
168 soc_info
.family
= RTL8380_FAMILY_ID
;
171 soc_info
.name
= "RTL8380";
172 soc_info
.family
= RTL8380_FAMILY_ID
;
175 soc_info
.name
= "RTL8382";
176 soc_info
.family
= RTL8380_FAMILY_ID
;
179 soc_info
.name
= "RTL8390";
180 soc_info
.family
= RTL8390_FAMILY_ID
;
183 soc_info
.name
= "RTL8391";
184 soc_info
.family
= RTL8390_FAMILY_ID
;
187 soc_info
.name
= "RTL8392";
188 soc_info
.family
= RTL8390_FAMILY_ID
;
191 soc_info
.name
= "RTL8393";
192 soc_info
.family
= RTL8390_FAMILY_ID
;
195 soc_info
.name
= "RTL9301";
196 soc_info
.family
= RTL9300_FAMILY_ID
;
200 soc_info
.family
= RTL9300_FAMILY_ID
;
203 soc_info
.name
= "RTL9303";
204 soc_info
.family
= RTL9300_FAMILY_ID
;
207 soc_info
.name
= "RTL9313";
208 soc_info
.family
= RTL9310_FAMILY_ID
;
211 soc_info
.name
= "DEFAULT";
215 pr_info("SoC Type: %s\n", get_system_type());
217 /* Early detection of CMP support */
218 if(soc_info
.family
== RTL9310_FAMILY_ID
) {
225 if (!register_cps_smp_ops())
228 #ifdef CONFIG_MIPS_MT_SMP
229 if (cpu_has_mipsmt
) {
230 rtl_smp_ops
= vsmp_smp_ops
;
231 rtl_smp_ops
.init_secondary
= rtl_init_secondary
;
232 register_smp_ops(&rtl_smp_ops
);
237 register_up_smp_ops();