target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Setup for the Realtek RTL838X SoC:
   4  *      Memory, Timer and Serial
   5  *
   6  * Copyright (C) 2020 B. Koblitz
   7  * based on the original BSP by
   8  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   9  *
  10  */
  11
  12 #include <linux/console.h>
  13 #include <linux/init.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/delay.h>
  17 #include <linux/of_fdt.h>
  18 #include <linux/irqchip.h>
  19
  20 #include <asm/addrspace.h>
  21 #include <asm/io.h>
  22 #include <asm/bootinfo.h>
  23 #include <asm/reboot.h>
  24 #include <asm/time.h>
  25 #include <asm/prom.h>
  26 #include <asm/smp-ops.h>
  27
  28 #include "mach-rtl83xx.h"
  29
  30 extern struct rtl83xx_soc_info soc_info;
  31
  32 u32 pll_reset_value;
  33
  34 static void rtl838x_restart(char *command)
  35 {
  36         u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
  37
  38         pr_info("System restart.\n");
  39         pr_info("PLL control register: %x, applying reset value %x\n",
  40                 pll, pll_reset_value);
  41
  42         sw_w32(3, RTL838X_INT_RW_CTRL);
  43         sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
  44         sw_w32(0, RTL838X_INT_RW_CTRL);
  45
  46         /* Reset Global Control1 Register */
  47         sw_w32(1, RTL838X_RST_GLB_CTRL_1);
  48 }
  49
  50 static void rtl839x_restart(char *command)
  51 {
  52         /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
  53         void (*f)(void) = (void *) 0xbfc00000;
  54
  55         pr_info("System restart.\n");
  56         /* Reset SoC */
  57         sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
  58         /* and call reset vector */
  59         f();
  60         /* If this fails, halt the CPU */
  61         while
  62                 (1);
  63 }
  64
  65 static void rtl930x_restart(char *command)
  66 {
  67         pr_info("System restart.\n");
  68         sw_w32(0x1, RTL930X_RST_GLB_CTRL_0);
  69         while
  70                 (1);
  71 }
  72
  73 static void rtl931x_restart(char *command)
  74 {
  75         u32 v;
  76
  77         pr_info("System restart.\n");
  78         sw_w32(1, RTL931X_RST_GLB_CTRL);
  79         v = sw_r32(RTL931X_RST_GLB_CTRL);
  80         sw_w32(0x101, RTL931X_RST_GLB_CTRL);
  81         msleep(15);
  82         sw_w32(v, RTL931X_RST_GLB_CTRL);
  83         msleep(15);
  84         sw_w32(0x101, RTL931X_RST_GLB_CTRL);
  85 }
  86
  87 static void rtl838x_halt(void)
  88 {
  89         pr_info("System halted.\n");
  90         while
  91                 (1);
  92 }
  93
  94 static void __init rtl838x_setup(void)
  95 {
  96         pr_info("Registering _machine_restart\n");
  97         _machine_restart = rtl838x_restart;
  98         _machine_halt = rtl838x_halt;
  99
 100         /* This PLL value needs to be restored before a reset and will then be
 101          * preserved over a SoC reset. A wrong value prevents the SoC from
 102          * connecting to the SPI flash controller at boot and reading the
 103          * reset routine */
 104         pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
 105
 106         /* Setup System LED. Bit 15 then allows to toggle it */
 107         sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);
 108 }
 109
 110 static void __init rtl839x_setup(void)
 111 {
 112         pr_info("Registering _machine_restart\n");
 113         _machine_restart = rtl839x_restart;
 114         _machine_halt = rtl838x_halt;
 115
 116         /* Setup System LED. Bit 14 of RTL839X_LED_GLB_CTRL then allows to toggle it */
 117         sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);
 118 }
 119
 120 static void __init rtl930x_setup(void)
 121 {
 122         pr_info("Registering _machine_restart\n");
 123         _machine_restart = rtl930x_restart;
 124         _machine_halt = rtl838x_halt;
 125
 126         if (soc_info.id == 0x9302)
 127                 sw_w32_mask(0, 3 << 13, RTL9302_LED_GLB_CTRL);
 128         else
 129                 sw_w32_mask(0, 3 << 13, RTL930X_LED_GLB_CTRL);
 130 }
 131
 132 static void __init rtl931x_setup(void)
 133 {
 134         pr_info("Registering _machine_restart\n");
 135         _machine_restart = rtl931x_restart;
 136         _machine_halt = rtl838x_halt;
 137         sw_w32_mask(0, 3 << 12, RTL931X_LED_GLB_CTRL);
 138 }
 139
 140 void __init plat_mem_setup(void)
 141 {
 142         void *dtb;
 143
 144         set_io_port_base(KSEG1);
 145         _machine_restart = rtl838x_restart;
 146
 147         if (fw_passed_dtb) /* UHI interface */
 148                 dtb = (void *)fw_passed_dtb;
 149         else if (__dtb_start != __dtb_end)
 150                 dtb = (void *)__dtb_start;
 151         else
 152                 panic("no dtb found");
 153
 154         /*
 155          * Load the devicetree. This causes the chosen node to be
 156          * parsed resulting in our memory appearing
 157          */
 158         __dt_setup_arch(dtb);
 159
 160         switch (soc_info.family) {
 161         case RTL8380_FAMILY_ID:
 162                 rtl838x_setup();
 163                 break;
 164         case RTL8390_FAMILY_ID:
 165                 rtl839x_setup();
 166                 break;
 167         case RTL9300_FAMILY_ID:
 168                 rtl930x_setup();
 169                 break;
 170         case RTL9310_FAMILY_ID:
 171                 rtl931x_setup();
 172                 break;
 173         }
 174 }
 175
 176 void __init plat_time_init(void)
 177 {
 178         struct device_node *np;
 179         u32 freq = 500000000;
 180
 181         of_clk_init(NULL);
 182         timer_probe();
 183
 184         np = of_find_node_by_name(NULL, "cpus");
 185         if (!np) {
 186                 pr_err("Missing 'cpus' DT node, using default frequency.");
 187         } else {
 188                 if (of_property_read_u32(np, "frequency", &freq) < 0)
 189                         pr_err("No 'frequency' property in DT, using default.");
 190                 else
 191                         pr_info("CPU frequency from device tree: %dMHz", freq / 1000000);
 192                 of_node_put(np);
 193         }
 194
 195         mips_hpt_frequency = freq / 2;
 196 }
 197
 198 void __init arch_init_irq(void)
 199 {
 200         irqchip_init();
 201 }