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realtek: clock driver: enhancement for RTL930X
[openwrt/staging/svanheule.git] / target / linux / realtek / files-5.10 / drivers / clk / realtek / clk-rtl83xx.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Realtek RTL83XX clock driver
4 * Copyright (C) 2022 Markus Stockhausen <markus.stockhausen@gmx.de>
5 */
6
7 #include <asm/cacheflush.h>
8 #include <asm/mipsmtregs.h>
9 #include <dt-bindings/clock/rtl83xx-clk.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/cpu.h>
14 #include <linux/delay.h>
15 #include <linux/genalloc.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/of_address.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22
23 #include "clk-rtl83xx.h"
24
25 /*
26 * some hardware specific definitions
27 */
28
29 #define RTCL_SOC838X 0
30 #define RTCL_SOC839X 1
31 #define RTCL_SOC930X 2
32 #define RTCL_SOCCNT 3
33
34 #define RTCL_DDR1 1
35 #define RTCL_DDR2 2
36 #define RTCL_DDR3 3
37
38 #define RTCL_REGCNT 2
39
40 #define RTCL_XTAL_RATE 25000000
41
42 #define RTCL_SOC_CLK(soc, clk) ((soc << 8) + clk)
43
44 static const int rtcl_regs[RTCL_SOCCNT][RTCL_REGCNT][CLK_COUNT] = {
45 {
46 {
47 RTL_SW_CORE_BASE + RTL838X_PLL_SW_CTRL0,
48 RTL_SW_CORE_BASE + RTL838X_PLL_CPU_CTRL0,
49 RTL_SW_CORE_BASE + RTL838X_PLL_MEM_CTRL0,
50 RTL_SW_CORE_BASE + RTL838X_PLL_LXB_CTRL0,
51 }, {
52 RTL_SW_CORE_BASE + RTL838X_PLL_SW_CTRL1,
53 RTL_SW_CORE_BASE + RTL838X_PLL_CPU_CTRL1,
54 RTL_SW_CORE_BASE + RTL838X_PLL_MEM_CTRL1,
55 RTL_SW_CORE_BASE + RTL838X_PLL_LXB_CTRL1
56 }
57 }, {
58 {
59 RTL_SW_CORE_BASE + RTL839X_PLL_SW_CTRL,
60 RTL_SW_CORE_BASE + RTL839X_PLL_CPU_CTRL0,
61 RTL_SW_CORE_BASE + RTL839X_PLL_MEM_CTRL0,
62 RTL_SW_CORE_BASE + RTL839X_PLL_LXB_CTRL0
63 }, {
64 RTL_SW_CORE_BASE + RTL839X_PLL_SW_CTRL,
65 RTL_SW_CORE_BASE + RTL839X_PLL_CPU_CTRL1,
66 RTL_SW_CORE_BASE + RTL839X_PLL_MEM_CTRL1,
67 RTL_SW_CORE_BASE + RTL839X_PLL_LXB_CTRL1
68 }
69 }, {
70 {
71 RTL_SW_CORE_BASE + RTL930X_PLL_SW_CTRL0,
72 RTL_SW_CORE_BASE + RTL930X_PLL_CPU_CTRL0,
73 RTL_SOC_BASE + RTL930X_PLL_MEM_CTRL2,
74 RTL_SW_CORE_BASE + RTL930X_PLL_SW_DIV_CTRL
75 }, {
76 RTL_SW_CORE_BASE + RTL930X_PLL_SW_CTRL1,
77 RTL_SW_CORE_BASE + RTL930X_PLL_CPU_MISC_CTRL,
78 RTL_SOC_BASE + RTL930X_PLL_MEM_CTRL3,
79 RTL_SW_CORE_BASE + RTL930X_PLL_SW_DIV_CTRL
80 }
81 }
82 };
83
84 #define RTCL_REG_SET(_rate, _ctrl0, _ctrl1) \
85 { \
86 .rate = _rate, \
87 .ctrl0 = _ctrl0, \
88 .ctrl1 = _ctrl1, \
89 }
90
91 struct rtcl_reg_set {
92 unsigned long rate;
93 unsigned int ctrl0;
94 unsigned int ctrl1;
95 };
96
97 /*
98 * The following configuration tables are valid operation points for their
99 * corresponding PLLs. The magic numbers are precalculated mulitpliers and
100 * dividers to keep the driver simple. They also provide rates outside the
101 * allowed physical specifications. E.g. DDR3 memory has a lower limit of 303
102 * MHz or the CPU might get unstable if set to anything above its startup
103 * frequency. Additionally the Realtek SOCs tend to expect CPU speed larger
104 * than MEM speed larger than LXB speed. The caller or DT configuration must
105 * take care that only valid operating points are selected.
106 */
107
108 static const struct rtcl_reg_set rtcl_838x_cpu_reg_set[] = {
109 RTCL_REG_SET(300000000, 0x045c, 5),
110 RTCL_REG_SET(325000000, 0x0464, 5),
111 RTCL_REG_SET(350000000, 0x046c, 5),
112 RTCL_REG_SET(375000000, 0x0474, 5),
113 RTCL_REG_SET(400000000, 0x045c, 3),
114 RTCL_REG_SET(425000000, 0x0462, 3),
115 RTCL_REG_SET(450000000, 0x0468, 3),
116 RTCL_REG_SET(475000000, 0x046e, 3),
117 RTCL_REG_SET(500000000, 0x0474, 3),
118 RTCL_REG_SET(525000000, 0x047a, 3),
119 RTCL_REG_SET(550000000, 0x0480, 3),
120 RTCL_REG_SET(575000000, 0x0486, 3),
121 RTCL_REG_SET(600000000, 0x048c, 3),
122 RTCL_REG_SET(625000000, 0x0492, 3)
123 };
124
125 static const struct rtcl_reg_set rtcl_838x_mem_reg_set[] = {
126 RTCL_REG_SET(200000000, 0x041b, 5),
127 RTCL_REG_SET(225000000, 0x0417, 3),
128 RTCL_REG_SET(250000000, 0x041a, 3),
129 RTCL_REG_SET(275000000, 0x0412, 1),
130 RTCL_REG_SET(300000000, 0x0414, 1),
131 RTCL_REG_SET(325000000, 0x0416, 1),
132 RTCL_REG_SET(350000000, 0x0418, 1),
133 RTCL_REG_SET(375000000, 0x041a, 1)
134 };
135
136 static const struct rtcl_reg_set rtcl_838x_lxb_reg_set[] = {
137 RTCL_REG_SET(100000000, 0x043c, 0),
138 RTCL_REG_SET(125000000, 0x043c, 0),
139 RTCL_REG_SET(150000000, 0x0450, 5),
140 RTCL_REG_SET(175000000, 0x0450, 5),
141 RTCL_REG_SET(200000000, 0x047c, 0)
142 };
143
144 static const struct rtcl_reg_set rtcl_839x_cpu_reg_set[] = {
145 RTCL_REG_SET(400000000, 0x0414, 5),
146 RTCL_REG_SET(425000000, 0x041e, 6),
147 RTCL_REG_SET(450000000, 0x0417, 5),
148 RTCL_REG_SET(475000000, 0x0422, 6),
149 RTCL_REG_SET(500000000, 0x041a, 5),
150 RTCL_REG_SET(525000000, 0x0426, 6),
151 RTCL_REG_SET(550000000, 0x0412, 4),
152 RTCL_REG_SET(575000000, 0x042a, 6),
153 RTCL_REG_SET(600000000, 0x0414, 4),
154 RTCL_REG_SET(625000000, 0x042e, 6),
155 RTCL_REG_SET(650000000, 0x0416, 4),
156 RTCL_REG_SET(675000000, 0x0432, 6),
157 RTCL_REG_SET(700000000, 0x0418, 4),
158 RTCL_REG_SET(725000000, 0x0436, 6),
159 RTCL_REG_SET(750000000, 0x0438, 6),
160 RTCL_REG_SET(775000000, 0x043a, 6),
161 RTCL_REG_SET(800000000, 0x043c, 6),
162 RTCL_REG_SET(825000000, 0x043e, 6),
163 RTCL_REG_SET(850000000, 0x0440, 6)
164 };
165
166 static const struct rtcl_reg_set rtcl_839x_mem_reg_set[] = {
167 RTCL_REG_SET(125000000, 0x041a, 7),
168 RTCL_REG_SET(150000000, 0x0414, 6),
169 RTCL_REG_SET(175000000, 0x0418, 6),
170 RTCL_REG_SET(200000000, 0x041c, 6),
171 RTCL_REG_SET(225000000, 0x0417, 5),
172 RTCL_REG_SET(250000000, 0x041a, 5),
173 RTCL_REG_SET(275000000, 0x0412, 4),
174 RTCL_REG_SET(300000000, 0x0414, 4),
175 RTCL_REG_SET(325000000, 0x0416, 4),
176 RTCL_REG_SET(350000000, 0x0418, 4),
177 RTCL_REG_SET(375000000, 0x041a, 4),
178 RTCL_REG_SET(400000000, 0x041c, 4)
179 };
180
181 static const struct rtcl_reg_set rtcl_839x_lxb_reg_set[] = {
182 RTCL_REG_SET(50000000, 0x1414, 3),
183 RTCL_REG_SET(100000000, 0x0814, 3),
184 RTCL_REG_SET(150000000, 0x0414, 3),
185 RTCL_REG_SET(200000000, 0x0414, 7)
186 };
187
188 static const struct rtcl_reg_set rtcl_930x_cpu_reg_set[] = {
189 /*
190 * TODO: The SRAM runs on 250 MHz. Depending on the the CPU speed we need
191 * additional magic register settings to make things work. For now remember
192 * that, provide all PLL values and exclude unwanted settings in DT.
193 */
194 RTCL_REG_SET(400000000, 0x002e, 4), /* sram_oc0_pulse=1 oc0_sram_pulse=0 */
195 RTCL_REG_SET(425000000, 0x0031, 4), /* ... */
196 RTCL_REG_SET(450000000, 0x0034, 4),
197 RTCL_REG_SET(475000000, 0x0037, 4), /* sram_oc0_pulse=1 oc0_sram_pulse=0 */
198 RTCL_REG_SET(500000000, 0x003a, 4), /* sram_oc0_pulse=1 oc0_sram_pulse=1 */
199 RTCL_REG_SET(525000000, 0x0032, 3), /* sram_oc0_pulse=0 oc0_sram_pulse=1 */
200 RTCL_REG_SET(550000000, 0x0035, 3), /* ... */
201 RTCL_REG_SET(575000000, 0x0037, 3),
202 RTCL_REG_SET(600000000, 0x002e, 2),
203 RTCL_REG_SET(625000000, 0x0030, 2),
204 RTCL_REG_SET(650000000, 0x0032, 2),
205 RTCL_REG_SET(675000000, 0x0034, 2),
206 RTCL_REG_SET(700000000, 0x0036, 2),
207 RTCL_REG_SET(725000000, 0x0038, 2),
208 RTCL_REG_SET(750000000, 0x003a, 2),
209 RTCL_REG_SET(775000000, 0x003c, 2),
210 RTCL_REG_SET(800000000, 0x003e, 2),
211 RTCL_REG_SET(825000000, 0x0040, 2),
212 RTCL_REG_SET(850000000, 0x0042, 2),
213 RTCL_REG_SET(875000000, 0x0044, 2),
214 RTCL_REG_SET(900000000, 0x0046, 2),
215 RTCL_REG_SET(925000000, 0x0048, 2),
216 RTCL_REG_SET(950000000, 0x004a, 2),
217 RTCL_REG_SET(975000000, 0x004c, 2), /* sram_oc0_pulse=0 oc0_sram_pulse=1 */
218 RTCL_REG_SET(1000000000, 0x004e, 2), /* sram_oc0_pulse=0 oc0_sram_pulse=2 */
219 RTCL_REG_SET(1025000000, 0x0050, 2), /* ... */
220 };
221
222 static const struct rtcl_reg_set rtcl_930x_mem_reg_set[] = {
223 RTCL_REG_SET(600000000, 0x0000, 0),
224 };
225
226 static const struct rtcl_reg_set rtcl_930x_lxb_reg_set[] = {
227 RTCL_REG_SET(153125000, 0x0c00, 0),
228 RTCL_REG_SET(175000000, 0x0a00, 0)
229 };
230
231 struct rtcl_rtab_set {
232 int count;
233 const struct rtcl_reg_set *rset;
234 };
235
236 #define RTCL_RTAB_SET(_rset) { .count = ARRAY_SIZE(_rset), .rset = _rset }
237 #define RTCL_RTAB_SET_NONE { .count = 0, .rset = NULL }
238
239 static const struct rtcl_rtab_set rtcl_rtab_set[RTCL_SOCCNT][CLK_COUNT] = {
240 {
241 RTCL_RTAB_SET_NONE,
242 RTCL_RTAB_SET(rtcl_838x_cpu_reg_set),
243 RTCL_RTAB_SET(rtcl_838x_mem_reg_set),
244 RTCL_RTAB_SET(rtcl_838x_lxb_reg_set)
245 }, {
246 RTCL_RTAB_SET_NONE,
247 RTCL_RTAB_SET(rtcl_839x_cpu_reg_set),
248 RTCL_RTAB_SET(rtcl_839x_mem_reg_set),
249 RTCL_RTAB_SET(rtcl_839x_lxb_reg_set)
250 }, {
251 RTCL_RTAB_SET_NONE,
252 RTCL_RTAB_SET(rtcl_930x_cpu_reg_set),
253 RTCL_RTAB_SET(rtcl_930x_mem_reg_set),
254 RTCL_RTAB_SET(rtcl_930x_lxb_reg_set)
255 }
256 };
257
258 #define RTCL_ROUND_SET(_min, _max, _s) { .min = _min, .max = _max, .step = _s }
259 #define RTCL_ROUND_SET_NONE { .min = 0, .max = 0, .step = 1 }
260
261 struct rtcl_round_set {
262 unsigned long min;
263 unsigned long max;
264 unsigned long step;
265 };
266
267 static const struct rtcl_round_set rtcl_round_set[RTCL_SOCCNT][CLK_COUNT] = {
268 {
269 RTCL_ROUND_SET_NONE,
270 RTCL_ROUND_SET(300000000, 625000000, 25000000),
271 RTCL_ROUND_SET(200000000, 375000000, 25000000),
272 RTCL_ROUND_SET(100000000, 200000000, 25000000)
273 }, {
274 RTCL_ROUND_SET_NONE,
275 RTCL_ROUND_SET(400000000, 850000000, 25000000),
276 RTCL_ROUND_SET(100000000, 400000000, 25000000),
277 RTCL_ROUND_SET(50000000, 200000000, 50000000)
278 }, {
279 RTCL_ROUND_SET_NONE,
280 RTCL_ROUND_SET(400000000, 975000000, 25000000),
281 RTCL_ROUND_SET(600000000, 600000000, 1),
282 RTCL_ROUND_SET(153125000, 175000000, 21875000)
283 }
284 };
285
286 static const int rtcl_divn3[] = { 2, 3, 4, 6 };
287 static const int rtcl_xdiv[] = { 1, 2, 4, 2 };
288
289 /*
290 * module data structures
291 */
292
293 #define RTCL_CLK_INFO(_idx, _name, _pname0, _pname1, _pname2, _dname) \
294 { \
295 .idx = _idx, \
296 .name = _name, \
297 .parent_name[RTCL_SOC838X] = _pname0, \
298 .parent_name[RTCL_SOC839X] = _pname1, \
299 .parent_name[RTCL_SOC930X] = _pname2, \
300 .display_name = _dname, \
301 }
302
303 struct rtcl_clk_info {
304 unsigned int idx;
305 const char *name;
306 const char *parent_name[RTCL_SOCCNT];
307 const char *display_name;
308 };
309
310 struct rtcl_clk {
311 struct clk_hw hw;
312 unsigned int idx;
313 unsigned long min;
314 unsigned long max;
315 unsigned long startup;
316 };
317 /*
318 * PLLs on the devices are mostly pretty straight forward derived from 25 MHz
319 * oscillator clock. Only exception is RTL930X where LXB clock has only dividers
320 * and is derived from switch clock.
321 */
322 static const struct rtcl_clk_info rtcl_clk_info[CLK_COUNT] = {
323 RTCL_CLK_INFO(CLK_SW, "sw_clk", "xtal_clk", "xtal_clk", "xtal_clk", "SW"),
324 RTCL_CLK_INFO(CLK_CPU, "cpu_clk", "xtal_clk", "xtal_clk", "xtal_clk", "CPU"),
325 RTCL_CLK_INFO(CLK_MEM, "mem_clk", "xtal_clk", "xtal_clk", "xtal_clk", "MEM"),
326 RTCL_CLK_INFO(CLK_LXB, "lxb_clk", "xtal_clk", "xtal_clk", "sw_clk", "LXB")
327 };
328
329 struct rtcl_dram {
330 int type;
331 int buswidth;
332 };
333
334 struct rtcl_sram {
335 int *pmark;
336 unsigned long vbase;
337 };
338
339 struct rtcl_ccu {
340 spinlock_t lock;
341 unsigned int soc;
342 struct rtcl_sram sram;
343 struct rtcl_dram dram;
344 struct device_node *np;
345 struct platform_device *pdev;
346 struct rtcl_clk clks[CLK_COUNT];
347 };
348
349 struct rtcl_ccu *rtcl_ccu;
350
351 #define rtcl_hw_to_clk(_hw) container_of(_hw, struct rtcl_clk, hw)
352
353 /*
354 * SRAM relocatable assembler functions. The dram() parts point to normal kernel
355 * memory while the sram() parts are the same functions but relocated to SRAM.
356 */
357
358 extern void rtcl_838x_dram_start(void);
359 extern int rtcl_838x_dram_size;
360
361 extern void rtcl_838x_dram_set_rate(int clk_idx, int ctrl0, int ctrl1);
362 static void (*rtcl_838x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1);
363
364 extern void rtcl_839x_dram_start(void);
365 extern int rtcl_839x_dram_size;
366
367 extern void rtcl_839x_dram_set_rate(int clk_idx, int ctrl0, int ctrl1);
368 static void (*rtcl_839x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1);
369
370 extern void rtcl_930x_dram_start(void);
371 extern int rtcl_930x_dram_size;
372
373 extern void rtcl_930x_dram_set_rate(int clk_idx, int ctrl0, int ctrl1);
374 static void (*rtcl_930x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1);
375
376 /*
377 * clock setter/getter functions
378 */
379
380 static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
381 {
382 struct rtcl_clk *clk = rtcl_hw_to_clk(hw);
383 unsigned int read0, read1;
384 unsigned int mul1 = 1, mul2 = 1, div1 = 1, div2 = 1, div3 = 1;
385 unsigned int cmu_divn2, cmu_divn2_selb, cmu_divn3_sel;
386
387 if ((clk->idx >= CLK_COUNT) || (!rtcl_ccu) || (rtcl_ccu->soc >= RTCL_SOCCNT))
388 return 0;
389
390 read0 = ioread32((void *)rtcl_regs[rtcl_ccu->soc][0][clk->idx]);
391 read1 = ioread32((void *)rtcl_regs[rtcl_ccu->soc][1][clk->idx]);
392
393 switch (RTCL_SOC_CLK(rtcl_ccu->soc, clk->idx)) {
394 case RTCL_SOC_CLK(RTCL_SOC838X, CLK_LXB):
395 case RTCL_SOC_CLK(RTCL_SOC838X, CLK_CPU):
396 case RTCL_SOC_CLK(RTCL_SOC838X, CLK_MEM):
397 cmu_divn2 = RTL83XX_PLL_CTRL0_CMU_DIVN2(read0) + 4;
398 cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(read1);
399 cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(read1)];
400
401 mul1 = RTL_PLL_CTRL0_CMU_NCODE_IN(read0) + 4;
402 mul2 = RTL_PLL_CTRL0_CMU_SEL_DIV4(read0) ? 4 : 1;
403 div1 = 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(read0);
404 div2 = cmu_divn2_selb ? cmu_divn3_sel : cmu_divn2;
405 div3 = rtcl_xdiv[clk->idx];
406 break;
407 case RTCL_SOC_CLK(RTCL_SOC839X, CLK_CPU):
408 case RTCL_SOC_CLK(RTCL_SOC839X, CLK_MEM):
409 case RTCL_SOC_CLK(RTCL_SOC839X, CLK_LXB):
410 cmu_divn2 = RTL83XX_PLL_CTRL0_CMU_DIVN2(read0) + 4;
411 cmu_divn2_selb = RTL839X_PLL_CTRL1_CMU_DIVN2_SELB(read1);
412 cmu_divn3_sel = rtcl_divn3[RTL839X_PLL_CTRL1_CMU_DIVN3_SEL(read1)];
413
414 mul1 = RTL_PLL_CTRL0_CMU_NCODE_IN(read0) + 4;
415 mul2 = RTL_PLL_CTRL0_CMU_SEL_DIV4(read0) ? 4 : 1;
416 div1 = 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(read0);
417 div2 = cmu_divn2_selb ? cmu_divn3_sel : cmu_divn2;
418 div3 = rtcl_xdiv[clk->idx];
419 break;
420 case RTCL_SOC_CLK(RTCL_SOC838X, CLK_SW):
421 case RTCL_SOC_CLK(RTCL_SOC839X, CLK_SW):
422 mul1 = RTL_PLL_CTRL0_CMU_NCODE_IN(read0) + 4;
423 mul2 = RTL_PLL_CTRL0_CMU_SEL_DIV4(read0) ? 4 : 1;
424 div1 = 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(read0);
425 break;
426 case RTCL_SOC_CLK(RTCL_SOC930X, CLK_CPU):
427 mul1 = (RTL_PLL_CTRL0_CMU_NCODE_IN(read0) + 2) * 2;
428 mul2 = RTL_PLL_CTRL0_CMU_SEL_DIV4(read0) ? 4 : 1;
429 div1 = 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(read0);
430 div2 = RTL930X_PLL_MISC_CMU_DIVN2(read1) + 2;
431 div3 = RTL930X_PLL_CTRL0_CMU_DIVN3_CPU(read0) + 1;
432 break;
433 case RTCL_SOC_CLK(RTCL_SOC930X, CLK_SW):
434 mul1 = (RTL_PLL_CTRL0_CMU_NCODE_IN(read0) + 2) * 2;
435 mul2 = RTL_PLL_CTRL0_CMU_SEL_DIV4(read0) ? 4 : 1;
436 div1 = 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(read0);
437 break;
438 case RTCL_SOC_CLK(RTCL_SOC930X, CLK_MEM):
439 mul1 = RTL930X_PLL_MEM_CTRL3_CMU_NCODE_IN(read1) + 2;
440 div1 = 1 << RTL930X_PLL_MEM_CTRL2_PREDIV(read0);
441 div2 = 2;
442 break;
443 case RTCL_SOC_CLK(RTCL_SOC930X, CLK_LXB):
444 div1 = (RTL930X_PLL_SW_DIV_CTRL_DIVN2_LXB(read0) + 2) * 2;
445 break;
446 }
447 /*
448 * Do the math in a way that interim values stay inside 32 bit bounds
449 */
450 return (((parent_rate / 16) * mul1) / (div1 * div2 * div3)) * mul2 * 16;
451 }
452
453 static int rtcl_838x_set_rate(int clk_idx, const struct rtcl_reg_set *reg)
454 {
455 unsigned long irqflags;
456 /*
457 * Runtime of this function (including locking)
458 * CPU: up to 14000 cycles / up to 56 us at 250 MHz (half default speed)
459 */
460 spin_lock_irqsave(&rtcl_ccu->lock, irqflags);
461 rtcl_838x_sram_set_rate(clk_idx, reg->ctrl0, reg->ctrl1);
462 spin_unlock_irqrestore(&rtcl_ccu->lock, irqflags);
463
464 return 0;
465 }
466
467 static int rtcl_839x_set_rate(int clk_idx, const struct rtcl_reg_set *reg)
468 {
469 unsigned long vpflags;
470 unsigned long irqflags;
471 /*
472 * Runtime of this function (including locking)
473 * CPU: up to 31000 cycles / up to 89 us at 350 MHz (half default speed)
474 */
475 spin_lock_irqsave(&rtcl_ccu->lock, irqflags);
476 vpflags = dvpe();
477 rtcl_839x_sram_set_rate(clk_idx, reg->ctrl0, reg->ctrl1);
478 evpe(vpflags);
479 spin_unlock_irqrestore(&rtcl_ccu->lock, irqflags);
480
481 return 0;
482 }
483
484 static int rtcl_930x_set_rate(int clk_idx, const struct rtcl_reg_set *reg)
485 {
486 unsigned long vpflags;
487 unsigned long irqflags;
488 /*
489 * Runtime of this function (including locking)
490 * CPU: up 19000 cycles / up to 48 us at 400 MHz (half default speed)
491 */
492 spin_lock_irqsave(&rtcl_ccu->lock, irqflags);
493 vpflags = dvpe();
494 rtcl_930x_dram_set_rate(clk_idx, reg->ctrl0, reg->ctrl1);
495 evpe(vpflags);
496 spin_unlock_irqrestore(&rtcl_ccu->lock, irqflags);
497
498 return 0;
499 }
500
501 static int rtcl_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
502 {
503 int tab_idx;
504 struct rtcl_clk *clk = rtcl_hw_to_clk(hw);
505 const struct rtcl_rtab_set *rtab = &rtcl_rtab_set[rtcl_ccu->soc][clk->idx];
506 const struct rtcl_round_set *round = &rtcl_round_set[rtcl_ccu->soc][clk->idx];
507
508 if ((clk->idx != CLK_CPU) || (!rtcl_ccu->sram.vbase))
509 return -EINVAL;
510 /*
511 * Currently we do not know if SRAM is stable on these devices. Maybe someone
512 * changes memory in this region and does not care about proper allocation. So
513 * check if something might go wrong.
514 */
515 if (unlikely(*rtcl_ccu->sram.pmark != RTL_SRAM_MARKER)) {
516 dev_err(&rtcl_ccu->pdev->dev, "SRAM code lost\n");
517 return -EINVAL;
518 }
519
520 tab_idx = (rate - round->min) / round->step;
521 if ((tab_idx < 0) || (tab_idx >= rtab->count) || (rtab->rset[tab_idx].rate != rate))
522 return -EINVAL;
523
524 switch (rtcl_ccu->soc) {
525 case RTCL_SOC838X:
526 return rtcl_838x_set_rate(clk->idx, &rtab->rset[tab_idx]);
527 case RTCL_SOC839X:
528 return rtcl_839x_set_rate(clk->idx, &rtab->rset[tab_idx]);
529 case RTCL_SOC930X:
530 return rtcl_930x_set_rate(clk->idx, &rtab->rset[tab_idx]);
531 }
532
533 return -ENXIO;
534 }
535
536 static long rtcl_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate)
537 {
538 struct rtcl_clk *clk = rtcl_hw_to_clk(hw);
539 unsigned long rrate = max(clk->min, min(clk->max, rate));
540 const struct rtcl_round_set *round = &rtcl_round_set[rtcl_ccu->soc][clk->idx];
541
542 rrate = ((rrate + (round->step >> 1)) / round->step) * round->step;
543 rrate -= (rrate > clk->max) ? round->step : 0;
544 rrate += (rrate < clk->min) ? round->step : 0;
545
546 return rrate;
547 }
548
549 /*
550 * Initialization functions to register the CCU and its clocks
551 */
552
553 #define RTCL_SRAM_FUNC(SOC, PBASE, FN) ({ \
554 rtcl_##SOC##_sram_##FN = ((void *)&rtcl_##SOC##_dram_##FN \
555 - (void *)&rtcl_##SOC##_dram_start) \
556 + (void *)PBASE; })
557
558 static const struct clk_ops rtcl_clk_ops = {
559 .set_rate = rtcl_set_rate,
560 .round_rate = rtcl_round_rate,
561 .recalc_rate = rtcl_recalc_rate,
562 };
563
564 static void rtcl_unlock_registers(void)
565 {
566 u32 enable, reg;
567
568 if (rtcl_ccu->soc != RTCL_SOC838X)
569 return;
570 /*
571 * Some RTL838X devices are shipped with register access locked. In this case
572 * we cannot read and/or write to LXB or SW PLL registers. As there is no real
573 * benefit of always unlocking/locking these registers just open up everything.
574 */
575 enable = RTL838X_INT_RW_CTRL_READ_EN | RTL838X_INT_RW_CTRL_WRITE_EN;
576 reg = ioread32((void *)RTL_SW_CORE_BASE + RTL838X_INT_RW_CTRL);
577 if ((reg & enable) != enable) {
578 reg |= enable;
579 iowrite32(reg, (void *)RTL_SW_CORE_BASE + RTL838X_INT_RW_CTRL);
580 pr_warn("%s: registers unlocked\n", __func__);
581 }
582 }
583
584 static int rtcl_ccu_create(struct device_node *np)
585 {
586 int soc;
587
588 if (of_device_is_compatible(np, "realtek,rtl8380-clock"))
589 soc = RTCL_SOC838X;
590 else if (of_device_is_compatible(np, "realtek,rtl8390-clock"))
591 soc = RTCL_SOC839X;
592 else if (of_device_is_compatible(np, "realtek,rtl9300-clock"))
593 soc = RTCL_SOC930X;
594 else
595 return -ENXIO;
596
597 rtcl_ccu = kzalloc(sizeof(*rtcl_ccu), GFP_KERNEL);
598 if (IS_ERR(rtcl_ccu))
599 return -ENOMEM;
600
601 rtcl_ccu->np = np;
602 rtcl_ccu->soc = soc;
603 rtcl_ccu->dram.type = RTL_MC_MCR_DRAMTYPE(ioread32((void *)RTL_SOC_BASE + RTL_MC_MCR));
604 rtcl_ccu->dram.buswidth = RTL_MC_DCR_BUSWIDTH(ioread32((void *)RTL_SOC_BASE + RTL_MC_DCR));
605 spin_lock_init(&rtcl_ccu->lock);
606
607 return 0;
608 }
609
610 int rtcl_register_clkhw(int clk_idx)
611 {
612 int ret;
613 struct clk *clk;
614 struct clk_init_data hw_init = { };
615 struct clk_parent_data parent_data = { };
616 struct rtcl_clk *rclk = &rtcl_ccu->clks[clk_idx];
617
618 rclk->idx = clk_idx;
619 rclk->hw.init = &hw_init;
620
621 parent_data.fw_name = rtcl_clk_info[clk_idx].parent_name[rtcl_ccu->soc];
622
623 hw_init.num_parents = 1;
624 hw_init.ops = &rtcl_clk_ops;
625 hw_init.parent_data = &parent_data;
626 hw_init.name = rtcl_clk_info[clk_idx].name;
627
628 ret = of_clk_hw_register(rtcl_ccu->np, &rclk->hw);
629 if (ret)
630 return ret;
631
632 clk_hw_register_clkdev(&rclk->hw, rtcl_clk_info[clk_idx].name, NULL);
633
634 clk = clk_get(NULL, rtcl_clk_info[clk_idx].name);
635 rclk->startup = clk_get_rate(clk);
636 clk_put(clk);
637
638 switch (clk_idx) {
639 case CLK_CPU:
640 rclk->min = rtcl_round_set[rtcl_ccu->soc][clk_idx].min;
641 rclk->max = rtcl_round_set[rtcl_ccu->soc][clk_idx].max;
642 break;
643 default:
644 /*
645 * TODO: This driver supports PLL reclocking and nothing else. Additional
646 * required steps for non CPU PLLs are missing. E.g. if we want to change memory
647 * clocks the right way we must adapt a lot of other settings. This includes
648 * MCR and DTRx timing registers (0xb80001000, 0xb8001008, ...) and a DLL reset
649 * so that hardware operates in the allowed limits. This is far too complex
650 * without official support. Avoid this for now.
651 */
652 rclk->min = rclk->max = rclk->startup;
653 break;
654 }
655
656 return 0;
657 }
658
659 static struct clk_hw *rtcl_get_clkhw(struct of_phandle_args *clkspec, void *prv)
660 {
661 unsigned int idx = clkspec->args[0];
662
663 if (idx >= CLK_COUNT) {
664 pr_err("%s: Invalid index %u\n", __func__, idx);
665 return ERR_PTR(-EINVAL);
666 }
667
668 return &rtcl_ccu->clks[idx].hw;
669 }
670
671 static int rtcl_ccu_register_clocks(void)
672 {
673 struct clk *clk;
674 int clk_idx, ret;
675
676 clk = clk_register_fixed_rate(NULL, "xtal_clk", NULL, 0, RTCL_XTAL_RATE);
677 clk_register_clkdev(clk, "xtal_clk", NULL);
678
679 for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) {
680 ret = rtcl_register_clkhw(clk_idx);
681 if (ret) {
682 pr_err("%s: Couldn't register %s clock\n",
683 __func__, rtcl_clk_info[clk_idx].display_name);
684 goto err_hw_unregister;
685 }
686 }
687
688 ret = of_clk_add_hw_provider(rtcl_ccu->np, rtcl_get_clkhw, rtcl_ccu);
689 if (ret) {
690 pr_err("%s: Couldn't register clock provider of %s\n",
691 __func__, of_node_full_name(rtcl_ccu->np));
692 goto err_hw_unregister;
693 }
694
695 return 0;
696
697 err_hw_unregister:
698 for (--clk_idx; clk_idx >= 0; --clk_idx)
699 clk_hw_unregister(&rtcl_ccu->clks[clk_idx].hw);
700
701 return ret;
702 }
703
704 int rtcl_init_sram(void)
705 {
706 struct gen_pool *sram_pool;
707 phys_addr_t sram_pbase;
708 unsigned long sram_vbase;
709 struct device_node *node;
710 struct platform_device *pdev = NULL;
711 void *dram_start;
712 int dram_size;
713 const char *wrn = ", rate setting disabled.\n";
714
715 switch (rtcl_ccu->soc) {
716 case RTCL_SOC838X:
717 dram_start = &rtcl_838x_dram_start;
718 dram_size = rtcl_838x_dram_size;
719 break;
720 case RTCL_SOC839X:
721 dram_start = &rtcl_839x_dram_start;
722 dram_size = rtcl_839x_dram_size;
723 break;
724 case RTCL_SOC930X:
725 dram_start = &rtcl_930x_dram_start;
726 dram_size = rtcl_930x_dram_size;
727 break;
728 default:
729 return -ENXIO;
730 }
731
732 for_each_compatible_node(node, NULL, "mmio-sram") {
733 pdev = of_find_device_by_node(node);
734 if (pdev) {
735 of_node_put(node);
736 break;
737 }
738 }
739
740 if (!pdev) {
741 dev_warn(&rtcl_ccu->pdev->dev, "no SRAM device found%s", wrn);
742 return -ENXIO;
743 }
744
745 sram_pool = gen_pool_get(&pdev->dev, NULL);
746 if (!sram_pool) {
747 dev_warn(&rtcl_ccu->pdev->dev, "SRAM pool unavailable%s", wrn);
748 goto err_put_device;
749 }
750
751 sram_vbase = gen_pool_alloc(sram_pool, dram_size);
752 if (!sram_vbase) {
753 dev_warn(&rtcl_ccu->pdev->dev, "can not allocate SRAM%s", wrn);
754 goto err_put_device;
755 }
756
757 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_vbase);
758 memcpy((void *)sram_pbase, dram_start, dram_size);
759 flush_icache_range((unsigned long)sram_pbase, (unsigned long)(sram_pbase + dram_size));
760
761 switch (rtcl_ccu->soc) {
762 case RTCL_SOC838X:
763 RTCL_SRAM_FUNC(838x, sram_pbase, set_rate);
764 break;
765 case RTCL_SOC839X:
766 RTCL_SRAM_FUNC(839x, sram_pbase, set_rate);
767 break;
768 case RTCL_SOC930X:
769 RTCL_SRAM_FUNC(930x, sram_pbase, set_rate);
770 break;
771 }
772
773 rtcl_ccu->sram.pmark = (int *)((void *)sram_pbase + (dram_size - 4));
774 rtcl_ccu->sram.vbase = sram_vbase;
775
776 return 0;
777
778 err_put_device:
779 put_device(&pdev->dev);
780
781 return -ENXIO;
782 }
783
784 void rtcl_ccu_log_early(void)
785 {
786 int clk_idx;
787 char meminfo[80], clkinfo[255], msg[255] = "rtl83xx-clk: initialized";
788
789 sprintf(meminfo, " (%d Bit DDR%d)", rtcl_ccu->dram.buswidth, rtcl_ccu->dram.type);
790 for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) {
791 sprintf(clkinfo, ", %s %lu MHz", rtcl_clk_info[clk_idx].display_name,
792 rtcl_ccu->clks[clk_idx].startup / 1000000);
793 if (clk_idx == CLK_MEM)
794 strcat(clkinfo, meminfo);
795 strcat(msg, clkinfo);
796 }
797 pr_info("%s\n", msg);
798 }
799
800 void rtcl_ccu_log_late(void)
801 {
802 int clk_idx;
803 struct rtcl_clk *rclk;
804 bool overclock = false;
805 char clkinfo[80], msg[255] = "rate setting enabled";
806
807 for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) {
808 rclk = &rtcl_ccu->clks[clk_idx];
809 if (rclk->min == rclk->max)
810 continue;
811 overclock |= rclk->max > rclk->startup;
812 sprintf(clkinfo, ", %s %lu-%lu MHz", rtcl_clk_info[clk_idx].display_name,
813 rclk->min / 1000000, rclk->max / 1000000);
814 strcat(msg, clkinfo);
815 }
816 if (overclock)
817 strcat(msg, ", OVERCLOCK AT OWN RISK");
818
819 dev_info(&rtcl_ccu->pdev->dev, "%s\n", msg);
820 }
821
822 /*
823 * Early registration: This module provides core startup clocks that are needed
824 * for generic SOC init and for further builtin devices (e.g. UART). Register
825 * asap via clock framework.
826 */
827
828 static void __init rtcl_probe_early(struct device_node *np)
829 {
830 if (rtcl_ccu_create(np))
831 return;
832
833 rtcl_unlock_registers();
834 if (rtcl_ccu_register_clocks())
835 kfree(rtcl_ccu);
836 else
837 rtcl_ccu_log_early();
838 }
839
840 CLK_OF_DECLARE_DRIVER(rtl838x_clk, "realtek,rtl8380-clock", rtcl_probe_early);
841 CLK_OF_DECLARE_DRIVER(rtl839x_clk, "realtek,rtl8390-clock", rtcl_probe_early);
842 CLK_OF_DECLARE_DRIVER(rtl930x_clk, "realtek,rtl9300-clock", rtcl_probe_early);
843
844 /*
845 * Late registration: Finally register as normal platform driver. At this point
846 * we can make use of other modules like SRAM.
847 */
848
849 static const struct of_device_id rtcl_dt_ids[] = {
850 { .compatible = "realtek,rtl8380-clock" },
851 { .compatible = "realtek,rtl8390-clock" },
852 { .compatible = "realtek,rtl9300-clock" },
853 {}
854 };
855
856 static int rtcl_probe_late(struct platform_device *pdev)
857 {
858 int ret;
859
860 if (!rtcl_ccu) {
861 dev_err(&pdev->dev, "early initialization not run");
862 return -ENXIO;
863 }
864 rtcl_ccu->pdev = pdev;
865 ret = rtcl_init_sram();
866 if (ret)
867 return ret;
868
869 rtcl_ccu_log_late();
870
871 return 0;
872 }
873
874 static struct platform_driver rtcl_platform_driver = {
875 .driver = {
876 .name = "rtl83xx-clk",
877 .of_match_table = rtcl_dt_ids,
878 },
879 .probe = rtcl_probe_late,
880 };
881
882 static int __init rtcl_init_subsys(void)
883 {
884 return platform_driver_register(&rtcl_platform_driver);
885 }
886
887 /*
888 * The driver does not know when SRAM module has finally loaded. With an
889 * arch_initcall() we might overtake SRAM initialization. Be polite and give the
890 * system a little more time.
891 */
892
893 subsys_initcall(rtcl_init_subsys);
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