1 // SPDX-License-Identifier: GPL-2.0-only
3 * Realtek RTL83XX clock driver
4 * Copyright (C) 2022 Markus Stockhausen <markus.stockhausen@gmx.de>
7 #include <asm/cacheflush.h>
8 #include <asm/mipsmtregs.h>
9 #include <dt-bindings/clock/rtl83xx-clk.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/cpu.h>
14 #include <linux/delay.h>
15 #include <linux/genalloc.h>
17 #include <linux/ioport.h>
18 #include <linux/of_address.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
23 #include "clk-rtl83xx.h"
26 * some hardware specific definitions
29 #define RTCL_SOC838X 0
30 #define RTCL_SOC839X 1
41 #define RTCL_XTAL_RATE 25000000
43 #define RTCL_SOC_CLK(soc, clk) ((soc << 8) + clk)
45 static const int rtcl_regs
[RTCL_SOCCNT
][REG_COUNT
][CLK_COUNT
] = {
48 RTL_SW_CORE_BASE
+ RTL838X_PLL_CPU_CTRL0
,
49 RTL_SW_CORE_BASE
+ RTL838X_PLL_MEM_CTRL0
,
50 RTL_SW_CORE_BASE
+ RTL838X_PLL_LXB_CTRL0
,
52 RTL_SW_CORE_BASE
+ RTL838X_PLL_CPU_CTRL1
,
53 RTL_SW_CORE_BASE
+ RTL838X_PLL_MEM_CTRL1
,
54 RTL_SW_CORE_BASE
+ RTL838X_PLL_LXB_CTRL1
58 RTL_SW_CORE_BASE
+ RTL839X_PLL_CPU_CTRL0
,
59 RTL_SW_CORE_BASE
+ RTL839X_PLL_MEM_CTRL0
,
60 RTL_SW_CORE_BASE
+ RTL839X_PLL_LXB_CTRL0
62 RTL_SW_CORE_BASE
+ RTL839X_PLL_CPU_CTRL1
,
63 RTL_SW_CORE_BASE
+ RTL839X_PLL_MEM_CTRL1
,
64 RTL_SW_CORE_BASE
+ RTL839X_PLL_LXB_CTRL1
69 #define RTCL_REG_SET(_rate, _ctrl0, _ctrl1) \
83 * The following configuration tables are valid operation points for their
84 * corresponding PLLs. The magic numbers are precalculated mulitpliers and
85 * dividers to keep the driver simple. They also provide rates outside the
86 * allowed physical specifications. E.g. DDR3 memory has a lower limit of 303
87 * MHz or the CPU might get unstable if set to anything above its startup
88 * frequency. Additionally the Realtek SOCs tend to expect CPU speed larger
89 * than MEM speed larger than LXB speed. The caller or DT configuration must
90 * take care that only valid operating points are selected.
93 static const struct rtcl_reg_set rtcl_838x_cpu_reg_set
[] = {
94 RTCL_REG_SET(300000000, 0x045c, 5),
95 RTCL_REG_SET(325000000, 0x0464, 5),
96 RTCL_REG_SET(350000000, 0x046c, 5),
97 RTCL_REG_SET(375000000, 0x0474, 5),
98 RTCL_REG_SET(400000000, 0x045c, 3),
99 RTCL_REG_SET(425000000, 0x0462, 3),
100 RTCL_REG_SET(450000000, 0x0468, 3),
101 RTCL_REG_SET(475000000, 0x046e, 3),
102 RTCL_REG_SET(500000000, 0x0474, 3),
103 RTCL_REG_SET(525000000, 0x047a, 3),
104 RTCL_REG_SET(550000000, 0x0480, 3),
105 RTCL_REG_SET(575000000, 0x0486, 3),
106 RTCL_REG_SET(600000000, 0x048c, 3),
107 RTCL_REG_SET(625000000, 0x0492, 3)
110 static const struct rtcl_reg_set rtcl_838x_mem_reg_set
[] = {
111 RTCL_REG_SET(200000000, 0x041b, 5),
112 RTCL_REG_SET(225000000, 0x0417, 3),
113 RTCL_REG_SET(250000000, 0x041a, 3),
114 RTCL_REG_SET(275000000, 0x0412, 1),
115 RTCL_REG_SET(300000000, 0x0414, 1),
116 RTCL_REG_SET(325000000, 0x0416, 1),
117 RTCL_REG_SET(350000000, 0x0418, 1),
118 RTCL_REG_SET(375000000, 0x041a, 1)
121 static const struct rtcl_reg_set rtcl_838x_lxb_reg_set
[] = {
122 RTCL_REG_SET(100000000, 0x043c, 0),
123 RTCL_REG_SET(125000000, 0x043c, 0),
124 RTCL_REG_SET(150000000, 0x0450, 5),
125 RTCL_REG_SET(175000000, 0x0450, 5),
126 RTCL_REG_SET(200000000, 0x047c, 0)
129 static const struct rtcl_reg_set rtcl_839x_cpu_reg_set
[] = {
130 RTCL_REG_SET(400000000, 0x0414, 5),
131 RTCL_REG_SET(425000000, 0x041e, 6),
132 RTCL_REG_SET(450000000, 0x0417, 5),
133 RTCL_REG_SET(475000000, 0x0422, 6),
134 RTCL_REG_SET(500000000, 0x041a, 5),
135 RTCL_REG_SET(525000000, 0x0426, 6),
136 RTCL_REG_SET(550000000, 0x0412, 4),
137 RTCL_REG_SET(575000000, 0x042a, 6),
138 RTCL_REG_SET(600000000, 0x0414, 4),
139 RTCL_REG_SET(625000000, 0x042e, 6),
140 RTCL_REG_SET(650000000, 0x0416, 4),
141 RTCL_REG_SET(675000000, 0x0432, 6),
142 RTCL_REG_SET(700000000, 0x0418, 4),
143 RTCL_REG_SET(725000000, 0x0436, 6),
144 RTCL_REG_SET(750000000, 0x0438, 6),
145 RTCL_REG_SET(775000000, 0x043a, 6),
146 RTCL_REG_SET(800000000, 0x043c, 6),
147 RTCL_REG_SET(825000000, 0x043e, 6),
148 RTCL_REG_SET(850000000, 0x0440, 6)
151 static const struct rtcl_reg_set rtcl_839x_mem_reg_set
[] = {
152 RTCL_REG_SET(125000000, 0x041a, 7),
153 RTCL_REG_SET(150000000, 0x0414, 6),
154 RTCL_REG_SET(175000000, 0x0418, 6),
155 RTCL_REG_SET(200000000, 0x041c, 6),
156 RTCL_REG_SET(225000000, 0x0417, 5),
157 RTCL_REG_SET(250000000, 0x041a, 5),
158 RTCL_REG_SET(275000000, 0x0412, 4),
159 RTCL_REG_SET(300000000, 0x0414, 4),
160 RTCL_REG_SET(325000000, 0x0416, 4),
161 RTCL_REG_SET(350000000, 0x0418, 4),
162 RTCL_REG_SET(375000000, 0x041a, 4),
163 RTCL_REG_SET(400000000, 0x041c, 4)
166 static const struct rtcl_reg_set rtcl_839x_lxb_reg_set
[] = {
167 RTCL_REG_SET(50000000, 0x1414, 3),
168 RTCL_REG_SET(100000000, 0x0814, 3),
169 RTCL_REG_SET(150000000, 0x0414, 3),
170 RTCL_REG_SET(200000000, 0x0414, 7)
173 struct rtcl_rtab_set
{
175 const struct rtcl_reg_set
*rset
;
178 #define RTCL_RTAB_SET(_rset) \
180 .count = ARRAY_SIZE(_rset), \
184 static const struct rtcl_rtab_set rtcl_rtab_set
[RTCL_SOCCNT
][CLK_COUNT
] = {
186 RTCL_RTAB_SET(rtcl_838x_cpu_reg_set
),
187 RTCL_RTAB_SET(rtcl_838x_mem_reg_set
),
188 RTCL_RTAB_SET(rtcl_838x_lxb_reg_set
)
190 RTCL_RTAB_SET(rtcl_839x_cpu_reg_set
),
191 RTCL_RTAB_SET(rtcl_839x_mem_reg_set
),
192 RTCL_RTAB_SET(rtcl_839x_lxb_reg_set
)
196 #define RTCL_ROUND_SET(_min, _max, _step) \
203 struct rtcl_round_set
{
209 static const struct rtcl_round_set rtcl_round_set
[RTCL_SOCCNT
][CLK_COUNT
] = {
211 RTCL_ROUND_SET(300000000, 625000000, 25000000),
212 RTCL_ROUND_SET(200000000, 375000000, 25000000),
213 RTCL_ROUND_SET(100000000, 200000000, 25000000)
215 RTCL_ROUND_SET(400000000, 850000000, 25000000),
216 RTCL_ROUND_SET(100000000, 400000000, 25000000),
217 RTCL_ROUND_SET(50000000, 200000000, 50000000)
221 static const int rtcl_divn3
[] = { 2, 3, 4, 6 };
222 static const int rtcl_xdiv
[] = { 2, 4, 2 };
225 * module data structures
228 #define RTCL_CLK_INFO(_idx, _name, _pname, _dname) \
232 .parent_name = _pname, \
233 .display_name = _dname, \
236 struct rtcl_clk_info
{
239 const char *parent_name
;
240 const char *display_name
;
249 unsigned long startup
;
252 static const struct rtcl_clk_info rtcl_clk_info
[CLK_COUNT
] = {
253 RTCL_CLK_INFO(CLK_CPU
, "cpu_clk", "ref_clk", "CPU"),
254 RTCL_CLK_INFO(CLK_MEM
, "mem_clk", "ref_clk", "MEM"),
255 RTCL_CLK_INFO(CLK_LXB
, "lxb_clk", "ref_clk", "LXB")
271 struct rtcl_sram sram
;
272 struct rtcl_dram dram
;
273 struct device_node
*np
;
274 struct platform_device
*pdev
;
275 struct rtcl_clk clks
[CLK_COUNT
];
278 struct rtcl_ccu
*rtcl_ccu
;
280 #define rtcl_hw_to_clk(_hw) container_of(_hw, struct rtcl_clk, hw)
283 * SRAM relocatable assembler functions. The dram() parts point to normal kernel
284 * memory while the sram() parts are the same functions but relocated to SRAM.
287 extern void rtcl_838x_dram_start(void);
288 extern int rtcl_838x_dram_size
;
290 extern void (*rtcl_838x_dram_set_rate
)(int clk_idx
, int ctrl0
, int ctrl1
);
291 static void (*rtcl_838x_sram_set_rate
)(int clk_idx
, int ctrl0
, int ctrl1
);
293 extern void rtcl_839x_dram_start(void);
294 extern int rtcl_839x_dram_size
;
296 extern void (*rtcl_839x_dram_set_rate
)(int clk_idx
, int ctrl0
, int ctrl1
);
297 static void (*rtcl_839x_sram_set_rate
)(int clk_idx
, int ctrl0
, int ctrl1
);
300 * clock setter/getter functions
303 static unsigned long rtcl_recalc_rate(struct clk_hw
*hw
, unsigned long parent_rate
)
305 struct rtcl_clk
*clk
= rtcl_hw_to_clk(hw
);
306 unsigned int read0
, read1
;
307 unsigned int mul1
= 1, mul2
= 1, div1
= 1, div2
= 1, div3
= 1;
308 unsigned int cmu_divn2
, cmu_divn2_selb
, cmu_divn3_sel
;
310 if ((clk
->idx
>= CLK_COUNT
) || (!rtcl_ccu
) || (rtcl_ccu
->soc
>= RTCL_SOCCNT
))
313 read0
= ioread32((void *)rtcl_regs
[rtcl_ccu
->soc
][0][clk
->idx
]);
314 read1
= ioread32((void *)rtcl_regs
[rtcl_ccu
->soc
][1][clk
->idx
]);
316 switch (RTCL_SOC_CLK(rtcl_ccu
->soc
, clk
->idx
)) {
317 case RTCL_SOC_CLK(RTCL_SOC838X
, CLK_LXB
):
318 case RTCL_SOC_CLK(RTCL_SOC838X
, CLK_CPU
):
319 case RTCL_SOC_CLK(RTCL_SOC838X
, CLK_MEM
):
320 cmu_divn2
= RTL83XX_PLL_CTRL0_CMU_DIVN2(read0
) + 4;
321 cmu_divn2_selb
= RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(read1
);
322 cmu_divn3_sel
= rtcl_divn3
[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(read1
)];
324 mul1
= RTL_PLL_CTRL0_CMU_NCODE_IN(read0
) + 4;
325 mul2
= RTL_PLL_CTRL0_CMU_SEL_DIV4(read0
) ? 4 : 1;
326 div1
= 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(read0
);
327 div2
= cmu_divn2_selb
? cmu_divn3_sel
: cmu_divn2
;
328 div3
= rtcl_xdiv
[clk
->idx
];
330 case RTCL_SOC_CLK(RTCL_SOC839X
, CLK_CPU
):
331 case RTCL_SOC_CLK(RTCL_SOC839X
, CLK_MEM
):
332 case RTCL_SOC_CLK(RTCL_SOC839X
, CLK_LXB
):
333 cmu_divn2
= RTL83XX_PLL_CTRL0_CMU_DIVN2(read0
) + 4;
334 cmu_divn2_selb
= RTL839X_PLL_CTRL1_CMU_DIVN2_SELB(read1
);
335 cmu_divn3_sel
= rtcl_divn3
[RTL839X_PLL_CTRL1_CMU_DIVN3_SEL(read1
)];
337 mul1
= RTL_PLL_CTRL0_CMU_NCODE_IN(read0
) + 4;
338 mul2
= RTL_PLL_CTRL0_CMU_SEL_DIV4(read0
) ? 4 : 1;
339 div1
= 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(read0
);
340 div2
= cmu_divn2_selb
? cmu_divn3_sel
: cmu_divn2
;
341 div3
= rtcl_xdiv
[clk
->idx
];
345 * Do the math in a way that interim values stay inside 32 bit bounds
347 return (((parent_rate
/ 16) * mul1
) / (div1
* div2
* div3
)) * mul2
* 16;
350 static int rtcl_838x_set_rate(int clk_idx
, const struct rtcl_reg_set
*reg
)
352 unsigned long irqflags
;
354 * Runtime of this function (including locking)
355 * CPU: up to 14000 cycles / up to 56 us at 250 MHz (half default speed)
357 spin_lock_irqsave(&rtcl_ccu
->lock
, irqflags
);
358 rtcl_838x_sram_set_rate(clk_idx
, reg
->ctrl0
, reg
->ctrl1
);
359 spin_unlock_irqrestore(&rtcl_ccu
->lock
, irqflags
);
364 static int rtcl_839x_set_rate(int clk_idx
, const struct rtcl_reg_set
*reg
)
366 unsigned long vpflags
;
367 unsigned long irqflags
;
369 * Runtime of this function (including locking)
370 * CPU: up to 31000 cycles / up to 89 us at 350 MHz (half default speed)
372 spin_lock_irqsave(&rtcl_ccu
->lock
, irqflags
);
374 rtcl_839x_sram_set_rate(clk_idx
, reg
->ctrl0
, reg
->ctrl1
);
376 spin_unlock_irqrestore(&rtcl_ccu
->lock
, irqflags
);
381 static int rtcl_set_rate(struct clk_hw
*hw
, unsigned long rate
, unsigned long parent_rate
)
384 struct rtcl_clk
*clk
= rtcl_hw_to_clk(hw
);
385 const struct rtcl_rtab_set
*rtab
= &rtcl_rtab_set
[rtcl_ccu
->soc
][clk
->idx
];
386 const struct rtcl_round_set
*round
= &rtcl_round_set
[rtcl_ccu
->soc
][clk
->idx
];
388 if ((parent_rate
!= RTCL_XTAL_RATE
) || (!rtcl_ccu
->sram
.vbase
))
391 * Currently we do not know if SRAM is stable on these devices. Maybe someone
392 * changes memory in this region and does not care about proper allocation. So
393 * check if something might go wrong.
395 if (unlikely(*rtcl_ccu
->sram
.pmark
!= RTL_SRAM_MARKER
)) {
396 dev_err(&rtcl_ccu
->pdev
->dev
, "SRAM code lost\n");
400 tab_idx
= (rate
- round
->min
) / round
->step
;
401 if ((tab_idx
< 0) || (tab_idx
>= rtab
->count
) || (rtab
->rset
[tab_idx
].rate
!= rate
))
404 rtcl_ccu
->clks
[clk
->idx
].rate
= rate
;
406 switch (rtcl_ccu
->soc
) {
408 return rtcl_838x_set_rate(clk
->idx
, &rtab
->rset
[tab_idx
]);
410 return rtcl_839x_set_rate(clk
->idx
, &rtab
->rset
[tab_idx
]);
416 static long rtcl_round_rate(struct clk_hw
*hw
, unsigned long rate
, unsigned long *parent_rate
)
418 struct rtcl_clk
*clk
= rtcl_hw_to_clk(hw
);
419 unsigned long rrate
= max(clk
->min
, min(clk
->max
, rate
));
420 const struct rtcl_round_set
*round
= &rtcl_round_set
[rtcl_ccu
->soc
][clk
->idx
];
422 rrate
= ((rrate
+ (round
->step
>> 1)) / round
->step
) * round
->step
;
423 rrate
-= (rrate
> clk
->max
) ? round
->step
: 0;
424 rrate
+= (rrate
< clk
->min
) ? round
->step
: 0;
430 * Initialization functions to register the CCU and its clocks
433 #define RTCL_SRAM_FUNC(SOC, PBASE, FN) ({ \
434 rtcl_##SOC##_sram_##FN = ((void *)&rtcl_##SOC##_dram_##FN \
435 - (void *)&rtcl_##SOC##_dram_start) \
438 static const struct clk_ops rtcl_clk_ops
= {
439 .set_rate
= rtcl_set_rate
,
440 .round_rate
= rtcl_round_rate
,
441 .recalc_rate
= rtcl_recalc_rate
,
444 static void rtcl_unlock_registers(void)
448 if (rtcl_ccu
->soc
!= RTCL_SOC838X
)
451 * Some RTL838X devices are shipped with register access locked. In this case
452 * we cannot read and/or write to LXB or SW PLL registers. As there is no real
453 * benefit of always unlocking/locking these registers just open up everything.
455 enable
= RTL838X_INT_RW_CTRL_READ_EN
| RTL838X_INT_RW_CTRL_WRITE_EN
;
456 reg
= ioread32((void *)RTL_SW_CORE_BASE
+ RTL838X_INT_RW_CTRL
);
457 if ((reg
& enable
) != enable
) {
459 iowrite32(reg
, (void *)RTL_SW_CORE_BASE
+ RTL838X_INT_RW_CTRL
);
460 pr_warn("%s: registers unlocked\n", __func__
);
464 static int rtcl_ccu_create(struct device_node
*np
)
468 if (of_device_is_compatible(np
, "realtek,rtl8380-clock"))
470 else if (of_device_is_compatible(np
, "realtek,rtl8390-clock"))
475 rtcl_ccu
= kzalloc(sizeof(*rtcl_ccu
), GFP_KERNEL
);
476 if (IS_ERR(rtcl_ccu
))
481 rtcl_ccu
->dram
.type
= RTL_MC_MCR_DRAMTYPE(ioread32((void *)RTL_SOC_BASE
+ RTL_MC_MCR
));
482 rtcl_ccu
->dram
.buswidth
= RTL_MC_DCR_BUSWIDTH(ioread32((void *)RTL_SOC_BASE
+ RTL_MC_DCR
));
483 spin_lock_init(&rtcl_ccu
->lock
);
488 int rtcl_register_clkhw(int clk_idx
)
492 struct clk_init_data hw_init
= { };
493 struct rtcl_clk
*rclk
= &rtcl_ccu
->clks
[clk_idx
];
494 struct clk_parent_data parent_data
= { .fw_name
= rtcl_clk_info
[clk_idx
].parent_name
};
497 rclk
->hw
.init
= &hw_init
;
499 hw_init
.num_parents
= 1;
500 hw_init
.ops
= &rtcl_clk_ops
;
501 hw_init
.parent_data
= &parent_data
;
502 hw_init
.name
= rtcl_clk_info
[clk_idx
].name
;
504 ret
= of_clk_hw_register(rtcl_ccu
->np
, &rclk
->hw
);
508 clk_hw_register_clkdev(&rclk
->hw
, rtcl_clk_info
[clk_idx
].name
, NULL
);
510 clk
= clk_get(NULL
, rtcl_clk_info
[clk_idx
].name
);
511 rclk
->startup
= clk_get_rate(clk
);
516 rclk
->min
= rtcl_round_set
[rtcl_ccu
->soc
][clk_idx
].min
;
517 rclk
->max
= rtcl_round_set
[rtcl_ccu
->soc
][clk_idx
].max
;
521 * TODO: This driver supports PLL reclocking and nothing else. Additional
522 * required steps for non CPU PLLs are missing. E.g. if we want to change memory
523 * clocks the right way we must adapt a lot of other settings. This includes
524 * MCR and DTRx timing registers (0xb80001000, 0xb8001008, ...) and a DLL reset
525 * so that hardware operates in the allowed limits. This is far too complex
526 * without official support. Avoid this for now.
528 rclk
->min
= rclk
->max
= rclk
->startup
;
535 static struct clk_hw
*rtcl_get_clkhw(struct of_phandle_args
*clkspec
, void *prv
)
537 unsigned int idx
= clkspec
->args
[0];
539 if (idx
>= CLK_COUNT
) {
540 pr_err("%s: Invalid index %u\n", __func__
, idx
);
541 return ERR_PTR(-EINVAL
);
544 return &rtcl_ccu
->clks
[idx
].hw
;
547 static int rtcl_ccu_register_clocks(void)
551 for (clk_idx
= 0; clk_idx
< CLK_COUNT
; clk_idx
++) {
552 ret
= rtcl_register_clkhw(clk_idx
);
554 pr_err("%s: Couldn't register %s clock\n",
555 __func__
, rtcl_clk_info
[clk_idx
].display_name
);
556 goto err_hw_unregister
;
560 ret
= of_clk_add_hw_provider(rtcl_ccu
->np
, rtcl_get_clkhw
, rtcl_ccu
);
562 pr_err("%s: Couldn't register clock provider of %s\n",
563 __func__
, of_node_full_name(rtcl_ccu
->np
));
564 goto err_hw_unregister
;
570 for (--clk_idx
; clk_idx
>= 0; --clk_idx
)
571 clk_hw_unregister(&rtcl_ccu
->clks
[clk_idx
].hw
);
576 int rtcl_init_sram(void)
578 struct gen_pool
*sram_pool
;
579 phys_addr_t sram_pbase
;
580 unsigned long sram_vbase
;
581 struct device_node
*node
;
582 struct platform_device
*pdev
= NULL
;
585 const char *wrn
= ", rate setting disabled.\n";
587 switch (rtcl_ccu
->soc
) {
589 dram_start
= &rtcl_838x_dram_start
;
590 dram_size
= rtcl_838x_dram_size
;
593 dram_start
= &rtcl_839x_dram_start
;
594 dram_size
= rtcl_839x_dram_size
;
600 for_each_compatible_node(node
, NULL
, "mmio-sram") {
601 pdev
= of_find_device_by_node(node
);
609 dev_warn(&rtcl_ccu
->pdev
->dev
, "no SRAM device found%s", wrn
);
613 sram_pool
= gen_pool_get(&pdev
->dev
, NULL
);
615 dev_warn(&rtcl_ccu
->pdev
->dev
, "SRAM pool unavailable%s", wrn
);
619 sram_vbase
= gen_pool_alloc(sram_pool
, dram_size
);
621 dev_warn(&rtcl_ccu
->pdev
->dev
, "can not allocate SRAM%s", wrn
);
625 sram_pbase
= gen_pool_virt_to_phys(sram_pool
, sram_vbase
);
626 memcpy((void *)sram_pbase
, dram_start
, dram_size
);
627 flush_icache_range((unsigned long)sram_pbase
, (unsigned long)(sram_pbase
+ dram_size
));
629 switch (rtcl_ccu
->soc
) {
631 RTCL_SRAM_FUNC(838x
, sram_pbase
, set_rate
);
634 RTCL_SRAM_FUNC(839x
, sram_pbase
, set_rate
);
638 rtcl_ccu
->sram
.pmark
= (int *)((void *)sram_pbase
+ (dram_size
- 4));
639 rtcl_ccu
->sram
.vbase
= sram_vbase
;
644 put_device(&pdev
->dev
);
649 void rtcl_ccu_log_early(void)
652 char meminfo
[80], clkinfo
[255], msg
[255] = "rtl83xx-clk: initialized";
654 sprintf(meminfo
, " (%d Bit DDR%d)", rtcl_ccu
->dram
.buswidth
, rtcl_ccu
->dram
.type
);
655 for (clk_idx
= 0; clk_idx
< CLK_COUNT
; clk_idx
++) {
656 sprintf(clkinfo
, ", %s %lu MHz", rtcl_clk_info
[clk_idx
].display_name
,
657 rtcl_ccu
->clks
[clk_idx
].startup
/ 1000000);
658 if (clk_idx
== CLK_MEM
)
659 strcat(clkinfo
, meminfo
);
660 strcat(msg
, clkinfo
);
662 pr_info("%s\n", msg
);
665 void rtcl_ccu_log_late(void)
668 struct rtcl_clk
*rclk
;
669 bool overclock
= false;
670 char clkinfo
[80], msg
[255] = "rate setting enabled";
672 for (clk_idx
= 0; clk_idx
< CLK_COUNT
; clk_idx
++) {
673 rclk
= &rtcl_ccu
->clks
[clk_idx
];
674 overclock
|= rclk
->max
> rclk
->startup
;
675 sprintf(clkinfo
, ", %s %lu-%lu MHz", rtcl_clk_info
[clk_idx
].display_name
,
676 rclk
->min
/ 1000000, rclk
->max
/ 1000000);
677 strcat(msg
, clkinfo
);
680 strcat(msg
, ", OVERCLOCK AT OWN RISK");
682 dev_info(&rtcl_ccu
->pdev
->dev
, "%s\n", msg
);
686 * Early registration: This module provides core startup clocks that are needed
687 * for generic SOC init and for further builtin devices (e.g. UART). Register
688 * asap via clock framework.
691 static void __init
rtcl_probe_early(struct device_node
*np
)
693 if (rtcl_ccu_create(np
))
696 rtcl_unlock_registers();
697 if (rtcl_ccu_register_clocks())
700 rtcl_ccu_log_early();
703 CLK_OF_DECLARE_DRIVER(rtl838x_clk
, "realtek,rtl8380-clock", rtcl_probe_early
);
704 CLK_OF_DECLARE_DRIVER(rtl839x_clk
, "realtek,rtl8390-clock", rtcl_probe_early
);
707 * Late registration: Finally register as normal platform driver. At this point
708 * we can make use of other modules like SRAM.
711 static const struct of_device_id rtcl_dt_ids
[] = {
712 { .compatible
= "realtek,rtl8380-clock" },
713 { .compatible
= "realtek,rtl8390-clock" },
717 static int rtcl_probe_late(struct platform_device
*pdev
)
722 dev_err(&pdev
->dev
, "early initialization not run");
725 rtcl_ccu
->pdev
= pdev
;
726 ret
= rtcl_init_sram();
735 static struct platform_driver rtcl_platform_driver
= {
737 .name
= "rtl83xx-clk",
738 .of_match_table
= rtcl_dt_ids
,
740 .probe
= rtcl_probe_late
,
743 static int __init
rtcl_init_subsys(void)
745 return platform_driver_register(&rtcl_platform_driver
);
749 * The driver does not know when SRAM module has finally loaded. With an
750 * arch_initcall() we might overtake SRAM initialization. Be polite and give the
751 * system a little more time.
754 subsys_initcall(rtcl_init_subsys
);