target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Realtek RTL83XX clock driver
   4  * Copyright (C) 2022 Markus Stockhausen <markus.stockhausen@gmx.de>
   5  */
   6
   7 #include <asm/cacheflush.h>
   8 #include <asm/mipsmtregs.h>
   9 #include <dt-bindings/clock/rtl83xx-clk.h>
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/cpu.h>
  14 #include <linux/delay.h>
  15 #include <linux/genalloc.h>
  16 #include <linux/io.h>
  17 #include <linux/ioport.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22
  23 #include "clk-rtl83xx.h"
  24
  25 /*
  26  * some hardware specific definitions
  27  */
  28
  29 #define RTCL_SOC838X            0
  30 #define RTCL_SOC839X            1
  31 #define RTCL_SOCCNT             2
  32
  33 #define RTCL_DDR1               1
  34 #define RTCL_DDR2               2
  35 #define RTCL_DDR3               3
  36
  37 #define RTCL_REGCNT             2
  38
  39 #define RTCL_XTAL_RATE          25000000
  40
  41 #define RTCL_SOC_CLK(soc, clk)  ((soc << 8) + clk)
  42
  43 static const int rtcl_regs[RTCL_SOCCNT][RTCL_REGCNT][CLK_COUNT] = {
  44         {
  45                 {
  46                         RTL_SW_CORE_BASE + RTL838X_PLL_CPU_CTRL0,
  47                         RTL_SW_CORE_BASE + RTL838X_PLL_MEM_CTRL0,
  48                         RTL_SW_CORE_BASE + RTL838X_PLL_LXB_CTRL0,
  49                 }, {
  50                         RTL_SW_CORE_BASE + RTL838X_PLL_CPU_CTRL1,
  51                         RTL_SW_CORE_BASE + RTL838X_PLL_MEM_CTRL1,
  52                         RTL_SW_CORE_BASE + RTL838X_PLL_LXB_CTRL1
  53                 }
  54         }, {
  55                 {
  56                         RTL_SW_CORE_BASE + RTL839X_PLL_CPU_CTRL0,
  57                         RTL_SW_CORE_BASE + RTL839X_PLL_MEM_CTRL0,
  58                         RTL_SW_CORE_BASE + RTL839X_PLL_LXB_CTRL0
  59                 }, {
  60                         RTL_SW_CORE_BASE + RTL839X_PLL_CPU_CTRL1,
  61                         RTL_SW_CORE_BASE + RTL839X_PLL_MEM_CTRL1,
  62                         RTL_SW_CORE_BASE + RTL839X_PLL_LXB_CTRL1
  63                 }
  64         }
  65 };
  66
  67 #define RTCL_REG_SET(_rate, _ctrl0, _ctrl1)     \
  68         {                                       \
  69                 .rate = _rate,                  \
  70                 .ctrl0 = _ctrl0,                \
  71                 .ctrl1 = _ctrl1,                \
  72         }
  73
  74 struct rtcl_reg_set {
  75         unsigned long rate;
  76         unsigned int ctrl0;
  77         unsigned int ctrl1;
  78 };
  79
  80 /*
  81  * The following configuration tables are valid operation points for their
  82  * corresponding PLLs. The magic numbers are precalculated mulitpliers and
  83  * dividers to keep the driver simple. They also provide rates outside the
  84  * allowed physical specifications. E.g. DDR3 memory has a lower limit of 303
  85  * MHz or the CPU might get unstable if set to anything above its startup
  86  * frequency. Additionally the Realtek SOCs tend to expect CPU speed larger
  87  * than MEM speed larger than LXB speed. The caller or DT configuration must
  88  * take care that only valid operating points are selected.
  89  */
  90
  91 static const struct rtcl_reg_set rtcl_838x_cpu_reg_set[] = {
  92         RTCL_REG_SET(300000000, 0x045c, 5),
  93         RTCL_REG_SET(325000000, 0x0464, 5),
  94         RTCL_REG_SET(350000000, 0x046c, 5),
  95         RTCL_REG_SET(375000000, 0x0474, 5),
  96         RTCL_REG_SET(400000000, 0x045c, 3),
  97         RTCL_REG_SET(425000000, 0x0462, 3),
  98         RTCL_REG_SET(450000000, 0x0468, 3),
  99         RTCL_REG_SET(475000000, 0x046e, 3),
 100         RTCL_REG_SET(500000000, 0x0474, 3),
 101         RTCL_REG_SET(525000000, 0x047a, 3),
 102         RTCL_REG_SET(550000000, 0x0480, 3),
 103         RTCL_REG_SET(575000000, 0x0486, 3),
 104         RTCL_REG_SET(600000000, 0x048c, 3),
 105         RTCL_REG_SET(625000000, 0x0492, 3)
 106 };
 107
 108 static const struct rtcl_reg_set rtcl_838x_mem_reg_set[] = {
 109         RTCL_REG_SET(200000000, 0x041b, 5),
 110         RTCL_REG_SET(225000000, 0x0417, 3),
 111         RTCL_REG_SET(250000000, 0x041a, 3),
 112         RTCL_REG_SET(275000000, 0x0412, 1),
 113         RTCL_REG_SET(300000000, 0x0414, 1),
 114         RTCL_REG_SET(325000000, 0x0416, 1),
 115         RTCL_REG_SET(350000000, 0x0418, 1),
 116         RTCL_REG_SET(375000000, 0x041a, 1)
 117 };
 118
 119 static const struct rtcl_reg_set rtcl_838x_lxb_reg_set[] = {
 120         RTCL_REG_SET(100000000, 0x043c, 0),
 121         RTCL_REG_SET(125000000, 0x043c, 0),
 122         RTCL_REG_SET(150000000, 0x0450, 5),
 123         RTCL_REG_SET(175000000, 0x0450, 5),
 124         RTCL_REG_SET(200000000, 0x047c, 0)
 125 };
 126
 127 static const struct rtcl_reg_set rtcl_839x_cpu_reg_set[] = {
 128         RTCL_REG_SET(400000000, 0x0414, 5),
 129         RTCL_REG_SET(425000000, 0x041e, 6),
 130         RTCL_REG_SET(450000000, 0x0417, 5),
 131         RTCL_REG_SET(475000000, 0x0422, 6),
 132         RTCL_REG_SET(500000000, 0x041a, 5),
 133         RTCL_REG_SET(525000000, 0x0426, 6),
 134         RTCL_REG_SET(550000000, 0x0412, 4),
 135         RTCL_REG_SET(575000000, 0x042a, 6),
 136         RTCL_REG_SET(600000000, 0x0414, 4),
 137         RTCL_REG_SET(625000000, 0x042e, 6),
 138         RTCL_REG_SET(650000000, 0x0416, 4),
 139         RTCL_REG_SET(675000000, 0x0432, 6),
 140         RTCL_REG_SET(700000000, 0x0418, 4),
 141         RTCL_REG_SET(725000000, 0x0436, 6),
 142         RTCL_REG_SET(750000000, 0x0438, 6),
 143         RTCL_REG_SET(775000000, 0x043a, 6),
 144         RTCL_REG_SET(800000000, 0x043c, 6),
 145         RTCL_REG_SET(825000000, 0x043e, 6),
 146         RTCL_REG_SET(850000000, 0x0440, 6)
 147 };
 148
 149 static const struct rtcl_reg_set rtcl_839x_mem_reg_set[] = {
 150         RTCL_REG_SET(125000000, 0x041a, 7),
 151         RTCL_REG_SET(150000000, 0x0414, 6),
 152         RTCL_REG_SET(175000000, 0x0418, 6),
 153         RTCL_REG_SET(200000000, 0x041c, 6),
 154         RTCL_REG_SET(225000000, 0x0417, 5),
 155         RTCL_REG_SET(250000000, 0x041a, 5),
 156         RTCL_REG_SET(275000000, 0x0412, 4),
 157         RTCL_REG_SET(300000000, 0x0414, 4),
 158         RTCL_REG_SET(325000000, 0x0416, 4),
 159         RTCL_REG_SET(350000000, 0x0418, 4),
 160         RTCL_REG_SET(375000000, 0x041a, 4),
 161         RTCL_REG_SET(400000000, 0x041c, 4)
 162 };
 163
 164 static const struct rtcl_reg_set rtcl_839x_lxb_reg_set[] = {
 165         RTCL_REG_SET(50000000, 0x1414, 3),
 166         RTCL_REG_SET(100000000, 0x0814, 3),
 167         RTCL_REG_SET(150000000, 0x0414, 3),
 168         RTCL_REG_SET(200000000, 0x0414, 7)
 169 };
 170
 171 struct rtcl_rtab_set {
 172         int count;
 173         const struct rtcl_reg_set *rset;
 174 };
 175
 176 #define RTCL_RTAB_SET(_rset) { .count = ARRAY_SIZE(_rset), .rset = _rset }
 177
 178 static const struct rtcl_rtab_set rtcl_rtab_set[RTCL_SOCCNT][CLK_COUNT] = {
 179         {
 180                 RTCL_RTAB_SET(rtcl_838x_cpu_reg_set),
 181                 RTCL_RTAB_SET(rtcl_838x_mem_reg_set),
 182                 RTCL_RTAB_SET(rtcl_838x_lxb_reg_set)
 183         }, {
 184                 RTCL_RTAB_SET(rtcl_839x_cpu_reg_set),
 185                 RTCL_RTAB_SET(rtcl_839x_mem_reg_set),
 186                 RTCL_RTAB_SET(rtcl_839x_lxb_reg_set)
 187         }
 188 };
 189
 190 #define RTCL_ROUND_SET(_min, _max, _s) { .min = _min, .max = _max, .step = _s }
 191
 192 struct rtcl_round_set {
 193         unsigned long min;
 194         unsigned long max;
 195         unsigned long step;
 196 };
 197
 198 static const struct rtcl_round_set rtcl_round_set[RTCL_SOCCNT][CLK_COUNT] = {
 199         {
 200                 RTCL_ROUND_SET(300000000,       625000000,      25000000),
 201                 RTCL_ROUND_SET(200000000,       375000000,      25000000),
 202                 RTCL_ROUND_SET(100000000,       200000000,      25000000)
 203         }, {
 204                 RTCL_ROUND_SET(400000000,       850000000,      25000000),
 205                 RTCL_ROUND_SET(100000000,       400000000,      25000000),
 206                 RTCL_ROUND_SET(50000000,        200000000,      50000000)
 207         }
 208 };
 209
 210 static const int rtcl_divn3[] = { 2, 3, 4, 6 };
 211 static const int rtcl_xdiv[] = { 2, 4, 2 };
 212
 213 /*
 214  * module data structures
 215  */
 216
 217 #define RTCL_CLK_INFO(_idx, _name, _pname, _dname)      \
 218         {                                               \
 219                 .idx = _idx,                            \
 220                 .name = _name,                          \
 221                 .parent_name = _pname,                  \
 222                 .display_name = _dname,                 \
 223         }
 224
 225 struct rtcl_clk_info {
 226         unsigned int idx;
 227         const char *name;
 228         const char *parent_name;
 229         const char *display_name;
 230 };
 231
 232 struct rtcl_clk {
 233         struct clk_hw hw;
 234         unsigned int idx;
 235         unsigned long min;
 236         unsigned long max;
 237         unsigned long startup;
 238 };
 239
 240 static const struct rtcl_clk_info rtcl_clk_info[CLK_COUNT] = {
 241         RTCL_CLK_INFO(CLK_CPU, "cpu_clk", "xtal_clk", "CPU"),
 242         RTCL_CLK_INFO(CLK_MEM, "mem_clk", "xtal_clk", "MEM"),
 243         RTCL_CLK_INFO(CLK_LXB, "lxb_clk", "xtal_clk", "LXB")
 244 };
 245
 246 struct rtcl_dram {
 247         int type;
 248         int buswidth;
 249 };
 250
 251 struct rtcl_sram {
 252         int *pmark;
 253         unsigned long vbase;
 254 };
 255
 256 struct rtcl_ccu {
 257         spinlock_t lock;
 258         unsigned int soc;
 259         struct rtcl_sram sram;
 260         struct rtcl_dram dram;
 261         struct device_node *np;
 262         struct platform_device *pdev;
 263         struct rtcl_clk clks[CLK_COUNT];
 264 };
 265
 266 struct rtcl_ccu *rtcl_ccu;
 267
 268 #define rtcl_hw_to_clk(_hw) container_of(_hw, struct rtcl_clk, hw)
 269
 270 /*
 271  * SRAM relocatable assembler functions. The dram() parts point to normal kernel
 272  * memory while the sram() parts are the same functions but relocated to SRAM.
 273  */
 274
 275 extern void     rtcl_838x_dram_start(void);
 276 extern int      rtcl_838x_dram_size;
 277
 278 extern void     rtcl_838x_dram_set_rate(int clk_idx, int ctrl0, int ctrl1);
 279 static void     (*rtcl_838x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1);
 280
 281 extern void     rtcl_839x_dram_start(void);
 282 extern int      rtcl_839x_dram_size;
 283
 284 extern void     rtcl_839x_dram_set_rate(int clk_idx, int ctrl0, int ctrl1);
 285 static void     (*rtcl_839x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1);
 286
 287 /*
 288  * clock setter/getter functions
 289  */
 290
 291 static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 292 {
 293         struct rtcl_clk *clk = rtcl_hw_to_clk(hw);
 294         unsigned int read0, read1;
 295         unsigned int mul1 = 1, mul2 = 1, div1 = 1, div2 = 1, div3 = 1;
 296         unsigned int cmu_divn2, cmu_divn2_selb, cmu_divn3_sel;
 297
 298         if ((clk->idx >= CLK_COUNT) || (!rtcl_ccu) || (rtcl_ccu->soc >= RTCL_SOCCNT))
 299                 return 0;
 300
 301         read0 = ioread32((void *)rtcl_regs[rtcl_ccu->soc][0][clk->idx]);
 302         read1 = ioread32((void *)rtcl_regs[rtcl_ccu->soc][1][clk->idx]);
 303
 304         switch (RTCL_SOC_CLK(rtcl_ccu->soc, clk->idx)) {
 305         case RTCL_SOC_CLK(RTCL_SOC838X, CLK_LXB):
 306         case RTCL_SOC_CLK(RTCL_SOC838X, CLK_CPU):
 307         case RTCL_SOC_CLK(RTCL_SOC838X, CLK_MEM):
 308                 cmu_divn2 = RTL83XX_PLL_CTRL0_CMU_DIVN2(read0) + 4;
 309                 cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(read1);
 310                 cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(read1)];
 311
 312                 mul1 = RTL_PLL_CTRL0_CMU_NCODE_IN(read0) + 4;
 313                 mul2 = RTL_PLL_CTRL0_CMU_SEL_DIV4(read0) ? 4 : 1;
 314                 div1 = 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(read0);
 315                 div2 = cmu_divn2_selb ? cmu_divn3_sel : cmu_divn2;
 316                 div3 = rtcl_xdiv[clk->idx];
 317                 break;
 318         case RTCL_SOC_CLK(RTCL_SOC839X, CLK_CPU):
 319         case RTCL_SOC_CLK(RTCL_SOC839X, CLK_MEM):
 320         case RTCL_SOC_CLK(RTCL_SOC839X, CLK_LXB):
 321                 cmu_divn2 = RTL83XX_PLL_CTRL0_CMU_DIVN2(read0) + 4;
 322                 cmu_divn2_selb = RTL839X_PLL_CTRL1_CMU_DIVN2_SELB(read1);
 323                 cmu_divn3_sel = rtcl_divn3[RTL839X_PLL_CTRL1_CMU_DIVN3_SEL(read1)];
 324
 325                 mul1 = RTL_PLL_CTRL0_CMU_NCODE_IN(read0) + 4;
 326                 mul2 = RTL_PLL_CTRL0_CMU_SEL_DIV4(read0) ? 4 : 1;
 327                 div1 = 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(read0);
 328                 div2 = cmu_divn2_selb ? cmu_divn3_sel : cmu_divn2;
 329                 div3 = rtcl_xdiv[clk->idx];
 330                 break;
 331         }
 332 /*
 333  * Do the math in a way that interim values stay inside 32 bit bounds
 334  */
 335         return (((parent_rate / 16) * mul1) / (div1 * div2 * div3)) * mul2 * 16;
 336 }
 337
 338 static int rtcl_838x_set_rate(int clk_idx, const struct rtcl_reg_set *reg)
 339 {
 340         unsigned long irqflags;
 341 /*
 342  * Runtime of this function (including locking)
 343  * CPU: up to 14000 cycles / up to 56 us at 250 MHz (half default speed)
 344  */
 345         spin_lock_irqsave(&rtcl_ccu->lock, irqflags);
 346         rtcl_838x_sram_set_rate(clk_idx, reg->ctrl0, reg->ctrl1);
 347         spin_unlock_irqrestore(&rtcl_ccu->lock, irqflags);
 348
 349         return 0;
 350 }
 351
 352 static int rtcl_839x_set_rate(int clk_idx, const struct rtcl_reg_set *reg)
 353 {
 354         unsigned long vpflags;
 355         unsigned long irqflags;
 356 /*
 357  * Runtime of this function (including locking)
 358  * CPU: up to 31000 cycles / up to 89 us at 350 MHz (half default speed)
 359  */
 360         spin_lock_irqsave(&rtcl_ccu->lock, irqflags);
 361         vpflags = dvpe();
 362         rtcl_839x_sram_set_rate(clk_idx, reg->ctrl0, reg->ctrl1);
 363         evpe(vpflags);
 364         spin_unlock_irqrestore(&rtcl_ccu->lock, irqflags);
 365
 366         return 0;
 367 }
 368
 369 static int rtcl_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
 370 {
 371         int tab_idx;
 372         struct rtcl_clk *clk = rtcl_hw_to_clk(hw);
 373         const struct rtcl_rtab_set *rtab = &rtcl_rtab_set[rtcl_ccu->soc][clk->idx];
 374         const struct rtcl_round_set *round = &rtcl_round_set[rtcl_ccu->soc][clk->idx];
 375
 376         if ((parent_rate != RTCL_XTAL_RATE) || (!rtcl_ccu->sram.vbase))
 377                 return -EINVAL;
 378 /*
 379  * Currently we do not know if SRAM is stable on these devices. Maybe someone
 380  * changes memory in this region and does not care about proper allocation. So
 381  * check if something might go wrong.
 382  */
 383         if (unlikely(*rtcl_ccu->sram.pmark != RTL_SRAM_MARKER)) {
 384                 dev_err(&rtcl_ccu->pdev->dev, "SRAM code lost\n");
 385                 return -EINVAL;
 386         }
 387
 388         tab_idx = (rate - round->min) / round->step;
 389         if ((tab_idx < 0) || (tab_idx >= rtab->count) || (rtab->rset[tab_idx].rate != rate))
 390                 return -EINVAL;
 391
 392         switch (rtcl_ccu->soc) {
 393         case RTCL_SOC838X:
 394                 return rtcl_838x_set_rate(clk->idx, &rtab->rset[tab_idx]);
 395         case RTCL_SOC839X:
 396                 return rtcl_839x_set_rate(clk->idx, &rtab->rset[tab_idx]);
 397         }
 398
 399         return -ENXIO;
 400 }
 401
 402 static long rtcl_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate)
 403 {
 404         struct rtcl_clk *clk = rtcl_hw_to_clk(hw);
 405         unsigned long rrate = max(clk->min, min(clk->max, rate));
 406         const struct rtcl_round_set *round = &rtcl_round_set[rtcl_ccu->soc][clk->idx];
 407
 408         rrate = ((rrate + (round->step >> 1)) / round->step) * round->step;
 409         rrate -= (rrate > clk->max) ? round->step : 0;
 410         rrate += (rrate < clk->min) ? round->step : 0;
 411
 412         return rrate;
 413 }
 414
 415 /*
 416  * Initialization functions to register the CCU and its clocks
 417  */
 418
 419 #define RTCL_SRAM_FUNC(SOC, PBASE, FN) ({                               \
 420         rtcl_##SOC##_sram_##FN = ((void *)&rtcl_##SOC##_dram_##FN       \
 421                                 - (void *)&rtcl_##SOC##_dram_start)     \
 422                                 + (void *)PBASE; })
 423
 424 static const struct clk_ops rtcl_clk_ops = {
 425         .set_rate = rtcl_set_rate,
 426         .round_rate = rtcl_round_rate,
 427         .recalc_rate = rtcl_recalc_rate,
 428 };
 429
 430 static void rtcl_unlock_registers(void)
 431 {
 432         u32 enable, reg;
 433
 434         if (rtcl_ccu->soc != RTCL_SOC838X)
 435                 return;
 436 /*
 437  * Some RTL838X devices are shipped with register access locked. In this case
 438  * we cannot read and/or write to LXB or SW PLL registers. As there is no real
 439  * benefit of always unlocking/locking these registers just open up everything.
 440  */
 441         enable = RTL838X_INT_RW_CTRL_READ_EN | RTL838X_INT_RW_CTRL_WRITE_EN;
 442         reg = ioread32((void *)RTL_SW_CORE_BASE + RTL838X_INT_RW_CTRL);
 443         if ((reg & enable) != enable) {
 444                 reg |= enable;
 445                 iowrite32(reg, (void *)RTL_SW_CORE_BASE + RTL838X_INT_RW_CTRL);
 446                 pr_warn("%s: registers unlocked\n", __func__);
 447         }
 448 }
 449
 450 static int rtcl_ccu_create(struct device_node *np)
 451 {
 452         int soc;
 453
 454         if (of_device_is_compatible(np, "realtek,rtl8380-clock"))
 455                 soc = RTCL_SOC838X;
 456         else if (of_device_is_compatible(np, "realtek,rtl8390-clock"))
 457                 soc = RTCL_SOC839X;
 458         else
 459                 return -ENXIO;
 460
 461         rtcl_ccu = kzalloc(sizeof(*rtcl_ccu), GFP_KERNEL);
 462         if (IS_ERR(rtcl_ccu))
 463                 return -ENOMEM;
 464
 465         rtcl_ccu->np = np;
 466         rtcl_ccu->soc = soc;
 467         rtcl_ccu->dram.type = RTL_MC_MCR_DRAMTYPE(ioread32((void *)RTL_SOC_BASE + RTL_MC_MCR));
 468         rtcl_ccu->dram.buswidth = RTL_MC_DCR_BUSWIDTH(ioread32((void *)RTL_SOC_BASE + RTL_MC_DCR));
 469         spin_lock_init(&rtcl_ccu->lock);
 470
 471         return 0;
 472 }
 473
 474 int rtcl_register_clkhw(int clk_idx)
 475 {
 476         int ret;
 477         struct clk *clk;
 478         struct clk_init_data hw_init = { };
 479         struct clk_parent_data parent_data = { };
 480         struct rtcl_clk *rclk = &rtcl_ccu->clks[clk_idx];
 481
 482         rclk->idx = clk_idx;
 483         rclk->hw.init = &hw_init;
 484
 485         parent_data.fw_name = rtcl_clk_info[clk_idx].parent_name;
 486
 487         hw_init.num_parents = 1;
 488         hw_init.ops = &rtcl_clk_ops;
 489         hw_init.parent_data = &parent_data;
 490         hw_init.name = rtcl_clk_info[clk_idx].name;
 491
 492         ret = of_clk_hw_register(rtcl_ccu->np, &rclk->hw);
 493         if (ret)
 494                 return ret;
 495
 496         clk_hw_register_clkdev(&rclk->hw, rtcl_clk_info[clk_idx].name, NULL);
 497
 498         clk = clk_get(NULL, rtcl_clk_info[clk_idx].name);
 499         rclk->startup = clk_get_rate(clk);
 500         clk_put(clk);
 501
 502         switch (clk_idx) {
 503         case CLK_CPU:
 504                 rclk->min = rtcl_round_set[rtcl_ccu->soc][clk_idx].min;
 505                 rclk->max = rtcl_round_set[rtcl_ccu->soc][clk_idx].max;
 506                 break;
 507         default:
 508 /*
 509  * TODO: This driver supports PLL reclocking and nothing else. Additional
 510  * required steps for non CPU PLLs are missing. E.g. if we want to change memory
 511  * clocks the right way we must adapt a lot of other settings. This includes
 512  * MCR and DTRx timing registers (0xb80001000, 0xb8001008, ...) and a DLL reset
 513  * so that hardware operates in the allowed limits. This is far too complex
 514  * without official support. Avoid this for now.
 515  */
 516                 rclk->min = rclk->max = rclk->startup;
 517                 break;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static struct clk_hw *rtcl_get_clkhw(struct of_phandle_args *clkspec, void *prv)
 524 {
 525         unsigned int idx = clkspec->args[0];
 526
 527         if (idx >= CLK_COUNT) {
 528                 pr_err("%s: Invalid index %u\n", __func__, idx);
 529                 return ERR_PTR(-EINVAL);
 530         }
 531
 532         return &rtcl_ccu->clks[idx].hw;
 533 }
 534
 535 static int rtcl_ccu_register_clocks(void)
 536 {
 537         struct clk *clk;
 538         int clk_idx, ret;
 539
 540         clk = clk_register_fixed_rate(NULL, "xtal_clk", NULL, 0, RTCL_XTAL_RATE);
 541         clk_register_clkdev(clk, "xtal_clk", NULL);
 542
 543         for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) {
 544                 ret = rtcl_register_clkhw(clk_idx);
 545                 if (ret) {
 546                         pr_err("%s: Couldn't register %s clock\n",
 547                                 __func__, rtcl_clk_info[clk_idx].display_name);
 548                         goto err_hw_unregister;
 549                 }
 550         }
 551
 552         ret = of_clk_add_hw_provider(rtcl_ccu->np, rtcl_get_clkhw, rtcl_ccu);
 553         if (ret) {
 554                 pr_err("%s: Couldn't register clock provider of %s\n",
 555                         __func__, of_node_full_name(rtcl_ccu->np));
 556                 goto err_hw_unregister;
 557         }
 558
 559         return 0;
 560
 561 err_hw_unregister:
 562         for (--clk_idx; clk_idx >= 0; --clk_idx)
 563                 clk_hw_unregister(&rtcl_ccu->clks[clk_idx].hw);
 564
 565         return ret;
 566 }
 567
 568 int rtcl_init_sram(void)
 569 {
 570         struct gen_pool *sram_pool;
 571         phys_addr_t sram_pbase;
 572         unsigned long sram_vbase;
 573         struct device_node *node;
 574         struct platform_device *pdev = NULL;
 575         void *dram_start;
 576         int dram_size;
 577         const char *wrn = ", rate setting disabled.\n";
 578
 579         switch (rtcl_ccu->soc) {
 580         case RTCL_SOC838X:
 581                 dram_start = &rtcl_838x_dram_start;
 582                 dram_size = rtcl_838x_dram_size;
 583                 break;
 584         case RTCL_SOC839X:
 585                 dram_start = &rtcl_839x_dram_start;
 586                 dram_size = rtcl_839x_dram_size;
 587                 break;
 588         default:
 589                 return -ENXIO;
 590         }
 591
 592         for_each_compatible_node(node, NULL, "mmio-sram") {
 593                 pdev = of_find_device_by_node(node);
 594                 if (pdev) {
 595                         of_node_put(node);
 596                         break;
 597                 }
 598         }
 599
 600         if (!pdev) {
 601                 dev_warn(&rtcl_ccu->pdev->dev, "no SRAM device found%s", wrn);
 602                 return -ENXIO;
 603         }
 604
 605         sram_pool = gen_pool_get(&pdev->dev, NULL);
 606         if (!sram_pool) {
 607                 dev_warn(&rtcl_ccu->pdev->dev, "SRAM pool unavailable%s", wrn);
 608                 goto err_put_device;
 609         }
 610
 611         sram_vbase = gen_pool_alloc(sram_pool, dram_size);
 612         if (!sram_vbase) {
 613                 dev_warn(&rtcl_ccu->pdev->dev, "can not allocate SRAM%s", wrn);
 614                 goto err_put_device;
 615         }
 616
 617         sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_vbase);
 618         memcpy((void *)sram_pbase, dram_start, dram_size);
 619         flush_icache_range((unsigned long)sram_pbase, (unsigned long)(sram_pbase + dram_size));
 620
 621         switch (rtcl_ccu->soc) {
 622         case RTCL_SOC838X:
 623                 RTCL_SRAM_FUNC(838x, sram_pbase, set_rate);
 624                 break;
 625         case RTCL_SOC839X:
 626                 RTCL_SRAM_FUNC(839x, sram_pbase, set_rate);
 627                 break;
 628         }
 629
 630         rtcl_ccu->sram.pmark = (int *)((void *)sram_pbase + (dram_size - 4));
 631         rtcl_ccu->sram.vbase = sram_vbase;
 632
 633         return 0;
 634
 635 err_put_device:
 636         put_device(&pdev->dev);
 637
 638         return -ENXIO;
 639 }
 640
 641 void rtcl_ccu_log_early(void)
 642 {
 643         int clk_idx;
 644         char meminfo[80], clkinfo[255], msg[255] = "rtl83xx-clk: initialized";
 645
 646         sprintf(meminfo, " (%d Bit DDR%d)", rtcl_ccu->dram.buswidth, rtcl_ccu->dram.type);
 647         for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) {
 648                 sprintf(clkinfo, ", %s %lu MHz", rtcl_clk_info[clk_idx].display_name,
 649                         rtcl_ccu->clks[clk_idx].startup / 1000000);
 650                 if (clk_idx == CLK_MEM)
 651                         strcat(clkinfo, meminfo);
 652                 strcat(msg, clkinfo);
 653         }
 654         pr_info("%s\n", msg);
 655 }
 656
 657 void rtcl_ccu_log_late(void)
 658 {
 659         int clk_idx;
 660         struct rtcl_clk *rclk;
 661         bool overclock = false;
 662         char clkinfo[80], msg[255] = "rate setting enabled";
 663
 664         for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) {
 665                 rclk = &rtcl_ccu->clks[clk_idx];
 666                 if (rclk->min == rclk->max)
 667                         continue;
 668                 overclock |= rclk->max > rclk->startup;
 669                 sprintf(clkinfo, ", %s %lu-%lu MHz", rtcl_clk_info[clk_idx].display_name,
 670                         rclk->min / 1000000, rclk->max / 1000000);
 671                 strcat(msg, clkinfo);
 672         }
 673         if (overclock)
 674                 strcat(msg, ", OVERCLOCK AT OWN RISK");
 675
 676         dev_info(&rtcl_ccu->pdev->dev, "%s\n", msg);
 677 }
 678
 679 /*
 680  * Early registration: This module provides core startup clocks that are needed
 681  * for generic SOC init and for further builtin devices (e.g. UART). Register
 682  * asap via clock framework.
 683  */
 684
 685 static void __init rtcl_probe_early(struct device_node *np)
 686 {
 687         if (rtcl_ccu_create(np))
 688                 return;
 689
 690         rtcl_unlock_registers();
 691         if (rtcl_ccu_register_clocks())
 692                 kfree(rtcl_ccu);
 693         else
 694                 rtcl_ccu_log_early();
 695 }
 696
 697 CLK_OF_DECLARE_DRIVER(rtl838x_clk, "realtek,rtl8380-clock", rtcl_probe_early);
 698 CLK_OF_DECLARE_DRIVER(rtl839x_clk, "realtek,rtl8390-clock", rtcl_probe_early);
 699
 700 /*
 701  * Late registration: Finally register as normal platform driver. At this point
 702  * we can make use of other modules like SRAM.
 703  */
 704
 705 static const struct of_device_id rtcl_dt_ids[] = {
 706         { .compatible = "realtek,rtl8380-clock" },
 707         { .compatible = "realtek,rtl8390-clock" },
 708         {}
 709 };
 710
 711 static int rtcl_probe_late(struct platform_device *pdev)
 712 {
 713         int ret;
 714
 715         if (!rtcl_ccu) {
 716                 dev_err(&pdev->dev, "early initialization not run");
 717                 return -ENXIO;
 718         }
 719         rtcl_ccu->pdev = pdev;
 720         ret = rtcl_init_sram();
 721         if (ret)
 722                 return ret;
 723
 724         rtcl_ccu_log_late();
 725
 726         return 0;
 727 }
 728
 729 static struct platform_driver rtcl_platform_driver = {
 730         .driver = {
 731                 .name = "rtl83xx-clk",
 732                 .of_match_table = rtcl_dt_ids,
 733         },
 734         .probe = rtcl_probe_late,
 735 };
 736
 737 static int __init rtcl_init_subsys(void)
 738 {
 739         return platform_driver_register(&rtcl_platform_driver);
 740 }
 741
 742 /*
 743  * The driver does not know when SRAM module has finally loaded. With an
 744  * arch_initcall() we might overtake SRAM initialization. Be polite and give the
 745  * system a little more time.
 746  */
 747
 748 subsys_initcall(rtcl_init_subsys);